Home
last modified time | relevance | path

Searched refs:L_CLKGEN0 (Results 1 – 25 of 49) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c2697 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2698 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2699 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2700 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2703 W2BYTEMSK(L_CLKGEN0(0x58), 0x0001, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2708 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2709 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2710 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2711 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2714 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
[all …]
H A DhalPNL.h203 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c2697 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2698 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2699 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2700 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2703 W2BYTEMSK(L_CLKGEN0(0x58), 0x0001, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2708 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2709 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2710 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2711 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2714 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c2708 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2709 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2710 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2711 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2714 W2BYTEMSK(L_CLKGEN0(0x58), 0x0001, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2719 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2720 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2721 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2722 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2725 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c3469 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3470 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3471 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3473 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
3484 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0030, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
3499 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3500 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3501 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3503 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3515 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
[all …]
H A DhalPNL.h205 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c3496 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3497 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3498 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3500 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
3511 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0030, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
3526 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3527 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3528 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3530 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3542 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
[all …]
H A DhalPNL.h205 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c1778 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
1779 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1780 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1782 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft in MHal_PNL_Init_XC_Clk()
1785 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
1786 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1787 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1789 W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo in MHal_PNL_Init_XC_Clk()
1790 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
1791 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
[all …]
H A DhalPNL.h193 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c1778 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
1779 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1780 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1782 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft in MHal_PNL_Init_XC_Clk()
1785 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
1786 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1787 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1789 W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo in MHal_PNL_Init_XC_Clk()
1790 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
1791 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c2445 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL_DIV_2, CKG_ODCLK_MASK); // select source tobe L… in MHal_PNL_Init_XC_Clk()
2447 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
2448 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
2449 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
2450 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft in MHal_PNL_Init_XC_Clk()
2452 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2460 W2BYTE(L_CLKGEN0(0x63), 0x0001); //[11:8]ckg_tx_mod_osd[4:0]osd2mod in MHal_PNL_Init_XC_Clk()
2462 W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc in MHal_PNL_Init_XC_Clk()
2507 W2BYTE(L_CLKGEN0(0x7A),0x01C0); in MHal_PNL_Init_XC_Clk()
2516 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod in MHal_PNL_Init_XC_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.c2166 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
2167 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
2168 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
2169 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft in MHal_PNL_Init_XC_Clk()
2171 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2179 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod in MHal_PNL_Init_XC_Clk()
2181 W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc in MHal_PNL_Init_XC_Clk()
2189 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod in MHal_PNL_Init_XC_Clk()
2194 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h196 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1431 W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo in MHal_PNL_Init_XC_Clk()
1432 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
1434 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h195 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1431 W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo in MHal_PNL_Init_XC_Clk()
1432 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
1434 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h195 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c4975 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
4976 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
4977 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
4980 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
4981 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
4982 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
5084 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
5085 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
5090 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
5099 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c5607 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
5608 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
5609 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
5612 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
5613 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
5614 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
5716 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
5717 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
5722 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
5731 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c6082 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6083 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6084 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6087 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6088 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6089 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6191 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
6192 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
6197 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
6206 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c6102 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6103 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6104 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6107 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6108 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6109 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6211 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
6212 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
6217 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
6226 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c5668 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
5669 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
5670 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
5673 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
5674 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
5675 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
5777 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
5778 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
5783 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
5792 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c6393 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6394 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6395 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6398 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6399 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6400 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6502 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
6503 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
6508 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
6517 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c6393 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6394 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert in MHal_CLKGEN_FRC_Init()
6395 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock in MHal_CLKGEN_FRC_Init()
6398 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK in MHal_CLKGEN_FRC_Init()
6399 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6400 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6502 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_CLKGEN_FRC_Bypass_Enable()
6503 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_CLKGEN_FRC_Bypass_Enable()
6508 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_CLKGEN_FRC_Bypass_Enable()
6517 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out in MHal_CLKGEN_FRC_Bypass_Enable()
[all …]

12