Lines Matching refs:L_CLKGEN0

2445 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL_DIV_2, CKG_ODCLK_MASK);      // select source tobe L…  in MHal_PNL_Init_XC_Clk()
2447 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK);      // select source tobe LPLL cl…  in MHal_PNL_Init_XC_Clk()
2448     W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT);               // clock not invert  in MHal_PNL_Init_XC_Clk()
2449     W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED);                // enable clock  in MHal_PNL_Init_XC_Clk()
2450     W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0);      //  reg_ckg_odclk_mft  in MHal_PNL_Init_XC_Clk()
2452     W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod  in MHal_PNL_Init_XC_Clk()
2460         W2BYTE(L_CLKGEN0(0x63), 0x0001);   //[11:8]ckg_tx_mod_osd[4:0]osd2mod  in MHal_PNL_Init_XC_Clk()
2462         W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc  in MHal_PNL_Init_XC_Clk()
2507             W2BYTE(L_CLKGEN0(0x7A),0x01C0);  in MHal_PNL_Init_XC_Clk()
2516             W2BYTE(L_CLKGEN0(0x63), 0x0410);   //[11:8]ckg_tx_mod_osd[4:0]osd2mod  in MHal_PNL_Init_XC_Clk()
2521             W2BYTE(L_CLKGEN0(0x63),0x0001); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod  in MHal_PNL_Init_XC_Clk()