Lines Matching refs:L_CLKGEN0
3469 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3470 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3471 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3473 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
3484 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0030, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
3499 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3500 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3501 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3503 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3515 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
3530 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3531 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3532 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
3534 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
3581 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0… in MHal_PNL_Init_XC_Clk()
3591 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0050, 0x00F0); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0… in MHal_PNL_Init_XC_Clk()
3620 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL cl… in MHal_PNL_Init_XC_Clk()
3621 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
3622 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
3623 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft in MHal_PNL_Init_XC_Clk()
3625 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
3634 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod in MHal_PNL_Init_XC_Clk()
3636 W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc in MHal_PNL_Init_XC_Clk()
3644 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod in MHal_PNL_Init_XC_Clk()
3649 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
5234 W2BYTEMSK(L_CLKGEN0(CLKGEN0SettingTBL_Video[u8CLKTblIndex][indexCounter].address), in _MHal_PNL_DumpVideoClkTable()
5281 W2BYTEMSK(L_CLKGEN0(CLKGEN0SettingTBL_OSD[u8CLKTblIndex][indexCounter].address), in _MHal_PNL_DumpOSDClkTable()