1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _HAL_PNL_C_
79 #define _HAL_PNL_C_
80
81 //-------------------------------------------------------------------------------------------------
82 // Include Files
83 //-------------------------------------------------------------------------------------------------
84
85 #include "MsCommon.h"
86 #include "MsTypes.h"
87 #include "utopia.h"
88 #include "utopia_dapi.h"
89 #include "apiPNL.h"
90 #include "apiPNL_v2.h"
91 #include "drvPNL.h"
92 #include "halPNL.h"
93 #include "PNL_private.h"
94 #include "pnl_hwreg_utility2.h"
95 #include "Messi_pnl_lpll_tbl.h"
96
97 #ifdef MSOS_TYPE_LINUX_KERNEL
98 #include <linux/string.h>
99 #include <linux/delay.h>
100 #include <asm/div64.h>
101 #else
102 #include "string.h"
103 #define do_div(x,y) ((x)/=(y))
104 #endif
105
106 //-------------------------------------------------------------------------------------------------
107 // Driver Compiler Options
108 //-------------------------------------------------------------------------------------------------
109
110 //-------------------------------------------------------------------------------------------------
111 // Local Defines
112 //-------------------------------------------------------------------------------------------------
113
114 #define UNUSED(x) (x=x)
115 #if 1
116 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) printf("PNL:"_fmt, ##_args); }
117 #define HAL_MOD_CAL_DBG(x) //x
118 #else
119 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { }
120 #endif
121
122 #define DAC_LPLL_ICTRL 0x0002
123 #define LVDS_LPLL_ICTRL 0x0001
124
125 //Get MOD calibration time
126 #define MOD_CAL_TIMER FALSE
127
128 //-------------------------------------------------------------------------------------------------
129 // Local Structurs
130 //-------------------------------------------------------------------------------------------------
131
132 //-------------------------------------------------------------------------------------------------
133 // Global Variables
134 //-------------------------------------------------------------------------------------------------
135 #define LANE_NUM_EACH_PINMAPPING_GROUP1 4
136 #define LANE_NUM_EACH_PINMAPPING_GROUP2 4
137 #define LANE_NUM_EACH_PINMAPPING_GROUP3 4
138 #define LANE_NUM_EACH_PINMAPPING_GROUP4 2
139
140 #define PINMAPPING_EXP 16
141 //-------------------------------------------------------------------------------------------------
142 // Local Variables
143 //-------------------------------------------------------------------------------------------------
144 MS_U8 LANE_AND_CLK_TBL[VBY1_CLK_TBL_ROW][3]=
145 { //lane(from) lane(to) bit(mask)
146 { 0, 3, 0x02, },
147 { 4, 6, 0x04, },
148 { 7, 9, 0x08, },
149 { 10, 13, 0x10, }
150 };
151 //-------------------------------------------------------------------------------------------------
152 // Debug Functions
153 //-------------------------------------------------------------------------------------------------
154
155 //-------------------------------------------------------------------------------------------------
156 // Local Functions
157 //-------------------------------------------------------------------------------------------------
158
159 static void _MHal_PNL_Set_Clk(void *pInstance,
160 MS_U8 u8LaneNum,
161 MS_U16 u16OutputOrder0_3,
162 MS_U16 u16OutputOrder4_7,
163 MS_U16 u16OutputOrder8_11,
164 MS_U16 u16OutputOrder12_13);
165
166 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance);
167 //-------------------------------------------------------------------------------------------------
168 // Global Function
169 //-------------------------------------------------------------------------------------------------
170 /**
171 * @brief: Power On MOD. but not mutex protected
172 *
173 */
MHal_MOD_PowerOn(void * pInstance,MS_BOOL bEn,MS_U8 u8LPLL_Type,MS_U8 DualModeType,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)174 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
175 {
176 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
177 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
178 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
179 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
180
181 if( bEn )
182 {
183 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8));
184
185 //analog MOD power down. 1: power down, 0: power up
186 // For Mod2 no output signel
187 ///////////////////////////////////////////////////
188
189 //2. Power on MOD (current and regulator)
190 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0));
191 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8));
192
193 //enable ib, enable ck
194 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1C, 0x1C);
195 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0)));
196
197 // clock gen of dot-mini
198 if(u8LPLL_Type == E_PNL_TYPE_MINILVDS)
199 {
200 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x4400);
201 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x4400);
202 }
203 //// for osd dedicated output port, 1 port for video and 1 port for osd
204 else if((u8LPLL_Type == E_PNL_TYPE_HS_LVDS)&&
205 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
206 {
207 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
208 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
209 // [7:4]reg_ckg_dot_mini_pre_osd
210 }
211 else
212 {
213 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0000);
214 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0000);
215 }
216
217 // 3. 4. 5.
218 MHal_Output_LVDS_Pair_Setting(pInstance, DualModeType, u16OutputCFG0_7, u16OutputCFG8_15, u16OutputCFG16_21);
219 }
220 else
221 {
222 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8));
223 if(u8LPLL_Type !=E_PNL_TYPE_MINILVDS)
224 {
225 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: power up
226 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8));
227 }
228
229 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib, enable ck
230
231 // clock gen of dot-mini
232 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x1100);
233 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x1100);
234
235 }
236 return 1;
237 }
238
239 /**
240 * @brief: Setup the PVDD power 1:2.5V, 0:3.3V
241 *
242 */
MHal_MOD_PVDD_Power_Setting(void * pInstance,MS_BOOL bIs2p5)243 void MHal_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5)
244 {
245 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, ((bIs2p5)? BIT(6):0), BIT(6)); //MOD PVDD=1: 0.9
246 }
247
MHal_PNL_TCON_Init(void * pInstance)248 void MHal_PNL_TCON_Init(void *pInstance)
249 {
250
251 }
252
MHal_Shift_LVDS_Pair(void * pInstance,MS_U8 Type)253 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type)
254 {
255 if(Type == 1)
256 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LVDS Mode3
257 else
258 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6)));
259
260 }
261
MHal_Output_LVDS_Pair_Setting(void * pInstance,MS_U8 Type,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)262 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
263 {
264
265 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
266 {
267 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
268 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x1554);
269 }
270 else if(Type == LVDS_SINGLE_OUTPUT_A)
271 {
272 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
273 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
274 }
275 else if( Type == LVDS_SINGLE_OUTPUT_B)
276 {
277 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
278 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
279 }
280 else if( Type == LVDS_OUTPUT_User)
281 {
282 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16OutputCFG0_7);
283 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16OutputCFG8_15);
284 }
285 else
286 {
287 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
288 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
289 }
290
291 MsOS_DelayTask(2);
292
293
294 }
295
_MHal_PNL_Get_LaneNum(void * pInstance)296 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance)
297 {
298 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
299 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
300 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
301 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
302
303 MS_U8 u8LaneNum = 0;
304 //check lane num
305
306 return u8LaneNum;
307 }
308
_MHal_PNL_Set_Clk(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)309 static void _MHal_PNL_Set_Clk(void *pInstance,
310 MS_U8 Type,
311 MS_U16 u16OutputOrder0_3,
312 MS_U16 u16OutputOrder4_7,
313 MS_U16 u16OutputOrder8_11,
314 MS_U16 u16OutputOrder12_13)
315 {
316 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
317 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
318 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
319 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
320
321 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
322 {
323 MS_U8 u8Clk = 0;
324 MS_U8 u8LaneNum = 0;
325 MS_BOOL bSkip = TRUE;
326 MS_U8 u8Count = 0;
327 MS_U8 u8Count1 = 0;
328 MS_U8 u8StartLane = 0;
329
330 //check lane num
331 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
332 if(u8LaneNum!=0)
333 {
334 bSkip = FALSE;
335 }
336 else
337 {
338 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //open all clk
339 bSkip = TRUE;
340 }
341
342 //count clk
343 if(!bSkip)
344 {
345 u8Clk = 0;
346 u8StartLane = 0;
347 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP1) ; u8Count++ )
348 {//lane 0 - lane 3
349 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
350 {
351 u8Count1 = 0;
352 do
353 {
354 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
355 {
356 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
357 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
358 break;
359 }
360 u8Count1 ++;
361 }
362 while(u8Count1<VBY1_CLK_TBL_ROW);
363 }
364 u16OutputOrder0_3 /= PINMAPPING_EXP;
365 }
366
367 u8StartLane = 4;
368 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP2) ; u8Count++ )
369 {//lane 4 - lane 7
370 if( ( u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
371 {
372 u8Count1 = 0;
373 do
374 {
375 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
376 {
377 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
378 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
379 break;
380 }
381 u8Count1 ++;
382 }
383 while(u8Count1<VBY1_CLK_TBL_ROW);
384 }
385 u16OutputOrder4_7 /= PINMAPPING_EXP;
386 }
387
388 u8StartLane = 8;
389 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP3) ; u8Count++ )
390 {//lane 8 - lane 11
391 if( ( u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
392 {
393 u8Count1 = 0;
394 do
395 {
396 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
397 {
398 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
399 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
400 break;
401 }
402 u8Count1 ++;
403 }
404 while(u8Count1<VBY1_CLK_TBL_ROW);
405 }
406 u16OutputOrder8_11 /= PINMAPPING_EXP;
407
408 }
409
410 u8StartLane = 12;
411 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP4) ; u8Count++ )
412 {//lane 12 - lane 13
413 if( ( u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
414 {
415 u8Count1 = 0;
416 do
417 {
418 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
419 {
420 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
421 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
422 break;
423 }
424 u8Count1 ++;
425 }
426 while(u8Count1<VBY1_CLK_TBL_ROW);
427 }
428 u16OutputOrder12_13 /= PINMAPPING_EXP;
429 }
430
431 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u8Clk, 0x1F);
432 }
433 }
434 else
435 {
436 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
437 }
438 }
439
MHal_Output_Channel_Order(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)440 void MHal_Output_Channel_Order(void *pInstance,
441 MS_U8 Type,
442 MS_U16 u16OutputOrder0_3,
443 MS_U16 u16OutputOrder4_7,
444 MS_U16 u16OutputOrder8_11,
445 MS_U16 u16OutputOrder12_13)
446 {
447 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
448 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
449 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
450 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
451
452 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
453 {
454 MOD_W2BYTE(REG_MOD_BK00_08_L, u16OutputOrder0_3);
455 MOD_W2BYTE(REG_MOD_BK00_09_L, u16OutputOrder4_7);
456 MOD_W2BYTE(REG_MOD_BK00_0A_L, u16OutputOrder8_11);
457 MOD_W2BYTE(REG_MOD_BK00_0B_L, u16OutputOrder12_13);
458 }
459 else
460 {
461 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
462 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
463 {
464 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
465 {
466 MOD_W2BYTE(REG_MOD_BK00_08_L, 0xDCBA);
467 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x6420);
468 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7531);
469 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0098);
470 }
471 else
472 {
473 MOD_W2BYTE(REG_MOD_BK00_08_L, 0xDCBA);
474 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x3210);
475 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7654);
476 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0098);
477 }
478 }
479 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
480 {//LVDS
481 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x10DC);
482 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x5432);
483 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x9876);
484 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x00BA);
485 }
486 else
487 {
488 MOD_W2BYTE(REG_MOD_BK00_08_L, 0xDCBA);
489 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x3210);
490 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7654);
491 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0098);
492 }
493 }
494
495 }
496
MHal_PQ_Clock_Gen_For_Gamma(void * pInstance)497 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance)
498 {
499 W2BYTEMSK(REG_CLKGEN0_52_L, 0x00, 0x07);
500 }
501
MHal_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)502 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping)
503 {
504 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
505 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
506
507 if(u8Mapping & GAMMA_MAPPING)
508 {
509 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_74_L, (u8Mapping & GAMMA_10BIT_MAPPING)? BIT(15):0, BIT(15));
510 }
511 else
512 {
513 PNL_ASSERT(0, "Invalid eSupportGammaMapMode [%d] Passed to [%s], please make sure the u8Mapping[%d] is valid\n.",
514 u8Mapping, __FUNCTION__, u8Mapping);
515 }
516 }
517
Hal_VOP_Is_GammaMappingMode_enable(void * pInstance)518 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance)
519 {
520 // Only support 1024 entry
521 return TRUE;
522 }
523
524 // After A5, 8 bit mode only support burst write!!!
Hal_VOP_Is_GammaSupportSignalWrite(void * pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)525 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)
526 {
527 if( u8Mapping == E_DRVPNL_GAMMA_10BIT_MAPPING )
528 return TRUE;
529 else
530 return FALSE;
531 }
532
533
hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)534 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
535 {
536 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
537 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
538
539 MS_U16 u16Delay = 0xFFFF;
540
541 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write [ch %d][addr 0x%x]: 0x%x \n", u8Channel, u16Addr, u16GammaValue);
542
543 if (!bBurstWrite )
544 {
545 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
546 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
547
548 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6C_L, u16Addr, 0x3FF); // set address port
549 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_6E_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
550
551 // kick off write
552 switch(u8Channel)
553 {
554 case 0: // Red
555 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(5), BIT(5));
556 break;
557
558 case 1: // Green
559 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(6), BIT(6));
560 break;
561
562 case 2: // Blue
563 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(7), BIT(7));
564 break;
565 }
566
567 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
568 }
569 else
570 {
571
572 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6E_L, u16GammaValue, 0xFFF);
573 }
574
575
576 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
577 }
578
579
hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)580 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
581 {
582 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
583 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
584
585 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of SC%u %d is 0x%x\n", (unsigned int)pPNLInstancePrivate->u32DeviceID, u8Channel, u16MaxGammaValue);
586
587 switch(u8Channel)
588 {
589 case 0: // max. Red
590 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7A_L , u16MaxGammaValue, 0xFFF); // max. base 0
591 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7B_L , u16MaxGammaValue, 0xFFF); // max. base 1
592 break;
593
594 case 1: // max. Green
595 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7C_L , u16MaxGammaValue, 0xFFF); // max. base 0
596 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 1
597 break;
598
599 case 2: //max. Blue
600 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 0
601 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
602 break;
603 }
604
605 }
606
607 /////////////////////////////////////////////////////////////////////////////
608 // Gamma format (12 bit LUT)
609 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
610 // 1 set uses 2 bytes of memory.
611 //
612 // [T2 and before ] N = 256
613 // [T3] N = 256 or 1024
614 // ______________________________________________________________________________
615 // Byte | 0 1 2 n-1 n
616 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
617 // 3:0 3:0 11:4 11:4 3:0 11:4
618 //
619
Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)620 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
621 {
622 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
623 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
624
625 MS_U16 u16Addr = 0;
626 MS_U16 u16CodeTableIndex = u16Addr/2*3;
627 MS_U16 u16GammaValue = 0;
628 MS_U16 u16MaxGammaValue = 0;
629 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
630 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
631 #if 0 //The patch for Messi Burst Write bug. Mantis: 1111420
632 bUsingBurstWrite=FALSE;
633 #endif
634
635 // Go to burst write if not support
636 if ( bUsingBurstWrite )
637 {
638 // 1. initial burst write address, LUT_ADDR[7:0]
639 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
640
641 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
642 switch(u8Channel)
643 {
644 case 0: // Red
645 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
646 break;
647
648 case 1: // Green
649 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
650 break;
651
652 case 2: // Blue
653 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
654 break;
655 }
656
657 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
658 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
659
660 }
661
662 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
663 // write gamma table per one channel
664 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
665 {
666 // gamma x
667 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
668 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
669
670 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
671 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
672
673 if(u16MaxGammaValue < u16GammaValue)
674 {
675 u16MaxGammaValue = u16GammaValue;
676 }
677
678 // write gamma value
679 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
680 u16Addr++;
681
682 // gamma x+1
683 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
684 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
685
686 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
687
688 if(u16MaxGammaValue < u16GammaValue)
689 {
690 u16MaxGammaValue = u16GammaValue;
691 }
692
693 // write gamma value
694 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
695 u16Addr++;
696 }
697
698 if ( bUsingBurstWrite )
699 {
700 // 5. after finish burst write data of one channel, disable burst write mode
701 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(0));
702 }
703
704 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
705 }
706 /////////////////////////////////////////////////////////////////////////////
707 // Gamma format (12 bit LUT)
708 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
709 // 1 set uses 2 bytes of memory.
710 //
711 // [T2 and before ] N = 256
712 // [T3] N = 256 or 1024
713 // ______________________________________________________________________________
714 // Byte | 0 1 2 n-1 n
715 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
716 // 3:0 3:0 11:4 11:4 3:0 11:4
717 //
718 #ifdef MONACO_SC2
Hal_PNL_Set12BitGammaPerChannel_SC2(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)719 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
720 {
721 MS_U16 u16Addr = 0;
722 MS_U16 u16CodeTableIndex = u16Addr/2*3;
723 MS_U16 u16GammaValue = 0;
724 MS_U16 u16MaxGammaValue = 0;
725 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
726 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
727 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
728 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
729
730 // Go to burst write if not support
731 if ( bUsingBurstWrite )
732 {
733 // 1. initial burst write address, LUT_ADDR[7:0]
734 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
735
736 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
737 switch(u8Channel)
738 {
739 case 0: // Red
740 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
741 break;
742
743 case 1: // Green
744 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
745 break;
746
747 case 2: // Blue
748 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
749 break;
750 }
751
752 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
753 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
754
755 }
756
757 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
758 // write gamma table per one channel
759 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
760 {
761 // gamma x
762 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
763 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
764
765 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
766 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
767
768 if(u16MaxGammaValue < u16GammaValue)
769 {
770 u16MaxGammaValue = u16GammaValue;
771 }
772
773 // write gamma value
774 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
775 u16Addr++;
776
777 // gamma x+1
778 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
779 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
780
781 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
782
783 if(u16MaxGammaValue < u16GammaValue)
784 {
785 u16MaxGammaValue = u16GammaValue;
786 }
787
788 // write gamma value
789 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
790 u16Addr++;
791 }
792
793 if ( bUsingBurstWrite )
794 {
795 // 5. after finish burst write data of one channel, disable burst write mode
796 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(0));
797 }
798
799 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
800 }
801 #endif
802 // src : 1 (scaler lpll)
803 // src : 0 (frc lpll)
MHal_PNL_FRC_lpll_src_sel(void * pInstance,MS_U8 u8src)804 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src)
805 {
806 if (u8src > 1)
807 {
808 return FALSE;
809 }
810 else
811 {
812 //Not support FRCINSIDE(frc lpll) for Monet
813 #if 0
814
815 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F);
816 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8));
817 if(u8src==0)
818 {
819 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F);
820 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8));
821 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0
822 }
823 #endif
824 return TRUE;
825 }
826
827 }
828
_MHal_PNL_GetSupportedLPLLIndex(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz,PNL_LPLL_TYPE_SEL lpll_type_sel)829 static MS_U8 _MHal_PNL_GetSupportedLPLLIndex(void *pInstance,
830 PNL_TYPE eLPLL_Type,
831 PNL_MODE eLPLL_Mode,
832 MS_U64 ldHz, PNL_LPLL_TYPE_SEL lpll_type_sel)
833 {
834 MS_U8 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
835 #if defined (__aarch64__)
836 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
837 #else
838 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
839 #endif
840
841 switch(lpll_type_sel)
842 {
843 default:
844 case E_PNL_LPLL_VIDEO:
845 {
846 switch (eLPLL_Type)
847 {
848 case E_PNL_TYPE_TTL:
849 if ((ldHz >= 250000000) && (ldHz < 500000000))
850 {
851 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to50MHz;
852 }
853 else if((ldHz >= 500000000) && (ldHz < 750000000))
854 {
855 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_50to75MHz;
856 }
857 else
858 {
859 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_75to150MHz;
860 }
861
862 break;
863
864 case E_PNL_TYPE_LVDS:
865 switch (eLPLL_Mode)
866 {
867 case E_PNL_MODE_SINGLE:
868 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz;
869 break;
870
871 default:
872 case E_PNL_MODE_DUAL:
873 if ((ldHz >= 500000000) && (ldHz < 1150000000))
874 {
875 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to115MHz;
876 }
877 else
878 {
879 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_115to150MHz;
880 }
881 break;
882 }
883 break;
884
885 case E_PNL_TYPE_HS_LVDS:
886
887 if((ldHz >= 500000000) && (ldHz < 1150000000))
888 {
889 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz;
890 }
891 else
892 {
893 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz;
894 }
895
896 break;
897
898 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
899 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz;
900 break;
901 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
902 if((ldHz >= 500000000) && (ldHz < 1000000000))
903 {
904 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz;
905 }
906 else
907 {
908 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz;
909 }
910 break;
911
912 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
913 if((ldHz >= 500000000) && (ldHz < 1000000000))
914 {
915 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz;
916 }
917 else
918 {
919 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz;
920 }
921 break;
922
923 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
924 if((ldHz >= 500000000) && (ldHz < 666700000))
925 {
926 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to66_67MHz;
927 }
928 else
929 {
930 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz;
931 }
932 break;
933
934 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
935 if ((ldHz <= 500000000) && (ldHz < 666700000))
936 {
937 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz;
938 }
939 else if((ldHz >= 666700000) && (ldHz < 1333300000))
940 {
941 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz;
942 }
943 else
944 {
945 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz;
946 }
947 break;
948
949 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
950 if ((ldHz <= 500000000) && (ldHz < 670000000))
951 {
952 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz;
953 }
954 else if((ldHz >= 670000000) && (ldHz < 1330000000))
955 {
956 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz;
957 }
958 else
959 {
960 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz;
961 }
962 break;
963
964 case E_PNL_LPLL_EPI28_4P:
965 if((ldHz >= 800000000) && (ldHz < 1140000000))
966 {
967 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to114MHz;
968 }
969 else
970 {
971 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_114to150MHz;
972 }
973 break;
974
975 case E_PNL_LPLL_EPI28_6P:
976 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to150MHz;
977 break;
978
979 case E_PNL_LPLL_EPI28_8P:
980 if((ldHz >= 800000000) && (ldHz < 1140000000))
981 {
982 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to114MHz;
983 }
984 else
985 {
986 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_114to150MHz;
987 }
988 break;
989
990 default:
991 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
992 break;
993 }
994 }
995 break;
996
997 }
998 return u8SupportedLPLLIndex;
999 }
1000
_MHal_PNL_DumpLPLLTable(void * pInstance,MS_U8 LPLLTblIndex,PNL_LPLL_TYPE_SEL lpll_type_sel)1001 static void _MHal_PNL_DumpLPLLTable(void *pInstance, MS_U8 LPLLTblIndex, PNL_LPLL_TYPE_SEL lpll_type_sel)
1002 {
1003 if(lpll_type_sel == E_PNL_LPLL_VIDEO)
1004 {
1005 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_MAX)
1006 {
1007 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1008 return;
1009 }
1010
1011 int indexCounter = 0;
1012
1013 for(indexCounter = 0 ; indexCounter<LPLL_REG_NUM; indexCounter++)
1014 {
1015 if (LPLLSettingTBL[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1016 {
1017 MsOS_DelayTaskUs(LPLLSettingTBL[LPLLTblIndex][indexCounter].value);
1018 continue; // step forward to next register setting.
1019 }
1020
1021 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address),
1022 LPLLSettingTBL[LPLLTblIndex][indexCounter].value,
1023 LPLLSettingTBL[LPLLTblIndex][indexCounter].mask);
1024 }
1025 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1026 }
1027
1028 }
1029
MHal_PNL_Init_LPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)1030 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
1031 {
1032 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1033 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1034 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1035 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1036 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1037 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1038
1039 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_VIDEO);
1040
1041 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1042 {
1043 printf("Not Supported LPLL Type, skip LPLL Init\n");
1044 return;
1045 }
1046
1047 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_VIDEO);
1048
1049
1050 MHal_MOD_PVDD_Power_Setting(pInstance, pPNLResourcePrivate->sthalPNL._bPVDD_2V5); // Einstein is always use 3.3V PVDD Power.
1051 }
1052
MHal_PNL_Get_Loop_DIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1053 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1054 {
1055 MS_U16 u16loop_div = 0;
1056 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1057 #if defined (__aarch64__)
1058 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1059 #else
1060 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1061 #endif
1062 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1063
1064 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1065 {
1066 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1067 u16loop_div = 0 ;
1068 }
1069 else
1070 {
1071 u16loop_div = u16LoopDiv[u8SupportedLPLLLIndex];
1072 }
1073 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_div=%u\n", u16loop_div);
1074
1075 u16loop_div *= 2;
1076 return u16loop_div;
1077 }
1078
MHal_PNL_Get_LPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1079 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1080 {
1081 MS_U16 u16loop_gain = 0;
1082 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1083 #if defined (__aarch64__)
1084 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1085 #else
1086 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1087 #endif
1088 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1089
1090 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1091 {
1092 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1093 u16loop_gain = 0 ;
1094 }
1095 else
1096 {
1097 u16loop_gain = u16LoopGain[u8SupportedLPLLLIndex];
1098 }
1099 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_gain=%u\n", u16loop_gain);
1100 return u16loop_gain;
1101 }
1102
1103 #define SKIP_TIMING_CHANGE_CAP TRUE
Hal_PNL_SkipTimingChange_GetCaps(void * pInstance)1104 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance)
1105 {
1106 #if (SKIP_TIMING_CHANGE_CAP)
1107 return TRUE;
1108 #else
1109 return FALSE;
1110 #endif
1111 }
1112
MHal_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1113 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1114 {
1115 if (bSetMode == TRUE)
1116 {
1117 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15));
1118 }
1119 else
1120 {
1121 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15));
1122 }
1123 }
1124
MHal_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)1125 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo)
1126 {
1127 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1128 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1129 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1130 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1131
1132 if (lvdsresinfo.bEnable)
1133 {
1134 if (lvdsresinfo.u16channel & BIT(0)) // Channel A
1135 {
1136 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1137 {
1138 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15));
1139 }
1140 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1141 {
1142 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14));
1143 }
1144 }
1145 if (lvdsresinfo.u16channel & BIT(1)) // Channel B
1146 {
1147 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1148 {
1149 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13));
1150 }
1151 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1152 {
1153 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12));
1154 }
1155 }
1156
1157 }
1158 else
1159 {
1160 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12)));
1161
1162 }
1163 }
1164
1165 ////////////////////////////////////////////////////////////////////////
1166 // Turn OD function
1167 ////////////////////////////////////////////////////////////////////////
MHal_PNL_OverDriver_Init(void * pInstance,MS_PHY u32OD_MSB_Addr,MS_PHY u32OD_MSB_limit,MS_U32 u32OD_LSB_Addr,MS_U32 u32OD_LSB_limit,MS_U8 u8MIUSel)1168 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit, MS_U8 u8MIUSel)
1169 {
1170 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1171 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1172 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK16_61_L,u8MIUSel<<8,BIT(8)|BIT(9)); // OD MIU select
1173
1174 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_15_L, (MS_U16)(u32OD_MSB_Addr & 0xFFFF)); // OD MSB request base address
1175 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_16_L, (MS_U16)((u32OD_MSB_Addr >> 16) & 0x00FF), 0x00FF); // OD MSB request base address
1176 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_Addr >> 24) & 0x0003), 0x0003); // OD MSB request base address
1177 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_17_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD MSB request address limit
1178 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_18_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD MSB request address limit
1179 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_limit >> 24) & 0x0003)<<2, 0x000C); // OD MSB request address limit
1180 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_39_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer write address limit
1181 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer write address limit
1182 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3B_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer read address limit
1183 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3C_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer read address limit
1184 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_4F_L, (MS_U16)(u32OD_LSB_Addr & 0xFFFF)); // OD LSB request base address
1185 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_Addr >> 16) & 0x00FF), 0x00FF); // OD LSB request base address
1186 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_limit & 0x00FF) << 8), 0xFF00); // OD LSB request limit address
1187 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_51_L, (MS_U16)((u32OD_LSB_limit >> 8) & 0xFFFF)); // OD LSB request limit address
1188
1189 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1A_L, 0x4020); // OD request rFIFO limit threshold, priority threshold
1190 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1C_L, 0x4020); // OD request wFIFO limit threshold, priority threshold
1191 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x00, BIT(14)); // OD strength gradually bypass
1192 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x2F00, 0x3F00); // OD strength gradually slop
1193 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_12_L, 0x0C, 0xFF); // OD active threshold
1194
1195 }
1196
MHal_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1197 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable)
1198 {
1199 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1200 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1201
1202 // OD mode
1203 // OD used user weight to output blending directly
1204 // OD Enable
1205 if (bEnable)
1206 {
1207 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2D, 0x2F);
1208 }
1209 else
1210 {
1211 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2C, 0x2F);
1212 }
1213 }
1214
MHal_PNL_OverDriver_TBL(void * pInstance,MS_U8 u8ODTbl[1056])1215 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056])
1216 {
1217 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1218 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1219
1220 MS_U16 i;
1221 MS_U8 u8target;
1222 MS_BOOL bEnable;
1223
1224 bEnable = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, BIT(0));
1225 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x00, BIT(0)); // OD enable
1226 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x0E, 0x0E); // OD table SRAM enable, RGB channel
1227
1228 u8target= u8ODTbl[9];
1229 for (i=0; i<272; i++)
1230 {
1231 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_03_L, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
1232 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1233 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, BIT(15)));
1234 }
1235
1236 u8target= u8ODTbl[(272+19)];
1237 for (i=0; i<272; i++)
1238 {
1239 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_06_L, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
1240 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, (i|0x8000), 0x81FF);
1241 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, BIT(15)));
1242 }
1243
1244 u8target= u8ODTbl[(272*2+29)];
1245 for (i=0; i<256; i++)
1246 {
1247 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_09_L, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
1248 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
1249 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, BIT(15)));
1250 }
1251
1252 u8target= u8ODTbl[(272*2+256+39)];
1253 for (i=0; i<256; i++)
1254 {
1255 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0C_L, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
1256 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0B_L, (i|0x8000), 0x81FF);
1257 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0D_L, BIT(15)));
1258 }
1259
1260 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x00, 0x0E); // OD table SRAM enable, RGB channel
1261 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, bEnable, BIT(0)); // OD enable
1262 }
1263
_MHal_PNL_MOD_Swing_Refactor_AfterCAL(void * pInstance,MS_U16 u16Swing_Level)1264 MS_U16 _MHal_PNL_MOD_Swing_Refactor_AfterCAL(void *pInstance, MS_U16 u16Swing_Level)
1265 {
1266 MS_U8 u8ibcal = 0x00;
1267 MS_U16 u16AfterCal_value = 0;
1268 MS_U16 u16Cus_value = 0;
1269
1270 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1271 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1272 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1273 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1274 // =========
1275 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1276 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1277 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1278 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1279 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1280 // =========
1281 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1282 {
1283 default:
1284 case 0:
1285 u8ibcal = 0x15;
1286 break;
1287 case 1:
1288 u8ibcal = 0x1F;
1289 break;
1290 case 2:
1291 u8ibcal = 0x1A;
1292 break;
1293 case 3:
1294 u8ibcal = 0x10;
1295 break;
1296 }
1297 u16Cus_value = (u16Swing_Level) * (pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4)/(u8ibcal + 4);
1298 u16AfterCal_value = (u16Cus_value-40)/10+2;
1299
1300 HAL_MOD_CAL_DBG(printf("\r\n--Swing value after refactor = %d\n", u16AfterCal_value));
1301
1302 return u16AfterCal_value;
1303 }
1304
MHal_PNL_MODSwingRegToRealLevelValue(void * pInstance,MS_U16 u16SwingRegValue)1305 MS_U16 MHal_PNL_MODSwingRegToRealLevelValue(void *pInstance, MS_U16 u16SwingRegValue)
1306 {
1307 MS_U8 u8ibcal = 0x00;
1308 MS_U16 u16SwingRealLevelValue = 0;
1309 MS_U16 u16CusValue = 0;
1310 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1311 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1312 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1313 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1314 // =========
1315 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1316 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1317 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1318 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1319 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1320 // =========
1321 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1322 {
1323 default:
1324 case 0:
1325 u8ibcal = 0x15;
1326 break;
1327 case 1:
1328 u8ibcal = 0x1F;
1329 break;
1330 case 2:
1331 u8ibcal = 0x1A;
1332 break;
1333 case 3:
1334 u8ibcal = 0x10;
1335 break;
1336 }
1337
1338 u16CusValue = ((u16SwingRegValue-2)*10)+40;
1339 u16SwingRealLevelValue=(u16CusValue*(u8ibcal + 4))/(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4);
1340
1341 HAL_MOD_CAL_DBG(printf("\r\n--Swing Real Level Value = %d\n", u16SwingRealLevelValue));
1342
1343 return u16SwingRealLevelValue;
1344 }
1345
MHal_PNL_MOD_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)1346 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level)
1347 {
1348 MS_BOOL bStatus = FALSE;
1349
1350 MS_U16 u16ValidSwing = 0;
1351 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1352 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1353 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1354 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1355
1356 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)||
1357 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS))
1358 {
1359 if(u16Swing_Level>600)
1360 u16Swing_Level=600;
1361 if(u16Swing_Level<40)
1362 u16Swing_Level=40;
1363
1364 u16ValidSwing = _MHal_PNL_MOD_Swing_Refactor_AfterCAL(pInstance, u16Swing_Level);
1365 }
1366 else
1367 {
1368 u16ValidSwing = u16Swing_Level;
1369 }
1370
1371 // Disable HW calibration keep mode first, to make SW icon value can write into register.
1372 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15)); // disable keep mode
1373
1374 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch0/1 calibration result
1375 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch2/3 calibration result
1376 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch4/5 calibration result
1377 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch6/7 calibration result
1378 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch8/9 calibration result
1379 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch10/11 calibration result
1380 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L,u16ValidSwing |(u16ValidSwing <<8)); // refine ch12/13 calibration result
1381
1382 bStatus = TRUE;
1383
1384 return bStatus;
1385 }
1386
1387 ////////////////////////////////////////////////////////////////////////
1388 // Turn Pre-Emphasis Current function
1389 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_PE_Current(void * pInstance,MS_U16 u16Current_Level)1390 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level)
1391 {
1392 MS_BOOL bStatus = FALSE;
1393 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
1394
1395 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,
1396 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1397 |(u16ValidCurrent << 12 )));
1398
1399 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,
1400 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1401 |(u16ValidCurrent << 12 )));
1402
1403 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,
1404 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1405 |(u16ValidCurrent << 12 )));
1406
1407 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,
1408 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1409 |(u16ValidCurrent << 12 )));
1410
1411 bStatus = TRUE;
1412
1413 return bStatus;
1414 }
1415
MHal_PNL_MOD_PECurrent_Setting(void * pInstance,MS_U16 u16Current_Level,MS_U16 u16Channel_Select)1416 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select)
1417 {
1418 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
1419 MS_U16 u16Ch00_03_mask,u16Ch04_07_mask,u16Ch08_11_mask,u16Ch12_15_mask = 0;
1420
1421 u16Ch00_03_mask = (((u16Channel_Select & BIT(0))? 0x000F:0x00)|((u16Channel_Select & BIT(1))? 0x00F0:0x00)
1422 |((u16Channel_Select & BIT(2))? 0x0F00:0x00)|((u16Channel_Select & BIT(3))? 0xF000:0x00));
1423 u16Ch04_07_mask = (((u16Channel_Select & BIT(4))? 0x000F:0x00)|((u16Channel_Select & BIT(5))? 0x00F0:0x00)
1424 |((u16Channel_Select & BIT(6))? 0x0F00:0x00)|((u16Channel_Select & BIT(7))? 0xF000:0x00));
1425 u16Ch08_11_mask = (((u16Channel_Select & BIT(8))? 0x000F:0x00)|((u16Channel_Select & BIT(9))? 0x00F0:0x00)
1426 |((u16Channel_Select & BIT(10))? 0x0F00:0x00)|((u16Channel_Select & BIT(11))? 0xF000:0x00));
1427 u16Ch12_15_mask = (((u16Channel_Select & BIT(12))? 0x000F:0x00)|((u16Channel_Select & BIT(13))? 0x00F0:0x00)
1428 |((u16Channel_Select & BIT(14))? 0x0F00:0x00)|((u16Channel_Select & BIT(15))? 0xF000:0x00));
1429
1430 if(u16Ch00_03_mask)
1431 {
1432 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L,
1433 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch00_03_mask);
1434 }
1435 else
1436 {
1437 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x00);
1438 }
1439
1440 if(u16Ch04_07_mask)
1441 {
1442 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L,
1443 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch04_07_mask);
1444 }
1445 else
1446 {
1447 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x00);
1448 }
1449
1450 if(u16Ch08_11_mask)
1451 {
1452 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L,
1453 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch08_11_mask);
1454 }
1455 else
1456 {
1457 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x00);
1458 }
1459
1460 if(u16Ch12_15_mask)
1461 {
1462 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L,
1463 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch12_15_mask);
1464 }
1465 else
1466 {
1467 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x00);
1468 }
1469 }
1470
1471 ////////////////////////////////////////////////////////////////////////
1472 // 1.Turn TTL low-power mode function
1473 // 2.Turn internal termination function
1474 // 3.Turn DRIVER BIAS OP function
1475 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_TTL_Resistor_OP(void * pInstance,MS_BOOL bEnble)1476 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL bEnble)
1477 {
1478 MS_BOOL bStatus = FALSE;
1479 if(bEnble)
1480 {
1481 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode
1482 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x001E, 0x001E);
1483
1484 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open)
1485 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F);
1486
1487 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP
1488 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F);
1489 }
1490 else
1491 {
1492 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode
1493 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x0000, 0x001E);
1494
1495 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close)
1496 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F);
1497
1498 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP
1499 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F);
1500 }
1501
1502 bStatus = TRUE;
1503 return bStatus;
1504 }
1505
MHal_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)1506 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam)
1507 {
1508 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1509 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1510 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1511 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1512 pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions = eParam;
1513 }
1514
MHal_PNL_Get_Output_MODE(void * pInstance)1515 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance)
1516 {
1517 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1518 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1519 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1520 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1521 PNL_OUTPUT_MODE eParam = pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions;
1522
1523 return eParam;
1524 }
1525
msReadEfuse(void * pInstance,MS_U8 u8Bank,MS_U32 u32Mask)1526 MS_U32 msReadEfuse(void *pInstance, MS_U8 u8Bank, MS_U32 u32Mask)
1527 {
1528 MS_U32 u32Result = 0;
1529 MS_U8 u8Count = 0;
1530
1531 W2BYTEMSK(0x2050, u8Bank<<2, BMASK(8:2)); /// reg28[8:2]Addr 6~0
1532 W2BYTEMSK(0x2050, BIT(13), BIT(13)); /// Reg28[13] Margin Read
1533 while(R2BYTEMSK(0x2050, BIT(13)) == BIT(13))
1534 {
1535 MsOS_DelayTask(1);
1536 u8Count ++;
1537
1538 if (u8Count >10)
1539 break;
1540 }
1541
1542 u32Result = (R4BYTE(0x2058)& u32Mask); /// reg2C,2D read value
1543 printf("[%s][%d]u32Result=%x, after mask u32Result=%x\n", __FUNCTION__, __LINE__, (unsigned int)R4BYTE(0x2058), (unsigned int)u32Result);
1544 return u32Result;
1545
1546 }
1547
msSetVBY1RconValue(void * pInstance)1548 void msSetVBY1RconValue(void *pInstance)
1549 {
1550 MS_U16 u16DefaultICON_Max = 40, u16DefaultICON_Min = 7;
1551 MS_U16 u16DefaultICON = 18;
1552 MS_U32 u32Mask = 0x3F;
1553 MS_BOOL bEfuseMode = FALSE;
1554 MS_U16 u16SwingOffset = 0; // by HW RD request
1555 MS_U16 u16temp = 0;
1556 if (msReadEfuse(pInstance, 0x4E, BIT(6)) == BIT(6))
1557 bEfuseMode = TRUE;
1558
1559
1560 // Disable HW calibration keep mode first, to make SW icon value can write into register.
1561 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
1562
1563 if (bEfuseMode)
1564 {
1565 if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) > u16DefaultICON_Max)
1566 u16temp = u16DefaultICON;
1567 else if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) < u16DefaultICON_Min)
1568 u16temp = u16DefaultICON;
1569 else
1570 u16temp = (MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset;
1571 }
1572 else
1573 {
1574 u16temp = u16DefaultICON;
1575 }
1576
1577 //ch0~ch13 rcon setting
1578 u16temp &= (u16temp&(MS_U16)u32Mask);
1579 printf("[%s][%d]u16temp= %x\n", __FUNCTION__, __LINE__, u16temp);
1580
1581 MOD_A_W2BYTE(REG_MOD_A_BK00_10_L, (u16temp<<8|u16temp));
1582 MOD_A_W2BYTE(REG_MOD_A_BK00_11_L, (u16temp<<8|u16temp));
1583 MOD_A_W2BYTE(REG_MOD_A_BK00_12_L, (u16temp<<8|u16temp));
1584 MOD_A_W2BYTE(REG_MOD_A_BK00_13_L, (u16temp<<8|u16temp));
1585 MOD_A_W2BYTE(REG_MOD_A_BK00_14_L, (u16temp<<8|u16temp));
1586 MOD_A_W2BYTE(REG_MOD_A_BK00_15_L, (u16temp<<8|u16temp));
1587 MOD_A_W2BYTE(REG_MOD_A_BK00_16_L, (u16temp<<8|u16temp));
1588 }
1589
MHal_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)1590 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
1591 {
1592 MS_U16 u16ValidSwing2 = 0;
1593 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1594 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1595 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1596 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1597 if( eLPLL_Type == E_PNL_TYPE_TTL)
1598 {
1599 // select pair output to be TTL
1600 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
1601 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
1602 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
1603 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
1604
1605 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair
1606
1607 // other TTL setting
1608 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x0000); // TTL output enable
1609
1610 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0x0000);
1611 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
1612 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000);
1613
1614 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew
1615
1616 // GPO gating
1617 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating
1618 }
1619 //// for osd dedicated output port, 1 port for video and 1 port for osd
1620 else if((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&
1621 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
1622 {
1623 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
1624 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path
1625 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
1626 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
1627 }
1628 else
1629 {
1630 switch(eOutputMode)
1631 {
1632 case E_PNL_OUTPUT_NO_OUTPUT:
1633 // if MOD_45[5:0] = 0x3F && XC_MOD_EXT_DATA_EN_L = 0x0,
1634 // then if XC_MOD_OUTPUT_CONF_L = 0x0 ---> output TTL as tri-state
1635 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
1636 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
1637 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
1638 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
1639
1640 //----------------------------------
1641 // Purpose: Set the output to be the GPO, and let it's level to Low
1642 // 1. External Enable, Pair 0~5
1643 // 2. GPIO Enable, pair 0~5
1644 // 3. GPIO Output data : All low, pair 0~5
1645 // 4. GPIO OEZ: output piar 0~5
1646 //----------------------------------
1647
1648 //1.External Enable, Pair 0~5
1649 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF);
1650 //2.GPIO Enable, pair 0~5
1651 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF);
1652 //3.GPIO Output data : All low, pair 0~5
1653 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF);
1654 //4.GPIO OEZ: output piar 0~5
1655 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF);
1656
1657 //1.External Enable, Pair 6~15
1658 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000);
1659 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
1660 //2.GPIO Enable, pair 6~15
1661 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000);
1662 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
1663 //3.GPIO Output data : All low, pair 6~15
1664 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000);
1665 MOD_A_W2BYTE(REG_MOD_A_BK00_45_L, 0x0000);
1666 //4.GPIO OEZ: output piar 6~15
1667 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000);
1668 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0x0000);
1669
1670 //1234.External Enable, Pair 16~17
1671 MOD_W2BYTE(REG_MOD_BK00_7E_L, 0xFF00);
1672
1673 //1.External Enable, Pair 18~20, 2.GPIO Enable, pair 18~20
1674 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F);
1675 //3.GPIO Output data : All low, pair 18~20
1676 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00);
1677 //4.GPIO OEZ: output piar 18~20
1678 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00);
1679 break;
1680
1681 case E_PNL_OUTPUT_CLK_ONLY:
1682 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000);
1683 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x4004);
1684 break;
1685
1686 case E_PNL_OUTPUT_DATA_ONLY:
1687 case E_PNL_OUTPUT_CLK_DATA:
1688 default:
1689
1690 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000);
1691 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0x0000);
1692 //1. set GCR_PVDD_2P5=1��b1; MOD PVDD power: 1: 2.5V
1693 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0, BIT(6));
1694 //2. set PD_IB_MOD=1��b0;
1695 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0));
1696 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8));
1697
1698
1699 // save ch6 init value
1700 u16ValidSwing2 = (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0B_L, 0x3F00)>>8);
1701 //3. set Desired Pairs: GCR_ICON[5:0]=6h3f (current all open);
1702 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, 0x3F));
1703 //4. set Desired Pairs: GCR_PE_ADJ[2:0]=3h7 (pre-emphasis current all open )
1704 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x07);
1705 //5. Enable low-power modeinternal termination Open, Enable OP
1706 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 1);
1707
1708 MsOS_DelayTask(1);
1709
1710 //6. Enable low-power modeinternal termination Open, Enable OP
1711 MHal_Output_LVDS_Pair_Setting(pInstance,
1712 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
1713 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
1714 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
1715 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
1716 MHal_Shift_LVDS_Pair(pInstance, pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift);
1717
1718 //7. set Desired Pairs: GCR_PE_ADJ[2:0]=3��h0 (pre-emphasis current all Close)
1719 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x00);
1720 //8. set Desired Pairs: GCR_ICON[5:0] (current all init);
1721 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, u16ValidSwing2));
1722 //9. Disable low-power modeinternal termination Close, Disable OP
1723 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 0);
1724
1725 // other TTL setting
1726 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/ PANEL_miniLVDS/ PANEL_RSDS
1727
1728 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000);
1729 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
1730 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F);
1731
1732 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew
1733
1734 // GPO gating
1735 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating
1736
1737 break;
1738 }
1739 }
1740
1741 // MHal_PNL_Bringup(pInstance);
1742 }
1743
Mhal_PNL_Flock_LPLLSet(void * pInstance,MS_U64 ldHz)1744 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz)
1745 {
1746 UNUSED(ldHz);
1747 }
1748
MHal_PNL_MISC_Control(void * pInstance,MS_U32 u32PNL_MISC)1749 void MHal_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC)
1750 {
1751 if(u32PNL_MISC & E_DRVPNL_MISC_MFC_ENABLE)
1752 {
1753 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair
1754 }
1755 }
1756
MHal_PNL_Init_XC_Clk(void * pInstance,PNL_InitData * pstPanelInitData)1757 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData)
1758 {
1759 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1760
1761 // setup output dot clock
1762 #if 0
1763 W2BYTEMSK(REG_CKG_ODCLK, CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock
1764 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert
1765 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock
1766
1767 W2BYTEMSK(REG_CKG_BT656, CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock
1768 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert
1769 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock
1770
1771 W2BYTE(REG_CLKGEN0_57_L,0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo
1772 W2BYTE(REG_CLKGEN0_58_L,0x0000); //[3:0]ckg_tx_mod
1773 W2BYTE(REG_CLKGEN0_63_L,0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod
1774
1775 W2BYTE(REG_CLKGEN1_31_L, 0x0000); //[11:8]ckg_odclk_frc
1776
1777 #else
1778 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock
1779 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert
1780 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock
1781
1782 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft
1783
1784 #if 0
1785 W2BYTEMSK(L_CLKGEN0(0x53), CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock
1786 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert
1787 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock
1788 #endif
1789 W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo
1790 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod
1791 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod
1792
1793 W2BYTE(L_CLKGEN1(0x31), 0x0000); //[11:8]ckg_odclk_frc
1794
1795 #endif
1796
1797
1798 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
1799 W2BYTE(REG_CLKGEN0_57_L,0x0000); //[3:0]ckg_fifo
1800
1801 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
1802 {
1803 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod
1804 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+
1805 }
1806 }
1807
MHal_PNL_Init_MOD(void * pInstance,PNL_InitData * pstPanelInitData)1808 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData)
1809 {
1810 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1811 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1812 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1813 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1814
1815 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1816
1817 //------------------------------------------------------------------------
1818
1819 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL0 = %x\n", pstPanelInitData->u16MOD_CTRL0);
1820 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL9 = %x\n", pstPanelInitData->u16MOD_CTRL9);
1821 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRLA = %x\n", pstPanelInitData->u16MOD_CTRLA);
1822 PNL_DBG(PNL_DBGLEVEL_INIT, "u8MOD_CTRLB = %x\n", pstPanelInitData->u8MOD_CTRLB);
1823
1824 //-------------------------------------------------------------------------
1825 // Set MOD registers
1826 //-------------------------------------------------------------------------
1827
1828 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK);
1829
1830 // GPIO is controlled in drvPadConf.c
1831 // MDrv_Write2Byte(L_BK_MOD(0x46), 0x0000); //EXT GPO disable
1832 // MDrv_Write2Byte(L_BK_MOD(0x47), 0x0000); //EXT GPO disable
1833
1834 MOD_W2BYTE(REG_MOD_BK00_49_L, pstPanelInitData->u16MOD_CTRL9); //{L_BK_MOD(0x49), 0x00}, // [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit, bit shift
1835 MHal_Output_Channel_Order(pInstance,
1836 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
1837 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
1838 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
1839 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
1840 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
1841
1842
1843 MOD_W2BYTE(REG_MOD_BK00_4A_L, pstPanelInitData->u16MOD_CTRLA);
1844 MOD_W2BYTE(REG_MOD_BK00_4B_L, pstPanelInitData->u8MOD_CTRLB); //[1:0]ti_bitmode 10:8bit 11:6bit 0x:10bit
1845
1846 //dual port lvds _start_//
1847 // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
1848 _MHal_PNL_Set_Clk(pInstance,
1849 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
1850 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
1851 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
1852 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
1853 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
1854 //dual port lvds _end_//
1855
1856 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, (_u8PnlDiffSwingLevel << 1), 0xFE); //differential output swing level
1857 //if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
1858 // (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
1859 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000, 0xF000); //bank selection for skew clock
1860
1861 //if(!MHal_PNL_MOD_Control_Out_Swing(_u8PnlDiffSwingLevel))
1862 // printf(">>Swing Level setting error!!\n");
1863 if(pstPanelInitData->eLPLL_Type != E_PNL_TYPE_MINILVDS)
1864 {
1865 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07);
1866 }
1867
1868 //// Patch for Vx1 and it should be control by panel ini
1869
1870 MOD_A_W2BYTE(REG_MOD_A_BK00_31_L, pstPanelInitData->u16LVDSTxSwapValue);
1871
1872
1873 // TODO: move from MDrv_Scaler_Init(), need to double check!
1874 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0));
1875
1876
1877 //--------------------------------------------------------------
1878 //Depend On Bitmode to set Dither
1879 //--------------------------------------------------------------
1880
1881
1882 // always enable noise dither and disable TAILCUT
1883 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, ((pstPanelInitData->u8PanelNoiseDith ? XC_PAFRC_DITH_NOISEDITH_EN : (1 - XC_PAFRC_DITH_NOISEDITH_EN)) <<3) , BIT(3));
1884 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, XC_PAFRC_DITH_TAILCUT_DISABLE, BIT(4));
1885
1886 switch(pstPanelInitData->u8MOD_CTRLB & 0x03)//[1:0]ti_bitmode b'10:8bit 11:6bit 0x:10bit
1887 {
1888 case HAL_TI_6BIT_MODE:
1889 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
1890 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(2), BIT(2));
1891 break;
1892
1893 case HAL_TI_8BIT_MODE:
1894 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
1895 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
1896 break;
1897
1898 case HAL_TI_10BIT_MODE:
1899 default:
1900 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(0));
1901 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
1902 break;
1903 }
1904
1905
1906 //-----depend on bitmode to set Dither------------------------------
1907 MHal_PNL_SetOutputType(pInstance, pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type); // TTL to Ursa
1908
1909 //MHal_PNL_Bringup(pInstance);
1910
1911 MHal_PNL_MISC_Control(pInstance, pstPanelInitData->u32PNL_MISC);
1912
1913 PNL_DBG(PNL_DBGLEVEL_INIT, "OutputType = %x, eLPLL_Type = %x\n", pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type);
1914 PNL_DBG(PNL_DBGLEVEL_INIT, "u32PNL_MISC = %x\n", (unsigned int)pstPanelInitData->u32PNL_MISC);
1915
1916 }
1917
MHal_PNL_DumpMODReg(void * pInstance,MS_U32 u32Addr,MS_U16 u16Value,MS_BOOL bHiByte,MS_U16 u16Mask)1918 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask)
1919 {
1920 if (bHiByte)
1921 {
1922 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
1923 }
1924 else
1925 {
1926 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask);
1927 }
1928 }
1929
MHal_MOD_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)1930 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
1931 {
1932 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1933 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1934 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1935 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1936 // Setup the default swing level
1937 pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel = pstModCaliInitData->u16ExpectSwingLevel; //mv
1938 #if 0
1939 // Pair setting
1940 // =========
1941 // Select calibration source pair, 00: ch2, 01: ch6, 10:ch8, 11:ch12
1942 //MOD_7D_L[3:2]
1943 // =========
1944 //in msModCurrentCalibration, it will transfer to the real data
1945
1946 switch(pstModCaliInitData->u8ModCaliPairSel)
1947 {
1948 default:
1949 case 0:
1950 //ch 2
1951 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x00; // ch2
1952 break;
1953 case 1:
1954 //ch 6
1955 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x01; // ch6, calibration initialized value
1956 break;
1957 case 2:
1958 //ch 8
1959 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x02;
1960 break;
1961 case 3:
1962 //ch 12
1963 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x03;
1964 break;
1965 }
1966 #endif
1967 // Target setting
1968 // =========
1969 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1970 // =========
1971 //in msModCurrentCalibration, it will transfer to the real data
1972 switch(pstModCaliInitData->u8ModCaliTarget)
1973 {
1974 default:
1975 case 0:
1976 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 0;
1977 break;
1978 case 1:
1979 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 1;
1980 break;
1981 case 2:
1982 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 2;
1983 break;
1984 case 3:
1985 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 3;
1986 break;
1987 }
1988 // Offset setting, for fine tune
1989 //_usMOD_CALI_OFFSET = pstModCaliInitData->s8ModCaliOffset;
1990 // _u8MOD_CALI_VALUE is a real value; the _u8MOD_CALI_VALUE is an idea value
1991 // Target value should be the same with _u8MOD_CALI_VALUE to be a default value
1992 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE= pstModCaliInitData->u8ModCaliTarget;
1993 // PVDD setting
1994 pPNLResourcePrivate->sthalPNL._bPVDD_2V5 = pstModCaliInitData->bPVDD_2V5;
1995
1996 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1997 PNL_DBG(PNL_DBGLEVEL_INIT, "u16ExpectSwingLevel = %u\n", pstModCaliInitData->u16ExpectSwingLevel);
1998 PNL_DBG(PNL_DBGLEVEL_INIT, "u8ModCaliTarget = %x\n", pstModCaliInitData->u8ModCaliTarget);
1999 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_TARGET = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET);
2000 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_VALUE = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE);
2001 PNL_DBG(PNL_DBGLEVEL_INIT, "bPVDD_2V5 = %x\n", pstModCaliInitData->bPVDD_2V5);
2002
2003 }
2004
MHal_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)2005 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type)
2006 {
2007 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2008 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2009 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2010 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2011 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
2012 {
2013 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift = LVDS_DUAL_OUTPUT_SPECIAL;
2014 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = 1;
2015 }
2016 else
2017 {
2018 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = Type;
2019 }
2020 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2021 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_LVDS_Pair_Type = %u\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
2022
2023 }
2024
msModCalDDAOUT(void)2025 MS_BOOL msModCalDDAOUT(void)
2026 {
2027 // W2BYTEMSK(BK_MOD(0x7D), ENABLE, 8:8);
2028 // MsOS_DelayTask(10); //10ms
2029 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_A_BK00_74_L, BIT(8))) >> 8);
2030 }
2031
msModCurrentCalibration(void * pInstance)2032 MS_U8 msModCurrentCalibration(void *pInstance)
2033 {
2034 #if MOD_CAL_TIMER
2035 MS_U32 delay_start_time;
2036 delay_start_time=MsOS_GetSystemTime();
2037 #endif
2038
2039 #if (!ENABLE_Auto_ModCurrentCalibration)
2040 return 0x60;
2041 #else
2042 MS_U8 u8cur_ibcal=0;
2043 MS_U16 u16reg_32da = 0, u16reg_32dc = 0 , u16cur_ibcal = 0;
2044 MS_U16 u16DefaultICON_Max = 0x2E, u16DefaultICON_Min = 0x06;
2045 MS_U16 u16DefaultICON = 0x19;
2046 MS_U32 u32Mask = 0xFF;
2047 MS_U16 u16icon_ch0_1=0,u16icon_ch2_3=0,u16icon_ch4_5=0,u16icon_ch6_7=0,
2048 u16icon_ch8_9=0,u16icon_ch10_11=0,u16icon_ch12_13=0;
2049 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2050 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2051 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2052 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2053 u16reg_32da = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2054 u16reg_32dc = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2055
2056 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s][%d]\n", __FUNCTION__, __LINE__);
2057
2058 // (1) Set keep mode to auto write calibration result into register.
2059 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15));
2060
2061 // (2) Set calibration step waiting time
2062 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0x0009); // reg_1ms_cnt
2063 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0009, 0x00FF); // reg_hw_cal_wait
2064
2065 // (3) Set calibration toggle time
2066 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00);
2067
2068 // (4) Select calibration level (LVDS is 250mV)
2069 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(1)|BIT(0)); // Select calibration target voltage, 00: 250mV, 01:350mV, 10: 300mV, 11: 200mV
2070
2071 // (5) Store output configuration value and Enable each pair test mode
2072 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0xFFFF);
2073 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0FFF);
2074
2075 // (6) Enable Calibration mode
2076 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function
2077
2078 // (7) Calibration fire on
2079 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, BIT(15), BIT(15));
2080
2081 // (8) Wait 3ms
2082 MsOS_DelayTask(3);
2083
2084 // (9) Read Finish and Fail flagbit
2085 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_73_L, 0x6000) == 0x4000)
2086 {
2087 //printf("\033[0;31m [%s][%d] cal ok, break \033[0m\n", __FUNCTION__, __LINE__);
2088 }
2089 else
2090 {
2091 //printf("\033[0;31m [%s][%d] cal ng, \033[0m\n", __FUNCTION__, __LINE__);
2092 }
2093
2094 // (10)
2095 // store ICON for each channel to avoid read not correct value when toogle
2096 // REG_MOD_A_BK00_72[15]
2097 u16icon_ch0_1 = MOD_A_R2BYTE(REG_MOD_A_BK00_08_L);
2098 u16icon_ch2_3 = MOD_A_R2BYTE(REG_MOD_A_BK00_09_L);
2099 u16icon_ch4_5 = MOD_A_R2BYTE(REG_MOD_A_BK00_0A_L);
2100 u16icon_ch6_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_0B_L);
2101 u16icon_ch8_9 = MOD_A_R2BYTE(REG_MOD_A_BK00_0C_L);
2102 u16icon_ch10_11 = MOD_A_R2BYTE(REG_MOD_A_BK00_0D_L);
2103 u16icon_ch12_13 = MOD_A_R2BYTE(REG_MOD_A_BK00_0E_L);
2104
2105 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_73_L, 0x6000) == 0x4000) // finsh= 1,fail= 0
2106 {
2107 // Error handling for calibration fail or unexpected calibraiton result case
2108 // ch0
2109 u8cur_ibcal = (u16icon_ch0_1&0x00FF);
2110 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15)); // disable keep mode
2111 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2112 {
2113 u16cur_ibcal = u16DefaultICON;
2114 }
2115 else
2116 {
2117 u16cur_ibcal = u8cur_ibcal;
2118 }
2119 // ch1
2120 u8cur_ibcal = (u16icon_ch0_1&0xFF00)>>8;
2121 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2122 {
2123 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2124 }
2125 else
2126 {
2127 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2128 }
2129 //refine ch0/ch1 calibration result
2130 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, u16cur_ibcal);
2131
2132 // ch2
2133 u8cur_ibcal = (u16icon_ch2_3&0x00FF);
2134 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2135 {
2136 u16cur_ibcal = u16DefaultICON;
2137 }
2138 else
2139 {
2140 u16cur_ibcal = u8cur_ibcal;
2141 }
2142 // ch3
2143 u8cur_ibcal = (u16icon_ch2_3&0xFF00)>>8;
2144
2145 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2146 {
2147 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2148 }
2149 else
2150 {
2151 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2152 }
2153 //refine ch2/ch3 calibration result
2154 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, u16cur_ibcal);
2155
2156 // ch4
2157 u8cur_ibcal = (u16icon_ch4_5&0x00FF);
2158
2159 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2160 {
2161 u16cur_ibcal = u16DefaultICON;
2162 }
2163 else
2164 {
2165 u16cur_ibcal = u8cur_ibcal;
2166 }
2167 // ch5
2168 u8cur_ibcal = (u16icon_ch4_5&0xFF00)>>8;
2169
2170 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2171 {
2172 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2173 }
2174 else
2175 {
2176 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2177 }
2178 //refine ch4/ch5 calibration result
2179 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, u16cur_ibcal);
2180
2181 // ch6
2182 u8cur_ibcal = (u16icon_ch6_7&0x00FF);
2183
2184 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2185 {
2186 u16cur_ibcal = u16DefaultICON;
2187 }
2188 else
2189 {
2190 u16cur_ibcal = u8cur_ibcal;
2191 }
2192 // ch7
2193 u8cur_ibcal = (u16icon_ch6_7&0xFF00)>>8;
2194
2195 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2196 {
2197 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0B_L, u16DefaultICON <<8, (MS_U16)u32Mask<<8); // refine ch7 calibration result
2198 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2199 }
2200 else
2201 {
2202 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2203 }
2204 //refine ch6/ch7 calibration result
2205 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, u16cur_ibcal);
2206
2207 // ch8
2208 u8cur_ibcal = (u16icon_ch8_9&0x00FF);
2209
2210 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2211 {
2212 u16cur_ibcal = u16DefaultICON;
2213 }
2214 else
2215 {
2216 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0C_L, u8cur_ibcal, (MS_U16)u32Mask); // refine ch8 calibration result
2217 u16cur_ibcal = u8cur_ibcal;
2218 }
2219 // ch9
2220 u8cur_ibcal = (u16icon_ch8_9&0xFF00)>>8;
2221 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2222 {
2223 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2224 }
2225 else
2226 {
2227 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0C_L, u8cur_ibcal <<8, (MS_U16)u32Mask<<8); // refine ch9 calibration result
2228 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2229 }
2230 //refine ch8/ch9 calibration result
2231 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, u16cur_ibcal);
2232
2233 // ch10
2234 u8cur_ibcal = (u16icon_ch10_11&0x00FF);
2235 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2236 {
2237 u16cur_ibcal = u16DefaultICON;
2238 }
2239 else
2240 {
2241 u16cur_ibcal = u8cur_ibcal;
2242 }
2243 // ch11
2244 u8cur_ibcal = (u16icon_ch10_11&0xFF00)>>8;
2245 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2246 {
2247 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2248 }
2249 else
2250 {
2251 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0D_L, u8cur_ibcal <<8, (MS_U16)u32Mask<<8); // refine ch11 calibration result
2252 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2253 }
2254 //refine ch10/ch11 calibration result
2255 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, u16cur_ibcal);
2256
2257 // ch12
2258 u8cur_ibcal = (u16icon_ch12_13&0x00FF);
2259
2260 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2261 {
2262 u16cur_ibcal = u16DefaultICON;
2263 }
2264 else
2265 {
2266 u16cur_ibcal = u8cur_ibcal;
2267 }
2268 // ch13
2269 u8cur_ibcal = (u16icon_ch12_13&0xFF00)>>8;
2270 if ((u8cur_ibcal < u16DefaultICON_Min) || (u8cur_ibcal > u16DefaultICON_Max))
2271 {
2272 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u16DefaultICON <<8);
2273 }
2274 else
2275 {
2276 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0E_L, u8cur_ibcal <<8, (MS_U16)u32Mask<<8); // refine ch13 calibration result
2277 u16cur_ibcal = (u16cur_ibcal&0xFF) |(u8cur_ibcal <<8);
2278 }
2279 //refine ch12/ch13 calibration result
2280 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, u16cur_ibcal);
2281 }
2282 else // Fail = 1
2283 {
2284 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15)); // disable keep mode
2285
2286 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch0/1 calibration result
2287 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch2/3 calibration result
2288 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch4/5 calibration result
2289 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch6/7 calibration result
2290 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch8/9 calibration result
2291 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch10/11 calibration result
2292 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L,u16DefaultICON |(u16DefaultICON <<8)); // refine ch12/13 calibration result
2293 }
2294
2295 // (11) Restore each pair output configuration
2296 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16reg_32da);
2297 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16reg_32dc);
2298
2299 // (12) Disable calibration mode
2300 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Diable Hardware calibration
2301
2302 // With HW calibration mode, HW would cal for each channel, and each channel would get different value
2303 // Return channel 2 vaule
2304 u8cur_ibcal = MOD_A_R2BYTEMSK(REG_MOD_A_BK00_09_L, 0x00FF); // return ch2 calibration result
2305
2306 #if MOD_CAL_TIMER
2307 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s] takes %ld ms\n", __FUNCTION__, (MsOS_GetSystemTime()-delay_start_time));
2308 #endif
2309 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n Calibration result= %x\n", u8cur_ibcal);
2310
2311 return (u8cur_ibcal&0xFF);//MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0D_L, 0x003F);
2312 #endif
2313 }
2314
MHal_PNL_MOD_Calibration(void * pInstance)2315 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance)
2316 {
2317 MS_U8 u8Cab;
2318 MS_U8 u8BackUSBPwrStatus;
2319 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2320 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2321 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2322 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2323
2324 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
2325
2326 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
2327
2328 u8Cab = msModCurrentCalibration(pInstance);
2329
2330 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
2331
2332 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type !=E_PNL_TYPE_MINILVDS)
2333 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07);
2334
2335 return E_PNL_OK;
2336
2337 }
2338
MHal_PNL_PowerDownLPLL(void * pInstance,MS_BOOL bEnable)2339 static void MHal_PNL_PowerDownLPLL(void *pInstance, MS_BOOL bEnable)
2340 {
2341 if(bEnable)
2342 {
2343 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5));
2344 }
2345 else
2346 {
2347 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5));
2348 }
2349 }
2350
MHal_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)2351 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn)
2352 {
2353 MS_U8 u8Cab;
2354 MS_U8 u8BackUSBPwrStatus;
2355 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2356 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2357 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2358 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2359
2360 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "[%s][%d]\n", __FUNCTION__, __LINE__);
2361
2362 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u32PNL_MISC = %x\n", (unsigned int)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC);
2363 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "bPanelOn = %x\n", bPanelOn);
2364 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "eLPLL_Type = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type);
2365 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "_u8MOD_LVDS_Pair_Type = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
2366 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
2367 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
2368 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2369
2370 MS_U16 u16PortA = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2371 MS_U16 u16PortB = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2372
2373 if(u16PortA!=0)
2374 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2375 if(u16PortB!=0)
2376 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2377
2378 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "==========================\n\n");
2379 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
2380 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
2381 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2382
2383
2384 if(bPanelOn)
2385 {
2386 // The order is PanelVCC -> delay pnlGetOnTiming1() -> VOP -> MOD
2387 // VOP
2388 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x4000, HBMASK);
2389
2390 // For Napoli compatible
2391 // need to wait 1ms to wait LDO stable before MOD power on
2392 MsOS_DelayTask(1);
2393
2394 // turn on LPLL
2395 MHal_PNL_PowerDownLPLL(pInstance, FALSE);
2396
2397 // mod power on
2398 MHal_MOD_PowerOn(pInstance
2399 , ENABLE
2400 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
2401 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
2402 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
2403 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
2404 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2405
2406
2407 if(bCalEn)
2408 {
2409
2410 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
2411
2412 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
2413
2414 u8Cab = msModCurrentCalibration(pInstance);
2415
2416 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
2417
2418 }
2419 else
2420 {
2421 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type>=E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2422 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type<=E_PNL_LPLL_VBY1_8BIT_8LANE) &&
2423 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE) == FALSE))
2424 {
2425 HAL_MOD_CAL_DBG(printf("Use RCON value \n", __FUNCTION__, __LINE__));
2426 msSetVBY1RconValue(pInstance);
2427 }
2428 else
2429 {
2430 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
2431
2432 if(!MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel))
2433 printf(">>Swing Level setting error!!\n");
2434 }
2435 }
2436
2437
2438 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
2439 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, ENABLE);
2440 }
2441 else
2442 {
2443 // The order is LPLL -> MOD -> VOP -> delay for MOD power off -> turn off VCC
2444
2445 // LPLL
2446 // MHal_PNL_PowerDownLPLL(TRUE); //Remove to keep op vsync if panel off
2447
2448 MHal_MOD_PowerOn(pInstance
2449 , DISABLE
2450 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
2451 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
2452 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
2453 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
2454 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2455 // VOP
2456 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS ||
2457 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_I ||
2458 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_P)//(bIsLVDS)
2459 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0xFF, LBMASK);
2460 else
2461 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x00, 0xFF);
2462 }
2463
2464 return E_PNL_OK;
2465 }
2466
MHal_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)2467 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
2468 {
2469 if (bEnable)
2470 {
2471 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF);
2472 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF);
2473 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF);
2474 MsOS_DelayTask(10);
2475 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15));
2476 }
2477 else
2478 {
2479 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15));
2480 }
2481
2482 }
2483
MHal_PNL_Switch_LPLL_SubBank(void * pInstance,MS_U16 u16Bank)2484 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank)
2485 {
2486 UNUSED(u16Bank);
2487 }
2488
MHal_PNL_Switch_TCON_SubBank(void * pInstance,MS_U16 u16Bank)2489 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank)
2490 {
2491 W2BYTEMSK(L_BK_TCON(0x00), u16Bank&0xff, 0xFF);
2492 }
2493
MHal_PNL_Read_TCON_SubBank(void * pInstance)2494 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance)
2495 {
2496 return (MS_U16)R2BYTEMSK(L_BK_TCON(0x00),0xFF);
2497 }
2498
MHal_PNL_Is_VBY1_Locked(void * pInstance)2499 MS_BOOL MHal_PNL_Is_VBY1_Locked(void *pInstance)
2500 {
2501 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0300) == 0x00)
2502 {
2503 return TRUE;
2504 }
2505 else
2506 {
2507 return FALSE;
2508 }
2509 }
2510
MHal_PNL_Is_VBY1_LockN_Locked(void * pInstance)2511 MS_BOOL MHal_PNL_Is_VBY1_LockN_Locked(void *pInstance)
2512 {
2513 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0100) == 0x00)
2514 {
2515 return TRUE;
2516 }
2517 else
2518 {
2519 return FALSE;
2520 }
2521 }
2522
MHal_PNL_VBY1_Handshake(void * pInstance)2523 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance)
2524 {
2525 MS_BOOL bIsLock = FALSE;
2526
2527 if (MHal_PNL_Is_VBY1_Locked(pInstance) == FALSE)
2528 {
2529 MS_U16 u16CheckTimes = 0;
2530 //MS_U16 u16DeboundTimes = 0;
2531
2532 // need to toggle vby1 packer process start first
2533 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11));
2534 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11));
2535
2536 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value
2537 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by
2538 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition
2539 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
2540 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance
2541
2542 while(u16CheckTimes < 10)
2543 {
2544 #if 0
2545 u16DeboundTimes = 2;
2546 while ((!MHal_PNL_Is_VBY1_LockN_Locked()) && (u16DeboundTimes --))
2547 {
2548 MsOS_DelayTask(1); // can't remove
2549 }
2550 #endif
2551 if(MHal_PNL_Is_VBY1_LockN_Locked(pInstance))
2552 {
2553 //-------------------------------------------------------------------
2554 // step1. Toggle clock when training
2555 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
2556 //--------------------------------------------------------------------
2557 bIsLock = TRUE;
2558 // pass 2 times debound to make sure VBY1 is locked
2559 break;
2560 }
2561
2562 u16CheckTimes++;
2563 MsOS_DelayTaskUs(40);
2564 }
2565
2566 if(bIsLock)
2567 {
2568 // step3. Disable HW check when lock done, Enable when loss lock
2569 //MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
2570
2571 /// Add the delay to increase time to send
2572 //MDrv_TIMER_Delayms(10);
2573 }
2574 }
2575 else
2576 {
2577 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE)
2578 {
2579 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
2580 }
2581 bIsLock = TRUE;
2582 }
2583
2584 return bIsLock;
2585 }
2586
MHal_PNL_Is_VBY1_OC_Locked(void * pInstance)2587 MS_BOOL MHal_PNL_Is_VBY1_OC_Locked(void *pInstance)
2588 {
2589 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0C00) == 0x00) // MOD_BK00_56_L[11:10] for OSD
2590 {
2591 return TRUE;
2592 }
2593 else
2594 {
2595 return FALSE;
2596 }
2597 }
2598
MHal_PNL_Is_VBY1_OC_LockN_Locked(void * pInstance)2599 MS_BOOL MHal_PNL_Is_VBY1_OC_LockN_Locked(void *pInstance)
2600 {
2601 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0400) == 0x00) // MOD_BK00_56_L[11:10] for OSD
2602 {
2603 return TRUE;
2604 }
2605 else
2606 {
2607 return FALSE;
2608 }
2609 }
2610
MHal_PNL_VBY1_OC_Handshake(void * pInstance)2611 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance)
2612 {
2613 MS_BOOL bIsLock = FALSE;
2614
2615 if (MHal_PNL_Is_VBY1_OC_Locked(pInstance) == FALSE)
2616 {
2617 MS_U16 u16CheckTimes = 0;
2618 // MS_U16 u16DeboundTimes = 0;
2619
2620 // need to toggle vby1 packer process start first
2621 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11));
2622 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11));
2623
2624
2625 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value
2626 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by
2627 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition
2628 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
2629 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance
2630
2631 while(u16CheckTimes < 10)
2632 {
2633 #if 0
2634 u16DeboundTimes = 2;
2635 while ((!MHal_PNL_Is_VBY1_OC_LockN_Locked()) && (u16DeboundTimes --))
2636 {
2637 MsOS_DelayTask(1);
2638 }
2639 #endif
2640 if(MHal_PNL_Is_VBY1_OC_LockN_Locked(pInstance))
2641 {
2642 //-------------------------------------------------------------------
2643 // step1. Toggle clock when training
2644
2645 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
2646 bIsLock = TRUE;
2647 // pass 2 times debound to make sure VBY1 is locked
2648 break;
2649 }
2650
2651 u16CheckTimes++;
2652 MsOS_DelayTaskUs(40);
2653 }
2654
2655 if(bIsLock)
2656 {
2657 // step3. Disable HW check when lock done, Enable when loss lock
2658 // MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
2659 }
2660 }
2661 else
2662 {
2663 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE)
2664 {
2665 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
2666 }
2667 bIsLock = TRUE;
2668 }
2669
2670 return bIsLock;
2671 }
2672
MHal_PNL_IsYUVOutput(void * pInstance)2673 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance)
2674 {
2675 return FALSE;
2676 }
2677
MHal_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)2678 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
2679 {
2680 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2681 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2682
2683 if (bEnable == TRUE)
2684 {
2685 //interlace output vtotal modify
2686 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9), BIT(9));
2687
2688 // two different interlace information through channel A reserved bit
2689 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7));
2690 // two different interlace information through channel B reserved bit
2691 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11));
2692 }
2693 else
2694 {
2695 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L , 0, BIT(9));
2696 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7));
2697 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11));
2698 }
2699
2700 return TRUE;
2701 }
2702
MHal_PNL_GetOutputInterlaceTiming(void * pInstance)2703 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance)
2704 {
2705 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2706 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2707
2708 MS_BOOL bIsInterlaceOutput = FALSE;
2709 //interlace output vtotal modify
2710 if (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9)) == BIT(9))
2711 {
2712 if ((MOD_R2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7)) == (BIT(4) | BIT(7)))
2713 || (MOD_R2BYTEMSK(REG_MOD_BK00_42_L, BIT(10) | BIT(11)) == (BIT(10)|BIT(11))))
2714 {
2715 bIsInterlaceOutput = TRUE;
2716 }
2717 }
2718 else
2719 {
2720 bIsInterlaceOutput = FALSE;
2721 }
2722 return bIsInterlaceOutput;
2723 }
2724
2725 // Output Dclk
MHal_PNL_CalExtLPLLSETbyDClk(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U64 ldHz)2726 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz)
2727 {
2728 UNUSED(pInstance);
2729 UNUSED(u8LPLL_Mode);
2730 UNUSED(u8LPLL_Type);
2731 UNUSED(ldHz);
2732 }
2733
MHal_PNL_SetOSDCOutputType(void * pInstance,PNL_TYPE eLPLL_Type,E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)2734 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)
2735 {
2736 UNUSED(pInstance);
2737 UNUSED(eLPLL_Type);
2738 UNUSED(eOC_OutputFormat);
2739 }
2740
MHal_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)2741 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
2742 {
2743 MS_U16 u16Span;
2744 MS_U16 u16Step;
2745 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
2746
2747 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
2748 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
2749 // Set SPAN
2750 if(u16Fmodulation < 200 || u16Fmodulation > 400)
2751 u16Fmodulation = 300;
2752 u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) / ((MS_U32)u32PLL_SET) ) ;
2753
2754 // Set STEP
2755 if(u16Rdeviation > 300)
2756 u16Rdeviation = 300;
2757 u16Step = ((MS_U32)u32PLL_SET*u16Rdeviation) / ((MS_U32)u16Span*10000);
2758
2759 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP
2760 W2BYTE(L_BK_LPLL(0x4F), u16Span & 0x3FFF);// LPLL_SPAN
2761 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
2762
2763
2764 return TRUE;
2765 }
2766
MHal_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)2767 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
2768 {
2769 //printf("bEnable = %d\n", bEnable);
2770 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
2771 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
2772 }
2773
MHal_PNL_Set_T3D_Setting(void * pInstance)2774 void MHal_PNL_Set_T3D_Setting(void *pInstance)
2775 {
2776 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2777 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2778
2779 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
2780 }
2781
MHal_PNL_Set_Device_Bank_Offset(void * pInstance)2782 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance)
2783 {
2784 UNUSED(pInstance);
2785 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM);
2786 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg bank offset
2787 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg bank offset
2788 }
2789
MHal_PNL_Init(void * pInstance)2790 void MHal_PNL_Init(void *pInstance)
2791 {
2792 // Do nothing
2793 UNUSED(pInstance);
2794 }
2795
MHal_PNL_Bringup(void * pInstance)2796 void MHal_PNL_Bringup(void *pInstance)
2797 {
2798 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2799 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2800 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2801 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2802
2803 ///patch for bring up
2804 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
2805 {
2806 //==================== MPLL ====================
2807 //swch 4
2808 W2BYTEMSK(0x00101e38, 0x00, 0xFF);
2809 W2BYTEMSK(0x00110c03, 0x00, 0xFF);
2810 W2BYTE(0x00111e74, 0x0100);
2811 //===== Setting LPLL (LVDS_2ch_150M) ======//
2812 W2BYTEMSK(0x0010311e, 0x440, 0xFF);
2813 W2BYTEMSK(0x0010311f, 0x7f, 0xFF);
2814 W2BYTEMSK(0x00103120, 0x27, 0xFF);
2815 W2BYTEMSK(0x00103121, 0x00, 0xFF);
2816 W2BYTEMSK(0x0010312a, 0x00, 0xFF);
2817 W2BYTEMSK(0x0010312b, 0x00, 0xFF);
2818 W2BYTEMSK(0x00103102, 0x02, 0xFF);
2819 W2BYTEMSK(0x00103103, 0x03, 0xFF);
2820 W2BYTEMSK(0x00103104, 0x00, 0xFF);
2821 W2BYTEMSK(0x00103105, 0x07, 0xFF);
2822 W2BYTEMSK(0x00103106, 0x04, 0xFF);
2823 W2BYTEMSK(0x00103107, 0x00, 0xFF);
2824 W2BYTEMSK(0x00103108, 0x00, 0xFF);
2825 W2BYTEMSK(0x00103109, 0x00, 0xFF);
2826 W2BYTEMSK(0x0010315c, 0x90, 0xFF);
2827 W2BYTEMSK(0x0010315d, 0x57, 0xFF);
2828 W2BYTEMSK(0x00103160, 0x00, 0xFF);
2829 W2BYTEMSK(0x00103161, 0x00, 0xFF);
2830 W2BYTEMSK(0x00103162, 0x00, 0xFF);
2831 W2BYTEMSK(0x00103163, 0x00, 0xFF);
2832 W2BYTEMSK(0x00103164, 0x00, 0xFF);
2833 W2BYTEMSK(0x00103165, 0x00, 0xFF);
2834 W2BYTEMSK(0x00103166, 0x20, 0xFF);
2835 W2BYTEMSK(0x00103167, 0x00, 0xFF);
2836 W2BYTEMSK(0x00103168, 0x00, 0xFF);
2837 W2BYTEMSK(0x00103169, 0x00, 0xFF);
2838 W2BYTEMSK(0x0010316a, 0x00, 0xFF);
2839 W2BYTEMSK(0x0010316b, 0x1f, 0xFF);
2840 W2BYTEMSK(0x0010316c, 0x00, 0xFF);
2841 W2BYTEMSK(0x0010316d, 0x00, 0xFF);
2842 W2BYTEMSK(0x0010316e, 0x00, 0xFF);
2843 W2BYTEMSK(0x0010316f, 0x00, 0xFF);
2844 W2BYTEMSK(0x00103172, 0x00, 0xFF);
2845 W2BYTEMSK(0x00103173, 0x00, 0xFF);
2846 W2BYTEMSK(0x001031c0, 0xf0, 0xFF);
2847 W2BYTEMSK(0x001031c1, 0x00, 0xFF);
2848 W2BYTEMSK(0x001031c2, 0x00, 0xFF);
2849 W2BYTEMSK(0x001031c3, 0x00, 0xFF);
2850 W2BYTEMSK(0x001031c4, 0xf0, 0xFF);
2851 W2BYTEMSK(0x001031c5, 0x00, 0xFF);
2852 W2BYTEMSK(0x001031c6, 0x00, 0xFF);
2853 W2BYTEMSK(0x001031c7, 0x00, 0xFF);
2854 W2BYTEMSK(0x001031c8, 0x00, 0xFF);
2855 W2BYTEMSK(0x001031c9, 0x00, 0xFF);
2856 W2BYTEMSK(0x001031ca, 0x00, 0xFF);
2857 W2BYTEMSK(0x001031cb, 0x00, 0xFF);
2858 W2BYTEMSK(0x001031cc, 0x00, 0xFF);
2859 W2BYTEMSK(0x001031cd, 0x00, 0xFF);
2860 W2BYTEMSK(0x001031e2, 0x00, 0xFF);
2861 W2BYTEMSK(0x001031e3, 0x00, 0xFF);
2862 //==================== CLKGEN ====================
2863 W2BYTEMSK(0x00100bb0, 0x00, 0xFF);
2864 W2BYTEMSK(0x00100bb1, 0x00, 0xFF);
2865 W2BYTEMSK(0x00100bae, 0x00, 0xFF);
2866 W2BYTEMSK(0x00100baf, 0x01, 0xFF);
2867 W2BYTEMSK(0x00100ba6, 0x0c, 0xFF);
2868 W2BYTEMSK(0x00100ba7, 0x00, 0xFF);
2869 W2BYTEMSK(0x00100bc6, 0x01, 0xFF);
2870 W2BYTEMSK(0x00100bc7, 0x00, 0xFF);
2871 //==================== disp_misc_a ====================
2872 W2BYTEMSK(0x00111e70, 0x1f, 0xFF);
2873 W2BYTEMSK(0x00111e71, 0x00, 0xFF);
2874 W2BYTEMSK(0x00111e00, 0x55, 0xFF);
2875 W2BYTEMSK(0x00111e01, 0x55, 0xFF);
2876 W2BYTEMSK(0x00111e02, 0x55, 0xFF);
2877 W2BYTEMSK(0x00111e03, 0x00, 0xFF);
2878 W2BYTEMSK(0x00111ed0, 0x3f, 0xFF);
2879 W2BYTEMSK(0x00111ed1, 0x00, 0xFF);
2880 W2BYTEMSK(0x00111eb2, 0x00, 0xFF);
2881 W2BYTEMSK(0x00111eb3, 0x00, 0xFF);
2882 W2BYTEMSK(0x00111eb0, 0x00, 0xFF);
2883 W2BYTEMSK(0x00111eb1, 0x00, 0xFF);
2884 //==================== disp_misc_a ====================
2885 //==================== disp_misc_d ====================
2886 W2BYTEMSK(0x00103294, 0x02, 0xFF);
2887 W2BYTEMSK(0x00103295, 0x00, 0xFF);
2888 W2BYTEMSK(0x00103266, 0x00, 0xFF);
2889 W2BYTEMSK(0x00103267, 0x80, 0xFF);
2890 //==================== disp_misc_d ====================
2891 //==========================//
2892 //= DISP_TGEN GREY BOX =//
2893 //==========================//
2894 W2BYTE(0x102f00, 0x0010);
2895 W2BYTE(0x102f02, 0x0002);
2896 W2BYTE(0x102f08, 0x0070);
2897 W2BYTE(0x102f0a, 0x07ef);
2898 W2BYTE(0x102f0c, 0x0014);
2899 W2BYTE(0x102f0e, 0x044b);
2900 W2BYTE(0x102f10, 0x0071);
2901 W2BYTE(0x102f12, 0x07ee);
2902 W2BYTE(0x102f14, 0x0015);
2903 W2BYTE(0x102f16, 0x044a);
2904 W2BYTE(0x102f18, 0x0897);
2905 W2BYTE(0x102f1a, 0x0464);
2906 W2BYTE(0x102f32, 0xff03);
2907 W2BYTE(0x102f34, 0x0000);
2908
2909 //*********** bring up for different setting *********//
2910 W2BYTE(0x111e62, 0x3fff);
2911 W2BYTEMSK(0x103280, 0x0C, 0xFF);
2912 W2BYTEMSK(0x103296, 0x00, 0xFF);
2913 }
2914
2915 }
2916
MHal_PNL_GetPanelVStart(void)2917 MS_U16 MHal_PNL_GetPanelVStart(void)
2918 {
2919 return 6;
2920 }
2921
MHal_PNL_Check_VBY1_Handshake_Status(void * pInstance)2922 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance)
2923 {
2924 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE)
2925 {
2926 //printf("VBY1 handshake return because the reg value is 0x%u, not 0xFAE.\n", MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF));
2927 return FALSE;
2928 }
2929 else
2930 {
2931 //printf("VBY handshake check success.\n");
2932 return TRUE;
2933 }
2934 }
2935
MHal_PNL_ChannelFIFOPointerADjust(void * pInstance)2936 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance)
2937 {
2938 // 0 to 1 then will do write and read point capture to
2939 // Read : REG_MOD_BK00_5F_L[14:12]
2940 // write : REG_MOD_BK00_5F_L[10:8]
2941 // it takes 3 ticks to capture and riu takes 5 ticks to write
2942 // so we don't have to do any delay between rising capture and
2943 // read/write pointer recognition
2944 MsOS_DelayTaskUs(500);
2945 MOD_A_W2BYTE(REG_MOD_A_BK00_5C_L, 0x3300);
2946
2947 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
2948 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
2949
2950 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
2951 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
2952
2953 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
2954 MS_U16 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
2955 MS_S8 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
2956 MS_S8 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
2957
2958 //OSD part
2959 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
2960 MS_U16 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
2961 MS_S8 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
2962 MS_S8 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
2963
2964 MS_BOOL bOSDC = ((MOD_A_R2BYTE(REG_MOD_A_BK00_58_L)&0x00F0) == 0x0040)?TRUE:FALSE;
2965 while (((abs(u8WritePointer-u8ReadPointer) >4) && (abs(u8WritePointer-u8ReadPointer)<2))
2966 ||(((abs(OSDu8WritePointer-OSDu8ReadPointer) >4) && (abs(OSDu8WritePointer-OSDu8ReadPointer)<2))&&bOSDC))
2967 {
2968 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
2969 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
2970
2971 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
2972 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
2973
2974 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
2975 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
2976 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
2977 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
2978
2979 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
2980 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
2981 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
2982 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
2983 printf("bOSDC [%d]\n",bOSDC);
2984
2985 }
2986
2987 }
2988
MHal_PNL_VBY1_Hardware_TrainingMode_En(void * pInstance,MS_BOOL bIsVideoMode,MS_BOOL bEnable)2989 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable)
2990 {
2991 if(bIsVideoMode)
2992 {
2993 if(bEnable)
2994 {
2995 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE);
2996 }
2997 else
2998 {
2999 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AA6);
3000 }
3001 }
3002 else
3003 {
3004 if(bEnable)
3005 {
3006 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE);
3007 }
3008 else
3009 {
3010 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6);
3011 }
3012 }
3013 }
3014
MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void * pInstance)3015 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance)
3016 {
3017 #ifdef SUPPORT_VBY1_HWTRAINING_MODE
3018 return TRUE;
3019 #else
3020 return FALSE;
3021 #endif
3022 }
3023
MHal_PNL_TCON_Patch(void)3024 void MHal_PNL_TCON_Patch(void)
3025 {
3026
3027 }
3028
3029 #endif
3030
3031