1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _HAL_PNL_C_
79 #define _HAL_PNL_C_
80
81 //-------------------------------------------------------------------------------------------------
82 // Include Files
83 //-------------------------------------------------------------------------------------------------
84
85 #include "MsCommon.h"
86 #include "MsTypes.h"
87 #include "utopia.h"
88 #include "utopia_dapi.h"
89 #include "apiPNL.h"
90 #include "apiPNL_v2.h"
91 #include "drvPNL.h"
92 #include "halPNL.h"
93 #include "PNL_private.h"
94 #include "pnl_hwreg_utility2.h"
95 #include "Maxim_pnl_lpll_tbl.h"
96 #include "Maxim_pnl_lpll_ext_tbl.h"
97
98 #ifdef MSOS_TYPE_LINUX_KERNEL
99 #include <linux/string.h>
100 #include <linux/delay.h>
101 #include <asm/div64.h>
102 #else
103 #include "string.h"
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114
115 #define UNUSED(x) (x=x)
116 #if 1
117 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) printf("PNL:"_fmt, ##_args); }
118 #define HAL_MOD_CAL_DBG(x) //x
119 #else
120 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { }
121 #endif
122
123 #define DAC_LPLL_ICTRL 0x0002
124 #define LVDS_LPLL_ICTRL 0x0001
125
126 //Get MOD calibration time
127 #define MOD_CAL_TIMER FALSE
128
129 #define FRC_PIPE_DELAY_VCNT_FSC_FHD 0x10
130 #define FRC_PIPE_DELAY_HCNT_FSC_FHD 0x140
131
132 //-------------------------------------------------------------------------------------------------
133 // Local Structurs
134 //-------------------------------------------------------------------------------------------------
135
136 //-------------------------------------------------------------------------------------------------
137 // Global Variables
138 //-------------------------------------------------------------------------------------------------
139 #define LANE_NUM_EACH_PINMAPPING_GROUP1 4
140 #define LANE_NUM_EACH_PINMAPPING_GROUP2 4
141 #define LANE_NUM_EACH_PINMAPPING_GROUP3 4
142 #define LANE_NUM_EACH_PINMAPPING_GROUP4 2
143
144 #define PINMAPPING_EXP 16
145 //-------------------------------------------------------------------------------------------------
146 // Local Variables
147 //-------------------------------------------------------------------------------------------------
148 MS_U8 LANE_AND_CLK_TBL[VBY1_CLK_TBL_ROW][3]=
149 { //lane(from) lane(to) bit(mask)
150 { 0, 3, 0x02, },
151 { 4, 6, 0x04, },
152 { 7, 9, 0x08, },
153 { 10, 13, 0x10, }
154 };
155 //-------------------------------------------------------------------------------------------------
156 // Debug Functions
157 //-------------------------------------------------------------------------------------------------
158
159 //-------------------------------------------------------------------------------------------------
160 // Local Functions
161 //-------------------------------------------------------------------------------------------------
162 static void _MHal_PNL_Auto_Set_Config(void *pInstance,
163 MS_U16 u16OutputOrder0_3,
164 MS_U16 u16OutputOrder4_7,
165 MS_U16 u16OutputOrder8_11,
166 MS_U16 u16OutputOrder12_13);
167 #if 0
168 static void _MHal_PNL_Set_Clk(void *pInstance,
169 MS_U8 u8LaneNum,
170 MS_U16 u16OutputOrder0_3,
171 MS_U16 u16OutputOrder4_7,
172 MS_U16 u16OutputOrder8_11,
173 MS_U16 u16OutputOrder12_13);
174 #endif
175
176 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance);
177
178 static MS_BOOL _Hal_MOD_External_eFuse(void);
179
180 //-------------------------------------------------------------------------------------------------
181 // Global Function
182 //-------------------------------------------------------------------------------------------------
183 /**
184 * @brief: Power On MOD. but not mutex protected
185 *
186 */
MHal_MOD_PowerOn(void * pInstance,MS_BOOL bEn,MS_U8 u8LPLL_Type,MS_U8 DualModeType,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)187 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
188 {
189 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
190 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
191 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
192 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
193
194 if( bEn )
195 {
196 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8));
197
198 //analog MOD power down. 1: power down, 0: power up
199 // For Mod2 no output signel
200 ///////////////////////////////////////////////////
201
202 //2. Power on MOD (current and regulator)
203 if(u8LPLL_Type == E_PNL_TYPE_TTL)
204 {
205 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0) , BIT(0));
206 }
207 else
208 {
209 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0));
210 }
211 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8));
212
213
214 // 3. 4. 5.
215 MHal_Output_LVDS_Pair_Setting(pInstance, DualModeType, u16OutputCFG0_7, u16OutputCFG8_15, u16OutputCFG16_21);
216
217
218 //enable ib, enable ck
219 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0)));
220
221 // clock gen of dot-mini
222 if(u8LPLL_Type == E_PNL_TYPE_MINILVDS)
223 {
224 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x4400);
225 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x4400);
226 }
227 else if((u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
228 (u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)||
229 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE) ||
230 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_2LANE))
231
232 {
233 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
234 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
235 // [7:4]reg_ckg_dot_mini_pre_osd
236 }
237 //// for osd dedicated output port, 1 port for video and 1 port for osd
238 else if((u8LPLL_Type == E_PNL_TYPE_HS_LVDS)&&
239 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
240 {
241 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
242 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
243 // [7:4]reg_ckg_dot_mini_pre_osd
244 }
245 #if 0 // this only for 8V4O case, no need this for Maxim 23x23 8V case
246 else if(u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
247 {
248 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); // [11:8]reg_ckg_dot_mini_pre2_osd
249 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
250 }
251 #endif
252 else
253 {
254 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0000);
255 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0000);
256 }
257
258 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0x0008, 0x0008); // reg_fix_cnt_clr
259 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0x0000, 0x0008);
260
261 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0080, 0x0080); // reg_proc_st_clr
262 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0000, 0x0080);
263
264 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0080, 0x0080); // reg_unlock_cnt_clr
265 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x0080);
266
267 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x0000, 0x8000);
268 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x8000, 0x8000);
269 }
270 else
271 {
272 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8));
273 if(u8LPLL_Type !=E_PNL_TYPE_MINILVDS)
274 {
275 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: power up
276 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8));
277 }
278
279 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib, enable ck
280
281 // clock gen of dot-mini
282 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x1100);
283 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x1100);
284
285 if( IsVBY1(u8LPLL_Type) )
286 {
287 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
288 MsOS_DelayTask(1);
289 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
290 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
291 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
292 }
293 }
294 return 1;
295 }
296
297 /**
298 * @brief: Setup the PVDD power 1:2.5V, 0:3.3V
299 *
300 */
MHal_MOD_PVDD_Power_Setting(void * pInstance,MS_BOOL bIs2p5)301 void MHal_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5)
302 {
303 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, ((bIs2p5)? BIT(6):0), BIT(6)); //MOD PVDD=1: 0.9
304 }
305
MHal_PNL_TCON_Init(void * pInstance)306 void MHal_PNL_TCON_Init(void *pInstance)
307 {
308
309 }
310
MHal_Shift_LVDS_Pair(void * pInstance,MS_U8 Type)311 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type)
312 {
313 if(Type == 1)
314 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LVDS Mode3
315 else
316 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6)));
317
318 }
319
MHal_Output_LVDS_Pair_Setting(void * pInstance,MS_U8 Type,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)320 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
321 {
322
323 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
324 {
325 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
326 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x1554);
327 }
328 else if(Type == LVDS_SINGLE_OUTPUT_A)
329 {
330 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
331 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
332 }
333 else if( Type == LVDS_SINGLE_OUTPUT_B)
334 {
335 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
336 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
337 }
338 else if( Type == LVDS_OUTPUT_User)
339 {
340 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16OutputCFG0_7);
341 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16OutputCFG8_15);
342 }
343 else
344 {
345 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
346 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
347 }
348
349 MsOS_DelayTask(2);
350
351
352 }
353
_MHal_PNL_Get_LaneNum(void * pInstance)354 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance)
355 {
356 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
357 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
358 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
359 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
360
361 MS_U8 u8LaneNum = 0;
362 //check lane num
363 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
364 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
365 {
366 u8LaneNum = 8;
367 }
368 else if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
369 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
370 {
371 u8LaneNum = 4;
372 }
373 else if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)
374 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
375 {
376 u8LaneNum = 2;
377 }
378 else
379 {
380 u8LaneNum = 0;
381 }
382 return u8LaneNum;
383 }
384
385
_MHal_PNL_Auto_Set_Config(void * pInstance,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)386 static void _MHal_PNL_Auto_Set_Config(void *pInstance,
387 MS_U16 u16OutputOrder0_3,
388 MS_U16 u16OutputOrder4_7,
389 MS_U16 u16OutputOrder8_11,
390 MS_U16 u16OutputOrder12_13)
391 {
392 //attention : This function just support vby1 now.
393 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
394 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
395 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
396 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
397
398
399 MS_U8 u8OutputConfigCount = 0;
400 MS_U16 u16Config =0;
401 MS_U8 u8Count = 0;
402 MS_U8 u8LaneNum = 0;
403 MS_BOOL bSkip = TRUE;
404
405 //check lane num
406 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
407 if(u8LaneNum!=0)
408 {
409 bSkip = FALSE;
410 }
411 else
412 {
413 bSkip = TRUE;
414
415 //use default config
416 MHal_Output_LVDS_Pair_Setting(pInstance,
417 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
418 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
419 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
420 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
421 }
422
423 if(!bSkip)
424 {
425 //set output config
426 u16Config = 0;
427 u8OutputConfigCount = 0;
428 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP1 ; u8Count++ )
429 {
430 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
431 {
432 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
433 }
434 u16OutputOrder0_3 = u16OutputOrder0_3 / PINMAPPING_EXP;
435 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
436 }
437 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP2 ; u8Count++ )
438 {
439 if( (u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
440 {
441 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
442 }
443 u16OutputOrder4_7 = u16OutputOrder4_7 / PINMAPPING_EXP;
444 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
445 }
446 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16Config);
447
448 u16Config =0;
449 u8OutputConfigCount = 0;
450 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP3 ; u8Count++ )
451 {
452 if( (u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
453 {
454 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
455 }
456 u16OutputOrder8_11 = u16OutputOrder8_11 / PINMAPPING_EXP;
457 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
458 }
459 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP4 ; u8Count++ )
460 {
461 if( (u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
462 {
463 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
464 }
465 u16OutputOrder12_13 = u16OutputOrder12_13 / PINMAPPING_EXP;
466 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
467 }
468 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16Config);
469
470 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
471 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
472 }
473 }
474
475 #if 0
476 static void _MHal_PNL_Set_Clk(void *pInstance,
477 MS_U8 Type,
478 MS_U16 u16OutputOrder0_3,
479 MS_U16 u16OutputOrder4_7,
480 MS_U16 u16OutputOrder8_11,
481 MS_U16 u16OutputOrder12_13)
482 {
483 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
484 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
485 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
486 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
487
488 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
489 {
490 MS_U8 u8Clk = 0;
491 MS_U8 u8LaneNum = 0;
492 MS_BOOL bSkip = TRUE;
493 MS_U8 u8Count = 0;
494 MS_U8 u8Count1 = 0;
495 MS_U8 u8StartLane = 0;
496
497 //check lane num
498 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
499 if(u8LaneNum!=0)
500 {
501 bSkip = FALSE;
502 }
503 else
504 {
505 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //open all clk
506 bSkip = TRUE;
507 }
508
509 //count clk
510 if(!bSkip)
511 {
512 u8Clk = 0;
513 u8StartLane = 0;
514 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP1) ; u8Count++ )
515 {//lane 0 - lane 3
516 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
517 {
518 u8Count1 = 0;
519 do
520 {
521 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
522 {
523 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
524 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
525 break;
526 }
527 u8Count1 ++;
528 }
529 while(u8Count1<VBY1_CLK_TBL_ROW);
530 }
531 u16OutputOrder0_3 /= PINMAPPING_EXP;
532 }
533
534 u8StartLane = 4;
535 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP2) ; u8Count++ )
536 {//lane 4 - lane 7
537 if( ( u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
538 {
539 u8Count1 = 0;
540 do
541 {
542 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
543 {
544 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
545 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
546 break;
547 }
548 u8Count1 ++;
549 }
550 while(u8Count1<VBY1_CLK_TBL_ROW);
551 }
552 u16OutputOrder4_7 /= PINMAPPING_EXP;
553 }
554
555 u8StartLane = 8;
556 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP3) ; u8Count++ )
557 {//lane 8 - lane 11
558 if( ( u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
559 {
560 u8Count1 = 0;
561 do
562 {
563 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
564 {
565 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
566 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
567 break;
568 }
569 u8Count1 ++;
570 }
571 while(u8Count1<VBY1_CLK_TBL_ROW);
572 }
573 u16OutputOrder8_11 /= PINMAPPING_EXP;
574
575 }
576
577 u8StartLane = 12;
578 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP4) ; u8Count++ )
579 {//lane 12 - lane 13
580 if( ( u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
581 {
582 u8Count1 = 0;
583 do
584 {
585 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
586 {
587 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
588 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
589 break;
590 }
591 u8Count1 ++;
592 }
593 while(u8Count1<VBY1_CLK_TBL_ROW);
594 }
595 u16OutputOrder12_13 /= PINMAPPING_EXP;
596 }
597
598 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u8Clk, 0x1F);
599 }
600 }
601 else
602 {
603 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
604 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
605 {
606 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
607 {
608 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
609 }
610 else
611 {
612 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
613 }
614 }
615 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
616 {//LVDS
617 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
618 }
619 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
620 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
621 {
622 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
623 }
624 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)
625 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
626 {
627 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
628 }
629 else
630 {
631 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
632 }
633 }
634 }
635 #endif
636
MHal_Output_Channel_Order(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)637 void MHal_Output_Channel_Order(void *pInstance,
638 MS_U8 Type,
639 MS_U16 u16OutputOrder0_3,
640 MS_U16 u16OutputOrder4_7,
641 MS_U16 u16OutputOrder8_11,
642 MS_U16 u16OutputOrder12_13)
643 {
644 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
645 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
646 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
647 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
648
649 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
650 {
651 MOD_W2BYTE(REG_MOD_BK00_08_L, u16OutputOrder0_3);
652 MOD_W2BYTE(REG_MOD_BK00_09_L, u16OutputOrder4_7);
653 MOD_W2BYTE(REG_MOD_BK00_0A_L, u16OutputOrder8_11);
654 MOD_W2BYTE(REG_MOD_BK00_0B_L, u16OutputOrder12_13);
655 }
656 else
657 {
658 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
659 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
660 {
661 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // 2 Divisoin
662 {
663 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x6420);
664 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7531);
665 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
666 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
667 }
668 else
669 {
670 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
671 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
672 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
673 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
674 }
675 }
676 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
677 {//LVDS
678 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x10DC);
679 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x5432);
680 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x9876);
681 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0xFEBA);
682 }
683 else
684 {// default is VB1 4lane/2lane
685 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
686 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
687 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
688 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
689 }
690 }
691
692 }
693
MHal_PQ_Clock_Gen_For_Gamma(void * pInstance)694 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance)
695 {
696 W2BYTEMSK(REG_CLKGEN0_52_L, 0x00, 0x07);
697 }
698
MHal_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)699 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping)
700 {
701 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
702 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
703
704 if(u8Mapping & GAMMA_MAPPING)
705 {
706 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_74_L, (u8Mapping & GAMMA_10BIT_MAPPING)? BIT(15):0, BIT(15));
707 }
708 else
709 {
710 PNL_ASSERT(0, "Invalid eSupportGammaMapMode [%d] Passed to [%s], please make sure the u8Mapping[%d] is valid\n.",
711 u8Mapping, __FUNCTION__, u8Mapping);
712 }
713 }
714
Hal_VOP_Is_GammaMappingMode_enable(void * pInstance)715 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance)
716 {
717 // Only support 1024 entry
718 return TRUE;
719 }
720
721 // After A5, 8 bit mode only support burst write!!!
Hal_VOP_Is_GammaSupportSignalWrite(void * pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)722 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)
723 {
724 if( u8Mapping == E_DRVPNL_GAMMA_10BIT_MAPPING )
725 return TRUE;
726 else
727 return FALSE;
728 }
729
730
hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)731 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
732 {
733 MS_U16 u16Delay = 0xFFFF;
734 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
735 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
736
737 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write SC%tu [ch %d][addr 0x%x]: 0x%x \n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16Addr, u16GammaValue);
738
739 if (!bBurstWrite )
740 {
741 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
742 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
743
744 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6C_L, u16Addr, 0x3FF); // set address port
745 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_6E_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
746
747 // kick off write
748 switch(u8Channel)
749 {
750 case 0: // Red
751 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(5), BIT(5));
752 break;
753
754 case 1: // Green
755 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(6), BIT(6));
756 break;
757
758 case 2: // Blue
759 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(7), BIT(7));
760 break;
761 }
762
763 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
764 }
765 else
766 {
767
768 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_72_L, u16GammaValue, 0xFFF);
769 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK00_7F_L, 0x00); // make little time delay
770 }
771
772
773 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
774
775 }
776
777
hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)778 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
779 {
780 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
781 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
782
783 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of SC%tu %d is 0x%x\n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16MaxGammaValue);
784 #ifdef MONACO_SC2
785 if(pPNLInstancePrivate->u32DeviceID == 0)
786 {
787 #endif
788 switch(u8Channel)
789 {
790 case 0: // max. Red
791 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 0
792 break;
793
794 case 1: // max. Green
795 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 1
796 break;
797
798 case 2: //max. Blue
799 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
800 break;
801 }
802 #ifdef MONACO_SC2
803 }else //Nike
804 {
805 switch(u8Channel)
806 {
807 case 0: // max. Red
808 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7A_L , u16MaxGammaValue, 0xFFF); // max. base 0
809 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7B_L , u16MaxGammaValue, 0xFFF); // max. base 1
810 break;
811
812 case 1: // max. Green
813 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7C_L , u16MaxGammaValue, 0xFFF); // max. base 0
814 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 1
815 break;
816
817 case 2: //max. Blue
818 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 0
819 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
820 break;
821 }
822
823 }
824 #endif
825 }
826
827 /////////////////////////////////////////////////////////////////////////////
828 // Gamma format (12 bit LUT)
829 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
830 // 1 set uses 2 bytes of memory.
831 //
832 // [T2 and before ] N = 256
833 // [T3] N = 256 or 1024
834 // ______________________________________________________________________________
835 // Byte | 0 1 2 n-1 n
836 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
837 // 3:0 3:0 11:4 11:4 3:0 11:4
838 //
839
Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)840 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
841 {
842 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
843 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
844
845 MS_U16 u16Addr = 0;
846 MS_U16 u16CodeTableIndex = u16Addr/2*3;
847 MS_U16 u16GammaValue = 0;
848 MS_U16 u16MaxGammaValue = 0;
849 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
850 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
851
852 // Go to burst write if not support
853 if ( bUsingBurstWrite )
854 {
855 // 1. initial burst write address, LUT_ADDR[7:0]
856 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_71_L, 0x00 , 0x3FF);
857
858 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
859 switch(u8Channel)
860 {
861 case 0: // Red
862 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, 0x00 , BIT(6) | BIT(5) );
863 break;
864
865 case 1: // Green
866 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(5) , BIT(6) | BIT(5) );
867 break;
868
869 case 2: // Blue
870 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(6) , BIT(6) | BIT(5) );
871 break;
872 }
873
874 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
875 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(7) , BIT(7)); // Burst write enable
876
877 }
878
879 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
880 // write gamma table per one channel
881 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
882 {
883 // gamma x
884 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
885 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
886
887 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
888 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
889
890 if(u16MaxGammaValue < u16GammaValue)
891 {
892 u16MaxGammaValue = u16GammaValue;
893 }
894
895 // write gamma value
896 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
897 u16Addr++;
898
899 // gamma x+1
900 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
901 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
902
903 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
904
905 if(u16MaxGammaValue < u16GammaValue)
906 {
907 u16MaxGammaValue = u16GammaValue;
908 }
909
910 // write gamma value
911 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
912 u16Addr++;
913 }
914
915 if ( bUsingBurstWrite )
916 {
917 // 5. after finish burst write data of one channel, disable burst write mode
918 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, 0x00 , BIT(7));
919 }
920
921 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
922 }
923 /////////////////////////////////////////////////////////////////////////////
924 // Gamma format (12 bit LUT)
925 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
926 // 1 set uses 2 bytes of memory.
927 //
928 // [T2 and before ] N = 256
929 // [T3] N = 256 or 1024
930 // ______________________________________________________________________________
931 // Byte | 0 1 2 n-1 n
932 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
933 // 3:0 3:0 11:4 11:4 3:0 11:4
934 //
935 #ifdef MONACO_SC2
Hal_PNL_Set12BitGammaPerChannel_SC2(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)936 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
937 {
938 MS_U16 u16Addr = 0;
939 MS_U16 u16CodeTableIndex = u16Addr/2*3;
940 MS_U16 u16GammaValue = 0;
941 MS_U16 u16MaxGammaValue = 0;
942 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
943 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
944 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
945 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
946
947 // Go to burst write if not support
948 if ( bUsingBurstWrite )
949 {
950 // 1. initial burst write address, LUT_ADDR[7:0]
951 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
952
953 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
954 switch(u8Channel)
955 {
956 case 0: // Red
957 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
958 break;
959
960 case 1: // Green
961 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
962 break;
963
964 case 2: // Blue
965 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
966 break;
967 }
968
969 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
970 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
971
972 }
973
974 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
975 // write gamma table per one channel
976 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
977 {
978 // gamma x
979 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
980 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
981
982 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
983 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
984
985 if(u16MaxGammaValue < u16GammaValue)
986 {
987 u16MaxGammaValue = u16GammaValue;
988 }
989
990 // write gamma value
991 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
992 u16Addr++;
993
994 // gamma x+1
995 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
996 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
997
998 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
999
1000 if(u16MaxGammaValue < u16GammaValue)
1001 {
1002 u16MaxGammaValue = u16GammaValue;
1003 }
1004
1005 // write gamma value
1006 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
1007 u16Addr++;
1008 }
1009
1010 if ( bUsingBurstWrite )
1011 {
1012 // 5. after finish burst write data of one channel, disable burst write mode
1013 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(0));
1014 }
1015
1016 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
1017 }
1018 #endif
1019 // src : 1 (scaler lpll)
1020 // src : 0 (frc lpll)
MHal_PNL_FRC_lpll_src_sel(void * pInstance,MS_U8 u8src)1021 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src)
1022 {
1023 if (u8src > 1)
1024 {
1025 return FALSE;
1026 }
1027 else
1028 {
1029 //Not support two LPLL (frc lpll) for Manhattan
1030 #if 0
1031 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F);
1032 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8));
1033
1034 if(u8src==0)
1035 {
1036 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F);
1037 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8));
1038 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0
1039 }
1040 #endif
1041 return TRUE;
1042 }
1043
1044 }
1045
_MHal_PNL_GetSupportedLPLLIndex(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz,PNL_LPLL_TYPE_SEL lpll_type_sel)1046 static MS_U8 _MHal_PNL_GetSupportedLPLLIndex(void *pInstance,
1047 PNL_TYPE eLPLL_Type,
1048 PNL_MODE eLPLL_Mode,
1049 MS_U64 ldHz, PNL_LPLL_TYPE_SEL lpll_type_sel)
1050 {
1051 MS_U8 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1052 #if defined (__aarch64__)
1053 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
1054 #else
1055 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
1056 #endif
1057
1058 /// Mini LVDS, EPI34/28, LVDS_1CH, Vx1_1P are 1P structure
1059 if(!((eLPLL_Type == E_PNL_TYPE_TTL)||
1060 ((eLPLL_Type == E_PNL_TYPE_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
1061 ((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
1062 (eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_1LANE)||(eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_1LANE)||
1063 ((eLPLL_Type >= E_PNL_LPLL_MINILVDS_2CH_3P_8BIT)&&(eLPLL_Type <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT))||
1064 ((eLPLL_Type >= E_PNL_LPLL_EPI34_2P)&&(eLPLL_Type <= E_PNL_LPLL_EPI28_4P))))
1065 {
1066 ldHz/=2;
1067 }
1068
1069 switch(lpll_type_sel)
1070 {
1071 default:
1072 case E_PNL_LPLL_VIDEO:
1073 {
1074 switch (eLPLL_Type)
1075 {
1076 case E_PNL_TYPE_DAC_P:
1077 case E_PNL_TYPE_DAC_I:
1078 // For Maxim HDMI Tx case, use this first,
1079 // need to refine after confirm with RD
1080 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz;
1081 break;
1082
1083 case E_PNL_TYPE_TTL:
1084 if (ldHz < 250000000UL)
1085 {
1086 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to25MHz;
1087 }
1088 else if ((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1089 {
1090 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to50MHz;
1091 }
1092 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1093 {
1094 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_50to100MHz;
1095 }
1096 else
1097 {
1098 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_100to150MHz;
1099 }
1100 break;
1101
1102 case E_PNL_TYPE_LVDS:
1103 switch (eLPLL_Mode)
1104 {
1105 case E_PNL_MODE_SINGLE:
1106 if (ldHz < 500000000UL)
1107 {
1108 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz;
1109 }
1110 else
1111 {
1112 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz;
1113 }
1114 break;
1115
1116 default:
1117 case E_PNL_MODE_DUAL:
1118 if (ldHz < 250000000UL)
1119 {
1120 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz;
1121 }
1122 else if ((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1123 {
1124 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz;
1125 }
1126 else
1127 {
1128 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz;
1129 }
1130 break;
1131 }
1132 break;
1133
1134 case E_PNL_TYPE_HS_LVDS:
1135
1136 switch (eLPLL_Mode)
1137 {
1138 case E_PNL_MODE_SINGLE:
1139 if(ldHz < 500000000UL)
1140 {
1141 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz;
1142 }
1143 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1144 {
1145 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz;
1146 }
1147 else
1148 {
1149 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz;
1150 }
1151 break;
1152
1153 default:
1154 case E_PNL_MODE_DUAL:
1155 if(ldHz < 250000000UL)
1156 {
1157 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz;
1158 }
1159 else if((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1160 {
1161 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz;
1162 }
1163 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1164 {
1165 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz;
1166 }
1167 else
1168 {
1169 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz;
1170 }
1171 break;
1172 }
1173 break;
1174 ///Not Support
1175 #if 0
1176 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
1177 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz;
1178 break;
1179
1180 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
1181 if((ldHz >= 500000000) && (ldHz < 1000000000))
1182 {
1183 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz;
1184 }
1185 else
1186 {
1187 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz;
1188 }
1189 break;
1190
1191 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
1192 if((ldHz >= 500000000) && (ldHz < 1000000000))
1193 {
1194 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz;
1195 }
1196 else
1197 {
1198 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz;
1199 }
1200 break;
1201
1202 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
1203 if((ldHz >= 500000000) && (ldHz < 666700000))
1204 {
1205 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz;
1206 }
1207 else
1208 {
1209 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz;
1210 }
1211 break;
1212
1213 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
1214 if ((ldHz <= 500000000) && (ldHz < 666700000))
1215 {
1216 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz;
1217 }
1218 else if((ldHz >= 666700000) && (ldHz < 1333300000))
1219 {
1220 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz;
1221 }
1222 else
1223 {
1224 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz;
1225 }
1226 break;
1227
1228 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
1229 if ((ldHz <= 500000000) && (ldHz < 670000000))
1230 {
1231 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz;
1232 }
1233 else if((ldHz >= 670000000) && (ldHz < 1330000000))
1234 {
1235 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz;
1236 }
1237 else
1238 {
1239 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz;
1240 }
1241 break;
1242
1243 case E_PNL_LPLL_EPI34_4P:
1244 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_95to150MHz;
1245 break;
1246
1247 case E_PNL_LPLL_EPI34_6P:
1248 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz;
1249 break;
1250
1251 case E_PNL_LPLL_EPI34_8P:
1252 if((ldHz >= 800000000) && (ldHz < 940000000))
1253 {
1254 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to94MHz;
1255 }
1256 else if((ldHz >= 940000000) && (ldHz < 1880000000))
1257 {
1258 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_94to188MHz;
1259 }
1260 else
1261 {
1262 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz;
1263 }
1264 break;
1265
1266 case E_PNL_LPLL_EPI28_4P:
1267 if((ldHz >= 800000000) && (ldHz < 1140000000))
1268 {
1269 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz;
1270 }
1271 else
1272 {
1273 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz;
1274 }
1275 break;
1276 #endif
1277
1278 case E_PNL_LPLL_EPI28_6P:
1279 if(ldHz < 1500000000UL)
1280 {
1281 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz;
1282 }
1283 else if((ldHz >= 1500000000UL) && (ldHz < 1800000000UL))
1284 {
1285 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz;
1286 }
1287 else
1288 {
1289 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz;
1290 }
1291 break;
1292
1293 case E_PNL_LPLL_EPI28_8P:
1294 if(ldHz < 1500000000UL)
1295 {
1296 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to150MHz;
1297 }
1298 else if((ldHz >= 1500000000UL) && (ldHz < 2400000000UL))
1299 {
1300 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to240MHz;
1301 }
1302 else
1303 {
1304 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_240to300MHz;
1305 }
1306 break;
1307 case E_PNL_LPLL_EPI24_12P:
1308 if(ldHz < 1500000000UL)
1309 {
1310 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to150MHz;
1311 }
1312 else
1313 {
1314 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to300MHz;
1315 }
1316 break;
1317 case E_PNL_LPLL_EPI28_12P:
1318 if(ldHz < 1500000000UL)
1319 {
1320 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to150MHz;
1321 }
1322 else
1323 {
1324 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to300MHz;
1325 }
1326 break;
1327 /*
1328 case E_PNL_LPLL_EPI34_12P:
1329 case E_PNL_LPLL_EPI24_12P:
1330 break;
1331 */
1332
1333 case E_PNL_LPLL_VBY1_10BIT_8LANE:
1334 if(ldHz < 1500000000UL)
1335 {
1336 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz;
1337 }
1338 else
1339 {
1340 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz;
1341 }
1342 printf("@@11=%u\n",u8SupportedLPLLIndex);
1343 break;
1344
1345 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1346 if(ldHz < 750000000UL)
1347 {
1348 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz;
1349 }
1350 else
1351 {
1352 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz;
1353 }
1354 break;
1355 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1356 if(ldHz < 375000000UL)
1357 {
1358 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz;
1359 }
1360 else
1361 {
1362 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz;
1363 }
1364 break;
1365 #if 0
1366 case E_PNL_LPLL_VBY1_10BIT_1LANE:
1367 if(ldHz < 400000000UL)
1368 {
1369 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to40MHz;
1370 }
1371 else
1372 {
1373 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to80MHz;
1374 }
1375 break;
1376 #endif
1377
1378 case E_PNL_LPLL_VBY1_8BIT_8LANE:
1379 if(ldHz < 1500000000UL)
1380 {
1381 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz;
1382 }
1383 else if((ldHz >= 1500000000UL) && (ldHz < 2200000000UL))
1384 {
1385 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz;
1386 }
1387 else
1388 {
1389 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz;
1390 }
1391 break;
1392
1393 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1394 if(ldHz < 750000000UL)
1395 {
1396 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz;
1397 }
1398 else if((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1399 {
1400 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz;
1401 }
1402 else
1403 {
1404 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz;
1405 }
1406 break;
1407
1408 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1409 if(ldHz < 375000000UL)
1410 {
1411 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz;
1412 }
1413 else if((ldHz >= 375000000UL) && (ldHz < 500000000UL))
1414 {
1415 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz;
1416 }
1417 else
1418 {
1419 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz;
1420 }
1421 break;
1422 #if 0
1423 case E_PNL_LPLL_VBY1_8BIT_1LANE:
1424 if(ldHz < 400000000UL)
1425 {
1426 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to40MHz;
1427 }
1428 else if((ldHz >= 400000000UL) && (ldHz < 500000000UL))
1429 {
1430 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to50MHz;
1431 }
1432 else
1433 {
1434 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_50to80MHz;
1435 }
1436 break;
1437
1438 case E_PNL_LPLL_VBY1_10BIT_16LANE:
1439 if(ldHz < 2000000000UL)
1440 {
1441 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to200MHz;
1442 }
1443 else
1444 {
1445 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to300MHz;
1446 }
1447 break;
1448 case E_PNL_LPLL_VBY1_8BIT_16LANE:
1449 if(ldHz < 2000000000UL)
1450 {
1451 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to200MHz;
1452 }
1453 else
1454 {
1455 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to300MHz;
1456 }
1457 break;
1458 #endif
1459 case E_PNL_LPLL_USI_T_8BIT_12P:
1460 if(ldHz < 1500000000UL)
1461 {
1462 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz;
1463 }
1464 else
1465 {
1466 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz;
1467 }
1468 break;
1469 case E_PNL_LPLL_USI_T_10BIT_12P:
1470 if(ldHz < 1500000000UL)
1471 {
1472 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz;
1473 }
1474 else
1475 {
1476 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz;
1477 }
1478 break;
1479 case E_PNL_LPLL_ISP_8BIT_12P:
1480 if(ldHz < 1500000000UL)
1481 {
1482 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz;
1483 }
1484 else
1485 {
1486 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz;
1487 }
1488 break;
1489 #if 0
1490 case E_PNL_LPLL_ISP_8BIT_6P_D:
1491 if(ldHz < 1500000000UL)
1492 {
1493 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz;
1494 }
1495 else
1496 {
1497 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to330MHz;
1498 }
1499 break;
1500 #endif
1501 default:
1502 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1503 break;
1504 }
1505 }
1506 break;
1507 case E_PNL_LPLL_OSD:
1508 {
1509 switch (eLPLL_Type)
1510 {
1511 case E_PNL_TYPE_HS_LVDS:
1512 {
1513 if(ldHz < 250000000UL)
1514 {
1515 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz;
1516 }
1517 else if((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1518 {
1519 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to50MHz;
1520 }
1521 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1522 {
1523 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_50to100MHz;
1524 }
1525 else
1526 {
1527 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_100to150MHz;
1528 }
1529 }
1530 break;
1531
1532 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1533 if(ldHz < 1500000000UL)
1534 {
1535 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to150MHz;
1536 }
1537 else
1538 {
1539 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to340MHz;
1540 }
1541 break;
1542
1543 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1544 if(ldHz < 750000000UL)
1545 {
1546 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to75MHz;
1547 }
1548 else
1549 {
1550 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to150MHz;
1551 }
1552 break;
1553
1554 case E_PNL_LPLL_VBY1_10BIT_1LANE:
1555 if(ldHz < 375000000UL)
1556 {
1557 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to37_5MHz;
1558 }
1559 else
1560 {
1561 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to75MHz;
1562 }
1563 break;
1564
1565 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1566 if(ldHz < 1500000000UL)
1567 {
1568 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to150MHz;
1569 }
1570 else if((ldHz >= 1500000000UL) && (ldHz < 2200000000UL))
1571 {
1572 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to200MHz;
1573 }
1574 else
1575 {
1576 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_200to340MHz;
1577 }
1578 break;
1579
1580 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1581 if(ldHz < 750000000UL)
1582 {
1583 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to75MHz;
1584 }
1585 else if((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1586 {
1587 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to100MHz;
1588 }
1589 else
1590 {
1591 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_100to150MHz;
1592 }
1593 break;
1594
1595 case E_PNL_LPLL_VBY1_8BIT_1LANE:
1596 if(ldHz < 375000000UL)
1597 {
1598 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to37_5MHz;
1599 }
1600 else if((ldHz >= 380000000UL) && (ldHz < 500000000UL))
1601 {
1602 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to50MHz;
1603 }
1604 else
1605 {
1606 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_50to75MHz;
1607 }
1608 break;
1609
1610 default:
1611 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
1612 break;
1613 }
1614 }
1615 break;
1616 }
1617 return u8SupportedLPLLIndex;
1618 }
1619
_MHal_PNL_DumpLPLLTable(void * pInstance,MS_U8 LPLLTblIndex,PNL_LPLL_TYPE_SEL lpll_type_sel)1620 static void _MHal_PNL_DumpLPLLTable(void *pInstance, MS_U8 LPLLTblIndex, PNL_LPLL_TYPE_SEL lpll_type_sel)
1621 {
1622 if(lpll_type_sel == E_PNL_LPLL_VIDEO)
1623 {
1624 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_MAX)
1625 {
1626 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1627 return;
1628 }
1629
1630 int indexCounter = 0;
1631
1632 for(indexCounter = 0 ; indexCounter<LPLL_REG_NUM; indexCounter++)
1633 {
1634 if (LPLLSettingTBL[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1635 {
1636 MsOS_DelayTaskUs(LPLLSettingTBL[LPLLTblIndex][indexCounter].value);
1637 continue; // step forward to next register setting.
1638 }
1639
1640 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address),
1641 LPLLSettingTBL[LPLLTblIndex][indexCounter].value,
1642 LPLLSettingTBL[LPLLTblIndex][indexCounter].mask);
1643 }
1644 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1645 }
1646 else
1647 {
1648 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
1649 {
1650 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1651 return;
1652 }
1653
1654 int indexCounter = 0;
1655
1656 for(indexCounter = 0 ; indexCounter<LPLL_EXT_REG_NUM; indexCounter++)
1657 {
1658 if (LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1659 {
1660 MsOS_DelayTaskUs(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value);
1661 continue; // step forward to next register setting.
1662 }
1663
1664 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address),
1665 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value,
1666 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].mask);
1667 }
1668 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1669 }
1670 }
1671
MHal_PNL_Init_LPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)1672 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
1673 {
1674 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1675 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1676 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1677 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1678 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1679 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1680
1681 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_VIDEO);
1682
1683 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1684 {
1685 printf("Not Supported LPLL Type, skip LPLL Init\n");
1686 return;
1687 }
1688
1689 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_VIDEO);
1690
1691
1692 MHal_MOD_PVDD_Power_Setting(pInstance, pPNLResourcePrivate->sthalPNL._bPVDD_2V5); // Einstein is always use 3.3V PVDD Power.
1693 }
1694
MHal_PNL_Get_Loop_DIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1695 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1696 {
1697 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1698 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1699
1700 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1701 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1702
1703 MS_U16 u16loop_div = 0;
1704 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1705 #if defined (__aarch64__)
1706 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1707 #else
1708 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1709 #endif
1710 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1711
1712 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1713 {
1714 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1715 u16loop_div = 0 ;
1716 }
1717 else
1718 {
1719 u16loop_div = u16LoopDiv[u8SupportedLPLLLIndex];
1720 }
1721
1722 // For Maxim HDMI Tx case, loop div follow HDMI SPEC
1723 if ((E_PNL_TYPE_DAC_P == eLPLL_Type) || (E_PNL_TYPE_DAC_I == eLPLL_Type))
1724 {
1725 if (ldHz < 500000000UL)
1726 {
1727 u16loop_div = 16;
1728 }
1729 else if ((ldHz >= 500000000UL) && (ldHz < 1200000000UL))
1730 {
1731 u16loop_div = 8;
1732 }
1733 else if ((ldHz >= 1200000000UL) && (ldHz < 2500000000UL))
1734 {
1735 u16loop_div = 4;
1736 }
1737 else if ((ldHz >= 2500000000UL) && (ldHz < 3000000000UL))
1738 {
1739 if ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16HTotal < 3000) &&
1740 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16VTotal < 2000))
1741 {
1742 u16loop_div = 2; // 1080px12bits, 297MHz
1743 }
1744 else
1745 {
1746 u16loop_div = 4; // 4K@30, 297MHz
1747 }
1748 }
1749 else if((ldHz >= 3000000000UL) && (ldHz < 6500000000UL))
1750 {
1751 u16loop_div = 2;
1752 }
1753 else
1754 {
1755 u16loop_div = 1;
1756 }
1757 }
1758
1759 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_div=%u\n", u16loop_div);
1760
1761 u16loop_div *= 2;
1762 return u16loop_div;
1763 }
1764
MHal_PNL_Get_LPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1765 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1766 {
1767 MS_U16 u16loop_gain = 0;
1768 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1769 #if defined (__aarch64__)
1770 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1771 #else
1772 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1773 #endif
1774 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1775
1776 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1777 {
1778 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1779 u16loop_gain = 0 ;
1780 }
1781 else
1782 {
1783 u16loop_gain = u16LoopGain[u8SupportedLPLLLIndex];
1784 }
1785
1786 // For Maxim HDMI Tx case, loop gain follow HDMI SPEC
1787 if ((E_PNL_TYPE_DAC_P == eLPLL_Type) || (E_PNL_TYPE_DAC_I == eLPLL_Type))
1788 {
1789 u16loop_gain = 4;
1790 }
1791
1792 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_gain=%u\n", u16loop_gain);
1793 return u16loop_gain;
1794 }
1795
1796 #define SKIP_TIMING_CHANGE_CAP TRUE
Hal_PNL_SkipTimingChange_GetCaps(void * pInstance)1797 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance)
1798 {
1799 #if (SKIP_TIMING_CHANGE_CAP)
1800 return TRUE;
1801 #else
1802 return FALSE;
1803 #endif
1804 }
1805
MHal_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1806 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1807 {
1808 if (bSetMode == TRUE)
1809 {
1810 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15));
1811 }
1812 else
1813 {
1814 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15));
1815 }
1816 }
1817
MHal_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)1818 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo)
1819 {
1820 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1821 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1822 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1823 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1824
1825 if (lvdsresinfo.bEnable)
1826 {
1827 if (lvdsresinfo.u16channel & BIT(0)) // Channel A
1828 {
1829 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1830 {
1831 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15));
1832 }
1833 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1834 {
1835 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14));
1836 }
1837 }
1838 if (lvdsresinfo.u16channel & BIT(1)) // Channel B
1839 {
1840 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1841 {
1842 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13));
1843 }
1844 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1845 {
1846 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12));
1847 }
1848 }
1849
1850 if( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) )
1851 {
1852 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1: three_d_flag
1853 }
1854 }
1855 else
1856 {
1857 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12)));
1858
1859 if( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) )
1860 {
1861 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1: three_d_flag
1862 }
1863 }
1864 }
1865
1866 ////////////////////////////////////////////////////////////////////////
1867 // Turn OD function
1868 ////////////////////////////////////////////////////////////////////////
MHal_PNL_OverDriver_Init(void * pInstance,MS_PHY u32OD_MSB_Addr,MS_PHY u32OD_MSB_limit,MS_PHY u32OD_LSB_Addr,MS_PHY u32OD_LSB_limit,MS_U8 u8MIUSel)1869 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_PHY u32OD_LSB_Addr, MS_PHY u32OD_LSB_limit, MS_U8 u8MIUSel)
1870 {
1871 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1872 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1873 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK16_61_L,u8MIUSel<<8,BIT(8)|BIT(9)); // OD MIU select
1874
1875 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_15_L, (MS_U16)(u32OD_MSB_Addr & 0xFFFF)); // OD MSB request base address
1876 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_16_L, (MS_U16)((u32OD_MSB_Addr >> 16) & 0x00FF), 0x00FF); // OD MSB request base address
1877 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_Addr >> 24) & 0x0003), 0x0003); // OD MSB request base address
1878 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_17_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD MSB request address limit
1879 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_18_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD MSB request address limit
1880 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_limit >> 24) & 0x0003)<<2, 0x000C); // OD MSB request address limit
1881 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_39_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer write address limit
1882 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer write address limit
1883 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3B_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer read address limit
1884 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3C_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer read address limit
1885 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_4F_L, (MS_U16)(u32OD_LSB_Addr & 0xFFFF)); // OD LSB request base address
1886 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_Addr >> 16) & 0x00FF), 0x00FF); // OD LSB request base address
1887 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_limit & 0x00FF) << 8), 0xFF00); // OD LSB request limit address
1888 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_51_L, (MS_U16)((u32OD_LSB_limit >> 8) & 0xFFFF)); // OD LSB request limit address
1889
1890 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1A_L, 0x4020); // OD request rFIFO limit threshold, priority threshold
1891 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1C_L, 0x4020); // OD request wFIFO limit threshold, priority threshold
1892 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x00, BIT(14)); // OD strength gradually bypass
1893 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x2F00, 0x3F00); // OD strength gradually slop
1894 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_12_L, 0x0C, 0xFF); // OD active threshold
1895
1896 }
1897
MHal_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1898 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable)
1899 {
1900 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1901 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1902
1903 // When OD enable, disable OD/RGBW SRAM PowerDown.
1904 #ifdef CONFIG_MSTAR_SRAMPD
1905 if(pPNLInstancePrivate->u32DeviceID == 0)
1906 {
1907 if(bEnable)
1908 {
1909 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_10_L, 0, BIT(0)); //OD SRAM PD Enable : SC_SPD_BK3F_10[0]
1910 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, BIT(8), BIT(8)); //OD Clock gate : ~SC_SPD_BK3F_50[8]
1911 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(15)); //OD Bypass Enable :SC_OD_BK16_6F[15]
1912 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_10_L, 0, BIT(1)); // RGBW SRAM PD Enable : SC_SPD_BK3F_10[1]
1913 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, BIT(9), BIT(9)); // RGBW Clock Gate : ~SC_SPD_BK3F_50[9]
1914 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(12)); // RGBW bypass enable :SC_OD_BK16_6F[12]
1915 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, BIT(13), BIT(13)); // RGBW bypass enable : ~SC_OD_BK16_6F[13]
1916
1917 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_17_L, 0, BIT(0)); //M+ SRAM PD Enable : SC_SPD_BK3F_17[0]
1918 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, BIT(10), BIT(10)); //M+ Clock gate : ~SC_SPD_BK3F_50[10]
1919 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L,0 , BIT(12)); // M+ bypass enable :SC_OD_BK16_6F[12]
1920 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(13)); // M+ bypass enable : ~SC_OD_BK16_6F[13]
1921
1922 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_0B_L, 0, BIT(4)); //Demura SRAM PD Enable : SC_SPD_BK3F_0B[4]
1923 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK77_26_L, 0, BIT(14)); //Demura Clock Gate : SC_BK77_26[14]
1924 W2BYTEMSK(REG_RVD_45_L, 0, BIT(0)); //Demura Clock gate : BK100A_CLKGEN2_45[0]
1925 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK77_26_L, 0, BIT(15)); //Demura Clock Gate : SC_BK77_26[15]
1926 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_0B_L, 0, BIT(5)); //DGA_GAMMA SRAM PD Enable : SC_SPD_BK3F_0B[5]
1927 }
1928 else
1929 {
1930 #if 0 // Skip power down for bring up
1931 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_10_L, BIT(0), BIT(0)); //OD SRAM PD Enable : SC_SPD_BK3F_10[0]
1932 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, 0, BIT(8)); //OD Clock gate : ~SC_SPD_BK3F_50[8]
1933 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, BIT(15), BIT(15)); //OD Bypass Enable :SC_OD_BK16_6F[15]
1934 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_10_L, BIT(1), BIT(1)); // RGBW SRAM PD Enable : SC_SPD_BK3F_10[1]
1935 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, 0, BIT(9)); // RGBW Clock Gate : ~SC_SPD_BK3F_50[9]
1936 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, BIT(12), BIT(12)); // RGBW bypass enable :SC_OD_BK16_6F[12]
1937 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(13)); // RGBW bypass enable : ~SC_OD_BK16_6F[13]
1938
1939 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_17_L, BIT(0), BIT(0)); //M+ SRAM PD Enable : SC_SPD_BK3F_17[0]
1940 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, 0, BIT(10)); //M+ Clock gate : ~SC_SPD_BK3F_50[10]
1941 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L,0 , BIT(12)); // M+ bypass enable :SC_OD_BK16_6F[12]
1942 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(13)); // M+ bypass enable : ~SC_OD_BK16_6F[13]
1943
1944 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_0B_L, BIT(4), BIT(4)); //Demura SRAM PD Enable : SC_SPD_BK3F_0B[4]
1945 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK77_26_L, BIT(14), BIT(14)); //Demura Clock Gate : SC_BK77_26[14]
1946 W2BYTEMSK(REG_RVD_45_L, BIT(0), BIT(0)); //Demura Clock gate : BK100A_CLKGEN2_45[0]
1947 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK77_26_L, BIT(15), BIT(15)); //Demura Clock Gate : SC_BK77_26[15]
1948 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_0B_L, BIT(5), BIT(5)); //DGA_GAMMA SRAM PD Enable : SC_SPD_BK3F_0B[5]
1949 #endif
1950 }
1951 }
1952 #endif
1953
1954 // OD mode
1955 // OD used user weight to output blending directly
1956 // OD Enable
1957 if (bEnable)
1958 {
1959 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2D, 0x2F);
1960 }
1961 else
1962 {
1963 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2C, 0x2F);
1964 }
1965 }
1966
MHal_PNL_OverDriver_TBL(void * pInstance,MS_U8 u8ODTbl[1056])1967 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056])
1968 {
1969 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1970 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1971
1972 MS_U16 i;
1973 MS_U8 u8target;
1974 MS_BOOL bEnable;
1975
1976 bEnable = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, BIT(0));
1977 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x00, BIT(0)); // OD enable
1978 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x0E, 0x0E); // OD table SRAM enable, RGB channel
1979
1980 u8target= u8ODTbl[9];
1981 for (i=0; i<272; i++)
1982 {
1983 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_03_L, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
1984 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1985 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, BIT(15)));
1986 }
1987
1988 u8target= u8ODTbl[(272+19)];
1989 for (i=0; i<272; i++)
1990 {
1991 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_06_L, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
1992 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, (i|0x8000), 0x81FF);
1993 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, BIT(15)));
1994 }
1995
1996 u8target= u8ODTbl[(272*2+29)];
1997 for (i=0; i<256; i++)
1998 {
1999 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_09_L, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
2000 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
2001 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, BIT(15)));
2002 }
2003
2004 u8target= u8ODTbl[(272*2+256+39)];
2005 for (i=0; i<256; i++)
2006 {
2007 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0C_L, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
2008 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0B_L, (i|0x8000), 0x81FF);
2009 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0D_L, BIT(15)));
2010 }
2011
2012 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x00, 0x0E); // OD table SRAM enable, RGB channel
2013 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, bEnable, BIT(0)); // OD enable
2014 }
2015
_MHal_PNL_MOD_Swing_Refactor_AfterCAL(void * pInstance,MS_U16 u16Swing_Level)2016 MS_U16 _MHal_PNL_MOD_Swing_Refactor_AfterCAL(void *pInstance, MS_U16 u16Swing_Level)
2017 {
2018 MS_U8 u8ibcal = 0x00;
2019 MS_U16 u16AfterCal_value = 0;
2020 MS_U16 u16Cus_value = 0;
2021
2022 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2023 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2024 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2025 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2026 // =========
2027 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
2028 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
2029 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
2030 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
2031 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
2032 // =========
2033 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
2034 {
2035 default:
2036 case 0:
2037 u8ibcal = 0x15;
2038 break;
2039 case 1:
2040 u8ibcal = 0x1F;
2041 break;
2042 case 2:
2043 u8ibcal = 0x1A;
2044 break;
2045 case 3:
2046 u8ibcal = 0x10;
2047 break;
2048 }
2049 u16Cus_value = (u16Swing_Level) * (pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4)/(u8ibcal + 4);
2050 u16AfterCal_value = (u16Cus_value-40)/10+2;
2051
2052 HAL_MOD_CAL_DBG(printf("\r\n--Swing value after refactor = %d\n", u16AfterCal_value));
2053
2054 return u16AfterCal_value;
2055 }
2056
MHal_PNL_MODSwingRegToRealLevelValue(void * pInstance,MS_U16 u16SwingRegValue)2057 MS_U16 MHal_PNL_MODSwingRegToRealLevelValue(void *pInstance, MS_U16 u16SwingRegValue)
2058 {
2059 MS_U8 u8ibcal = 0x00;
2060 MS_U16 u16SwingRealLevelValue = 0;
2061 MS_U16 u16CusValue = 0;
2062 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2063 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2064 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2065 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2066 // =========
2067 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
2068 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
2069 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
2070 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
2071 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
2072 // =========
2073 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
2074 {
2075 default:
2076 case 0:
2077 u8ibcal = 0x15;
2078 break;
2079 case 1:
2080 u8ibcal = 0x1F;
2081 break;
2082 case 2:
2083 u8ibcal = 0x1A;
2084 break;
2085 case 3:
2086 u8ibcal = 0x10;
2087 break;
2088 }
2089
2090 u16CusValue = ((u16SwingRegValue-2)*10)+40;
2091 u16SwingRealLevelValue=(u16CusValue*(u8ibcal + 4))/(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4);
2092
2093 HAL_MOD_CAL_DBG(printf("\r\n--Swing Real Level Value = %d\n", u16SwingRealLevelValue));
2094
2095 return u16SwingRealLevelValue;
2096 }
2097
MHal_PNL_MOD_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)2098 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level)
2099 {
2100 MS_BOOL bStatus = FALSE;
2101
2102 MS_U16 u16ValidSwing = 0;
2103 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2104 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2105 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2106 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2107
2108 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)||
2109 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS))
2110 {
2111 if(u16Swing_Level>600)
2112 u16Swing_Level=600;
2113 if(u16Swing_Level<40)
2114 u16Swing_Level=40;
2115
2116 u16ValidSwing = _MHal_PNL_MOD_Swing_Refactor_AfterCAL(pInstance, u16Swing_Level);
2117 }
2118 else
2119 {
2120 u16ValidSwing = u16Swing_Level;
2121 }
2122
2123 // Disable HW calibration keep mode first, to make SW icon value can write into register.
2124 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
2125
2126 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2127 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
2128 {
2129 u16ValidSwing &=0x0F;
2130 // vby1 vreg
2131 // ch0+ch1+ch2+ch3
2132 MOD_A_W2BYTE(REG_MOD_A_BK00_20_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2133 // ch4+ch5+ch6+ch7
2134 MOD_A_W2BYTE(REG_MOD_A_BK00_21_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2135 // ch8+ch9+ch10+ch11
2136 MOD_A_W2BYTE(REG_MOD_A_BK00_22_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2137 // ch12+ch13+ch14+ch15
2138 MOD_A_W2BYTE(REG_MOD_A_BK00_23_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2139 }
2140 else
2141 {
2142 u16ValidSwing &=0xFF;
2143 // LVDS fill ICON
2144 // ch0+ch1
2145 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, (u16ValidSwing << 8 | u16ValidSwing));
2146 // ch2+ch3
2147 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, (u16ValidSwing << 8 | u16ValidSwing));
2148 // ch4+ch5
2149 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, (u16ValidSwing << 8 | u16ValidSwing));
2150 // ch6+ch7
2151 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, (u16ValidSwing << 8 | u16ValidSwing));
2152 // ch8+ch9
2153 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, (u16ValidSwing << 8 | u16ValidSwing));
2154 // ch10+ch11
2155 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, (u16ValidSwing << 8 | u16ValidSwing));
2156 // ch12+ch13
2157 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, (u16ValidSwing << 8 | u16ValidSwing));
2158 // ch14+ch15
2159 MOD_A_W2BYTE(REG_MOD_A_BK00_0F_L, (u16ValidSwing << 8 | u16ValidSwing));
2160 }
2161 bStatus = TRUE;
2162
2163 return bStatus;
2164 }
2165
2166 ////////////////////////////////////////////////////////////////////////
2167 // Turn Pre-Emphasis Current function
2168 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_PE_Current(void * pInstance,MS_U16 u16Current_Level)2169 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level)
2170 {
2171 MS_BOOL bStatus = FALSE;
2172 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
2173
2174 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,
2175 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2176 |(u16ValidCurrent << 12 )));
2177
2178 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,
2179 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2180 |(u16ValidCurrent << 12 )));
2181
2182 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,
2183 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2184 |(u16ValidCurrent << 12 )));
2185
2186 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,
2187 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2188 |(u16ValidCurrent << 12 )));
2189
2190 bStatus = TRUE;
2191
2192 return bStatus;
2193 }
2194
MHal_PNL_MOD_PECurrent_Setting(void * pInstance,MS_U16 u16Current_Level,MS_U16 u16Channel_Select)2195 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select)
2196 {
2197 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
2198 MS_U16 u16Ch00_03_mask,u16Ch04_07_mask,u16Ch08_11_mask,u16Ch12_15_mask = 0;
2199
2200 u16Ch00_03_mask = (((u16Channel_Select & BIT(0))? 0x000F:0x00)|((u16Channel_Select & BIT(1))? 0x00F0:0x00)
2201 |((u16Channel_Select & BIT(2))? 0x0F00:0x00)|((u16Channel_Select & BIT(3))? 0xF000:0x00));
2202 u16Ch04_07_mask = (((u16Channel_Select & BIT(4))? 0x000F:0x00)|((u16Channel_Select & BIT(5))? 0x00F0:0x00)
2203 |((u16Channel_Select & BIT(6))? 0x0F00:0x00)|((u16Channel_Select & BIT(7))? 0xF000:0x00));
2204 u16Ch08_11_mask = (((u16Channel_Select & BIT(8))? 0x000F:0x00)|((u16Channel_Select & BIT(9))? 0x00F0:0x00)
2205 |((u16Channel_Select & BIT(10))? 0x0F00:0x00)|((u16Channel_Select & BIT(11))? 0xF000:0x00));
2206 u16Ch12_15_mask = (((u16Channel_Select & BIT(12))? 0x000F:0x00)|((u16Channel_Select & BIT(13))? 0x00F0:0x00)
2207 |((u16Channel_Select & BIT(14))? 0x0F00:0x00)|((u16Channel_Select & BIT(15))? 0xF000:0x00));
2208
2209 if(u16Ch00_03_mask)
2210 {
2211 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L,
2212 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch00_03_mask);
2213 }
2214 else
2215 {
2216 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x00);
2217 }
2218
2219 if(u16Ch04_07_mask)
2220 {
2221 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L,
2222 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch04_07_mask);
2223 }
2224 else
2225 {
2226 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x00);
2227 }
2228
2229 if(u16Ch08_11_mask)
2230 {
2231 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L,
2232 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch08_11_mask);
2233 }
2234 else
2235 {
2236 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x00);
2237 }
2238
2239 if(u16Ch12_15_mask)
2240 {
2241 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L,
2242 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch12_15_mask);
2243 }
2244 else
2245 {
2246 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x00);
2247 }
2248 }
2249
2250 ////////////////////////////////////////////////////////////////////////
2251 // 1.Turn TTL low-power mode function
2252 // 2.Turn internal termination function
2253 // 3.Turn DRIVER BIAS OP function
2254 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_TTL_Resistor_OP(void * pInstance,MS_BOOL bEnble)2255 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL bEnble)
2256 {
2257 MS_BOOL bStatus = FALSE;
2258 if(bEnble)
2259 {
2260 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode
2261 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x001E, 0x001E);
2262
2263 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open)
2264 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F);
2265
2266 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP
2267 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F);
2268 }
2269 else
2270 {
2271 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode
2272 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x0000, 0x001E);
2273
2274 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close)
2275 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F);
2276
2277 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP
2278 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F);
2279 }
2280
2281 bStatus = TRUE;
2282 return bStatus;
2283 }
2284
MHal_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)2285 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam)
2286 {
2287 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2288 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2289 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2290 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2291 pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions = eParam;
2292 }
2293
MHal_PNL_Get_Output_MODE(void * pInstance)2294 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance)
2295 {
2296 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2297 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2298 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2299 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2300 PNL_OUTPUT_MODE eParam = pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions;
2301
2302 return eParam;
2303 }
2304
msReadEfuse(void * pInstance,MS_U8 u8Bank,MS_U32 u32Mask)2305 MS_U32 msReadEfuse(void *pInstance, MS_U8 u8Bank, MS_U32 u32Mask)
2306 {
2307 MS_U32 u32Result = 0;
2308 MS_U8 u8Count = 0;
2309
2310 W2BYTEMSK(0x2050, u8Bank<<2, BMASK(8:2)); /// reg28[8:2]Addr 6~0
2311 W2BYTEMSK(0x2050, BIT(13), BIT(13)); /// Reg28[13] Margin Read
2312 while(R2BYTEMSK(0x2050, BIT(13)) == BIT(13))
2313 {
2314 MsOS_DelayTask(1);
2315 u8Count ++;
2316
2317 if (u8Count >10)
2318 break;
2319 }
2320
2321 u32Result = (R4BYTE(0x2058)& u32Mask); /// reg2C,2D read value
2322 printf("[%s][%d]u32Result=%tx, after mask u32Result=%tx\n", __FUNCTION__, __LINE__,(ptrdiff_t) R4BYTE(0x2058), (ptrdiff_t)u32Result);
2323 return u32Result;
2324
2325 }
2326
msSetVBY1RconValue(void * pInstance)2327 void msSetVBY1RconValue(void *pInstance)
2328 {
2329 MS_U16 u16DefaultICON_Max = 40, u16DefaultICON_Min = 7;
2330 MS_U16 u16DefaultICON = 18;
2331 MS_U32 u32Mask = 0x3F;
2332 MS_BOOL bEfuseMode = FALSE;
2333 MS_U16 u16SwingOffset = 0; // by HW RD request
2334 MS_U16 u16temp = 0;
2335
2336 if(!(_Hal_MOD_External_eFuse()))
2337 {
2338 if (msReadEfuse(pInstance, 0x4E, BIT(6)) == BIT(6))
2339 bEfuseMode = TRUE;
2340
2341 // Disable HW calibration keep mode first, to make SW icon value can write into register.
2342 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
2343
2344 if (bEfuseMode)
2345 {
2346 if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) > u16DefaultICON_Max)
2347 u16temp = u16DefaultICON;
2348 else if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) < u16DefaultICON_Min)
2349 u16temp = u16DefaultICON;
2350 else
2351 u16temp = (MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset;
2352 }
2353 else
2354 {
2355 u16temp = u16DefaultICON;
2356 }
2357
2358 //ch0~ch13 rcon setting
2359 u16temp &= (u16temp&(MS_U16)u32Mask);
2360 printf("[%s][%d]u16temp= %x\n", __FUNCTION__, __LINE__, u16temp);
2361
2362 MOD_A_W2BYTE(REG_MOD_A_BK00_10_L, (u16temp<<8|u16temp));
2363 MOD_A_W2BYTE(REG_MOD_A_BK00_11_L, (u16temp<<8|u16temp));
2364 MOD_A_W2BYTE(REG_MOD_A_BK00_12_L, (u16temp<<8|u16temp));
2365 MOD_A_W2BYTE(REG_MOD_A_BK00_13_L, (u16temp<<8|u16temp));
2366 MOD_A_W2BYTE(REG_MOD_A_BK00_14_L, (u16temp<<8|u16temp));
2367 MOD_A_W2BYTE(REG_MOD_A_BK00_15_L, (u16temp<<8|u16temp));
2368 MOD_A_W2BYTE(REG_MOD_A_BK00_16_L, (u16temp<<8|u16temp));
2369 MOD_A_W2BYTE(REG_MOD_A_BK00_17_L, (u16temp<<8|u16temp));
2370 }
2371 }
2372
MHal_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)2373 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
2374 {
2375 MS_U16 u16ValidSwing2 = 0;
2376 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2377 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2378 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2379 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2380 if( eLPLL_Type == E_PNL_TYPE_TTL)
2381 {
2382 // select pair output to be TTL
2383 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2384 MsOS_DelayTask(1);
2385 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2386 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2387 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2388
2389 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair
2390
2391 // other TTL setting
2392 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x0000); // TTL output enable
2393
2394 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0x0000);
2395 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2396 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000);
2397
2398 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew
2399
2400 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007);//[2:0]reg_mft_mode
2401
2402 MOD_A_W2BYTE(REG_MOD_A_BK00_38_L, 0x0000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2403
2404 // GPO gating
2405 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating
2406 }
2407 else if(( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)||
2408 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
2409 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE))
2410 {
2411 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2
2412
2413 // rcon
2414 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE)
2415 {
2416 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
2417 MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel);
2418 }
2419 else
2420 {
2421 HAL_MOD_CAL_DBG(printf("Use RconValue\n", __FUNCTION__, __LINE__));
2422 msSetVBY1RconValue(pInstance);
2423 }
2424
2425 // rint
2426 MOD_A_W2BYTE(REG_MOD_A_BK00_32_L, 0x0000);
2427
2428 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003f);
2429
2430 //-------------------------------------
2431 //## pe
2432 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
2433 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
2434 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
2435 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
2436
2437 // VBY1 setting
2438 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0xFFFF);
2439
2440 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8F3F); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
2441 // MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2442
2443 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0xFFFF);
2444 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2445 MOD_A_W2BYTE(REG_MOD_A_BK00_48_L, 0xFFFF);
2446 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2447 MOD_A_W2BYTE(REG_MOD_A_BK00_42_L, 0xFFFF);
2448 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0xFFFF);
2449
2450 switch(eOutputMode)
2451 {
2452 case E_PNL_OUTPUT_NO_OUTPUT:
2453 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2454 MsOS_DelayTask(1);
2455 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2456 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2457 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2458 if(1)//( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2459 {
2460 //-------------------------------------
2461 //## icon (Swing)
2462 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
2463 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
2464
2465 //-------------------------------------
2466 //vby1
2467 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
2468 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2469 }
2470 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2471 {
2472 //-------------------------------------
2473 //## icon (Swing)
2474 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
2475 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
2476
2477 //vby1
2478 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f);
2479 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF);
2480 }
2481 break;
2482
2483 case E_PNL_OUTPUT_CLK_ONLY:
2484 case E_PNL_OUTPUT_DATA_ONLY:
2485 case E_PNL_OUTPUT_CLK_DATA:
2486 default:
2487 if(eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
2488 {
2489 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC100);
2490 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2491 {
2492 _MHal_PNL_Auto_Set_Config(pInstance,
2493 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2494 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2495 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2496 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2497 }
2498 else
2499 {
2500 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x5555); //[15:0]reg_output_conf[15:0]
2501 }
2502 }
2503 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2504 {
2505 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2506 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0002); //[1]reg_dualmode[0]abswitch
2507 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2508 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x7f7f);
2509
2510 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2511 {
2512 _MHal_PNL_Auto_Set_Config(pInstance,
2513 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2514 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2515 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2516 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2517 }
2518 else
2519 {
2520 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0055); //[15:0]reg_output_conf[15:0]
2521 }
2522 }
2523 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2524 {
2525 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2526 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0000);
2527 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2528 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x0000);
2529
2530 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2531 {
2532 _MHal_PNL_Auto_Set_Config(pInstance,
2533 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2534 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2535 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2536 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2537 }
2538 else
2539 {
2540 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0005);
2541 }
2542 }
2543 break;
2544 }
2545 }
2546 //// for osd dedicated output port, 1 port for video and 1 port for osd
2547 else if((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&
2548 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
2549 {
2550 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2551 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path
2552 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
2553 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2554 }
2555 else
2556 {
2557 switch(eOutputMode)
2558 {
2559 case E_PNL_OUTPUT_NO_OUTPUT:
2560 // if MOD_45[5:0] = 0x3F && XC_MOD_EXT_DATA_EN_L = 0x0,
2561 // then if XC_MOD_OUTPUT_CONF_L = 0x0 ---> output TTL as tri-state
2562 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2563 MsOS_DelayTask(1);
2564 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2565 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2566 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2567
2568 //----------------------------------
2569 // Purpose: Set the output to be the GPO, and let it's level to Low
2570 // 1. External Enable, Pair 0~5
2571 // 2. GPIO Enable, pair 0~5
2572 // 3. GPIO Output data : All low, pair 0~5
2573 // 4. GPIO OEZ: output piar 0~5
2574 //----------------------------------
2575
2576 //1.External Enable, Pair 0~5
2577 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF);
2578 //2.GPIO Enable, pair 0~5
2579 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF);
2580 //3.GPIO Output data : All low, pair 0~5
2581 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF);
2582 //4.GPIO OEZ: output piar 0~5
2583 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF);
2584
2585 //1.External Enable, Pair 6~15
2586 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000);
2587 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2588 //2.GPIO Enable, pair 6~15
2589 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000);
2590 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2591 //3.GPIO Output data : All low, pair 6~15
2592 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000);
2593 MOD_A_W2BYTE(REG_MOD_A_BK00_45_L, 0x0000);
2594 //4.GPIO OEZ: output piar 6~15
2595 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000);
2596 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0x0000);
2597
2598 //1234.External Enable, Pair 16~17
2599 MOD_W2BYTE(REG_MOD_BK00_7E_L, 0xFF00);
2600
2601 //1.External Enable, Pair 18~20, 2.GPIO Enable, pair 18~20
2602 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F);
2603 //3.GPIO Output data : All low, pair 18~20
2604 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00);
2605 //4.GPIO OEZ: output piar 18~20
2606 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00);
2607 break;
2608
2609 case E_PNL_OUTPUT_CLK_ONLY:
2610 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000);
2611 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x4004);
2612 break;
2613
2614 case E_PNL_OUTPUT_DATA_ONLY:
2615 case E_PNL_OUTPUT_CLK_DATA:
2616 default:
2617 // LVDS default setting
2618 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x5550);
2619 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
2620
2621 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000);
2622 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0x0000);
2623 //1. set GCR_PVDD_2P5=1¡¦b1; MOD PVDD power: 1: 2.5V
2624 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0, BIT(6));
2625 //2. set PD_IB_MOD=1¡¦b0;
2626 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(0));
2627 // save ch6 init value
2628 u16ValidSwing2 = (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0B_L, 0x3F00)>>8);
2629 //3. set Desired Pairs: GCR_ICON[5:0]=6h3f (current all open);
2630 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, 0x3F));
2631 //4. set Desired Pairs: GCR_PE_ADJ[2:0]=3h7 (pre-emphasis current all open )
2632 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x07);
2633 //5. Enable low-power modeinternal termination Open, Enable OP
2634 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 1);
2635
2636 MsOS_DelayTask(1);
2637
2638 //6. Enable low-power modeinternal termination Open, Enable OP
2639 MHal_Output_LVDS_Pair_Setting(pInstance,
2640 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
2641 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
2642 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
2643 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2644 MHal_Shift_LVDS_Pair(pInstance, pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift);
2645
2646 //7. set Desired Pairs: GCR_PE_ADJ[2:0]=3¡¦h0 (pre-emphasis current all Close)
2647 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x00);
2648 //8. set Desired Pairs: GCR_ICON[5:0] (current all init);
2649 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, u16ValidSwing2));
2650 //9. Disable low-power modeinternal termination Close, Disable OP
2651 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 0);
2652
2653 // other TTL setting
2654 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/ PANEL_miniLVDS/ PANEL_RSDS
2655
2656 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000);
2657 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2658 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F);
2659
2660 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew
2661
2662 // GPO gating
2663 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating
2664
2665 break;
2666 }
2667 }
2668
2669 // MHal_PNL_Bringup(pInstance);
2670 }
2671
Mhal_PNL_Flock_LPLLSet(void * pInstance,MS_U64 ldHz)2672 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz)
2673 {
2674 UNUSED(ldHz);
2675 }
2676
MHal_PNL_MISC_Control(void * pInstance,MS_U32 u32PNL_MISC)2677 void MHal_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC)
2678 {
2679 if(u32PNL_MISC & E_DRVPNL_MISC_MFC_ENABLE)
2680 {
2681 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair
2682 }
2683 }
2684
MHal_PNL_Init_XC_Clk(void * pInstance,PNL_InitData * pstPanelInitData)2685 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData)
2686 {
2687 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2688 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2689 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2690 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2691
2692 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2693
2694 // setup output dot clock
2695 if (pstPanelInitData->eLPLL_Type == E_PNL_TYPE_TTL)
2696 {
2697 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2698 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2699 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2700 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL clock div, TTL:DIV2
2701
2702 W2BYTEMSK(REG_RVD_44_L, 0x0004, 0x001F); //[4:0]reg_ckg_clk_misc
2703 W2BYTEMSK(L_CLKGEN0(0x58), 0x0001, 0x000F); //[3:0]ckg_tx_mod
2704 }
2705 else if ((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_LVDS) && ((pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE)))
2706 {
2707 // 1366x768, 1CH LVDS case
2708 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2709 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2710 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2711 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL clock div, TTL:DIV2
2712
2713 W2BYTEMSK(REG_RVD_44_L, 0x0004, 0x001F); //[4:0]reg_ckg_clk_misc
2714 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod
2715 }
2716 if ((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_DAC_P) || (pstPanelInitData->eLPLL_Type == E_PNL_TYPE_DAC_I))
2717 {
2718 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2719 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2720 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2721 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // [4..3] LPLL clock div, TTL:DIV2
2722
2723 // For mantis 1208252: HDMI Tx frame lock issue, HW RD said 0x100A_44 should be 0x1C for HDMI Tx case
2724 W2BYTEMSK(REG_RVD_44_L, 0x001C, 0x001F); //[4:0]reg_ckg_clk_misc
2725 }
2726 else
2727 {
2728 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2729 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2730 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2731 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div
2732
2733 W2BYTEMSK(REG_RVD_44_L, 0x000C, 0x001F); //[4:0]reg_ckg_clk_misc
2734 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod
2735 }
2736
2737 // reg_ckg_odclk_mft
2738 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_MFT_GATED); // [8] disable clock
2739 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_MFT_INVERT); // [9] invert clock
2740 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_MFT_SEL_LPLL, CKG_ODCLK_MFT_SEL_SOURCE); // [10] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out // 0:synthetic clock out, 1:LPLL clock out
2741 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_MFT_XTAL, CKG_ODCLK_MFT_MASK); // [12:11] LPLL clock div
2742
2743 W2BYTE(L_CLKGEN1(0x31), 0x0000); //[11:8]ckg_odclk_frc
2744
2745 if( IsVBY1(pstPanelInitData->eLPLL_Type) )
2746 {
2747 W2BYTEMSK(REG_CLKGEN0_57_L, 0x000C, 0x000F); //[3:0]ckg_fifo
2748 W2BYTE(REG_RVD_09_L, 0x0800); //[13:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2749 //W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc
2750 W2BYTEMSK(L_CLKGEN0(0x56),0x0010, 0x00F0); //[7:4]reg_ckg_odclk_a
2751 W2BYTE(L_CLKGEN0(0x63),0x1001); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod
2752
2753 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
2754 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
2755 {
2756 W2BYTE(L_CLKGEN0(0x5A),0x0800); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
2757 }
2758 else if ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
2759 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
2760 {
2761 W2BYTE(L_CLKGEN0(0x5A),0x0900); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
2762 }
2763 else
2764 {
2765 W2BYTE(L_CLKGEN0(0x5A),0x0A00); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
2766 }
2767
2768 }
2769 else
2770 {
2771
2772 if (pstPanelInitData->eLPLL_Type == E_PNL_TYPE_TTL)
2773 {
2774 W2BYTEMSK(REG_CLKGEN0_57_L, 0x0001, 0x000F); //[3:0]ckg_fifo
2775 W2BYTEMSK(L_CLKGEN0(0x56),0x0040, 0x00F0); //[7:4]reg_ckg_odclk_a
2776 W2BYTE(L_CLKGEN0(0x63),0x1100); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod
2777 }
2778 else if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2779 {
2780 W2BYTE(L_CLKGEN0(0x63),0x1000); //[7:4]reg_ckg_odclk_a
2781 W2BYTEMSK(REG_CLKGEN0_57_L, 0x000C, 0x000F); //[3:0]ckg_fifo
2782 W2BYTEMSK(L_CLKGEN0(0x56),0x0000, 0x000F); //[7:4]reg_ckg_odclk_a
2783 }
2784 else
2785 {
2786 W2BYTEMSK(REG_CLKGEN0_57_L, 0x0000, 0x000F); //[3:0]ckg_fifo
2787 W2BYTE(L_CLKGEN0(0x63),0x1000); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod
2788 }
2789
2790 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
2791 {
2792 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+
2793 }
2794 else if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2795 {
2796 W2BYTE(REG_RVD_09_L, 0x0800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2797 }
2798 else
2799 {
2800 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2801 }
2802 }
2803
2804 if( (E_PNL_TYPE_TTL == pstPanelInitData->eLPLL_Type)||
2805 ((E_PNL_TYPE_LVDS == pstPanelInitData->eLPLL_Type)&&(E_PNL_MODE_SINGLE==pstPanelInitData->eLPLL_Mode))||
2806 ((E_PNL_TYPE_HS_LVDS == pstPanelInitData->eLPLL_Type)&&(E_PNL_MODE_SINGLE==pstPanelInitData->eLPLL_Mode)))
2807 {
2808 //set LPLL mux
2809 W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0_reserved0[7:2]
2810 //[0] : diable clock
2811 //[1] : invert clock
2812 //[4:2] : xx0 : floclk_odclk_synth_out
2813 // 011 / 111: LPLL output clock
2814 }
2815 else if ((E_PNL_TYPE_DAC_P == pstPanelInitData->eLPLL_Type) ||
2816 (E_PNL_TYPE_DAC_I == pstPanelInitData->eLPLL_Type))
2817 {
2818 //set LPLL mux
2819 W2BYTEMSK(L_CLKGEN0(0x7E), 0x00A0, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0_reserved0[7:2]
2820 //[0] : diable clock
2821 //[1] : invert clock
2822 //[4:2] : xx0 : floclk_odclk_synth_out
2823 // 011 / 111: LPLL output clock
2824 }
2825 else
2826 {
2827 //set LPLL mux
2828 W2BYTEMSK(L_CLKGEN0(0x7E), 0x0030, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0_reserved0[7:2]
2829 //[0] : diable clock
2830 //[1] : invert clock
2831 //[4:2] : xx0 : floclk_odclk_synth_out
2832 // 011 / 111: LPLL output clock
2833 }
2834
2835 if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2836 {
2837 W2BYTEMSK(REG_CHIP_50_L, 0x000F, 0x000F);
2838 }
2839 }
2840
2841 #define OUTPUT_CHANNEL_PART_A 0x0055 // CH0~3
2842 #define OUTPUT_CHANNEL_PART_B 0x5500 // CH4~7
2843 #define OUTPUT_CHANNEL_PART_C 0x0015 // CH8~10
2844 #define OUTPUT_CHANNEL_PART_D 0x0540 // CH11~13
2845 #define OUTPUT_CHANNEL_ALL 0x5555
2846
MHal_PNL_Init_MOD(void * pInstance,PNL_InitData * pstPanelInitData)2847 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData)
2848 {
2849 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2850 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2851 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2852 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2853
2854 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2855
2856 //------------------------------------------------------------------------
2857
2858 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL0 = %x\n", pstPanelInitData->u16MOD_CTRL0);
2859 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL9 = %x\n", pstPanelInitData->u16MOD_CTRL9);
2860 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRLA = %x\n", pstPanelInitData->u16MOD_CTRLA);
2861 PNL_DBG(PNL_DBGLEVEL_INIT, "u8MOD_CTRLB = %x\n", pstPanelInitData->u8MOD_CTRLB);
2862
2863 //-------------------------------------------------------------------------
2864 // Set MOD registers
2865 //-------------------------------------------------------------------------
2866
2867 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK);
2868
2869 // GPIO is controlled in drvPadConf.c
2870 // MDrv_Write2Byte(L_BK_MOD(0x46), 0x0000); //EXT GPO disable
2871 // MDrv_Write2Byte(L_BK_MOD(0x47), 0x0000); //EXT GPO disable
2872 if(IsVBY1(pstPanelInitData->eLPLL_Type_Ext))
2873 {
2874 ///u16MOD_CTRL9 [6] : 62[9]reg_vby1_pair_swap
2875 ///u16MOD_CTRL9 [12:11] : 62[5:4]reg_vby1_pair_mirror
2876 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xAC40, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2877
2878 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9));
2879 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|BIT(4));
2880
2881 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2882 {
2883 if(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
2884 {
2885 // 2 divison just be supported in monet vby1 8 lane
2886 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2887 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode
2888
2889 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value
2890 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize
2891 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len
2892 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage
2893 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask
2894 }
2895 else
2896 {
2897 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode
2898 }
2899 }
2900 else
2901 {
2902 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2903 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x0000, 0xFFFF); //[11:0]reg_dly_value
2904 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007); //[2:0]reg_mft_mode
2905 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFFFF); //[2:0]reg_sram_usage
2906 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask
2907 }
2908
2909 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(14), BIT(14)); //[14]:reg_lockn_to_acq
2910 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0003, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv
2911
2912 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
2913 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1
2914 else
2915 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1
2916
2917
2918 ///u16MOD_CTRL9 [7] : 63[13]reg_vby1_pair_swap_osd
2919 ///u16MOD_CTRL9 [14:13] : 63[11:10]reg_vby1_pair_mirror2
2920 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13));
2921 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|BIT(10));
2922
2923 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
2924 {
2925 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1
2926
2927 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
2928 {
2929 // 2 Divisoin
2930 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2
2931 }
2932 else
2933 {
2934 // 1 Division
2935 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2
2936 }
2937 }
2938 else //if ///E_PNL_LPLL_VBY1_10BIT_4LANE, E_PNL_LPLL_VBY1_10BIT_2LANE
2939 {
2940 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(12)); // [12] enable 8ch vx1 mode : 0
2941 }
2942
2943 MHal_Output_Channel_Order(pInstance,
2944 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2945 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2946 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2947 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2948 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2949
2950
2951 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2952 {
2953 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2954 }
2955 else
2956 {
2957 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2958 }
2959
2960 ////per RD's suggestion ---Start
2961 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, 0xFFFF, 0xFFFF); //reg_gcr_pe_en_ch
2962 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //reg_gcr_en_rint_ch
2963 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //reg_gcr_test_ch
2964
2965 ////per RD's suggestion, for VBY1 channel skew
2966 MOD_A_W2BYTE(REG_MOD_A_BK00_02_L, 0x4444); //Fine tune skew for channel 0~7
2967 MOD_A_W2BYTE(REG_MOD_A_BK00_03_L, 0x4444); //Fine tune skew for channel 8~15
2968
2969 /// reg_gcr_pe_adj ch0~ch15
2970 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x0202);
2971 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x0202);
2972 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x0202);
2973 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x0202);
2974 MOD_A_W2BYTE(REG_MOD_A_BK00_1C_L,0x0202);
2975 MOD_A_W2BYTE(REG_MOD_A_BK00_1D_L,0x0202);
2976 MOD_A_W2BYTE(REG_MOD_A_BK00_1E_L,0x0202);
2977 MOD_A_W2BYTE(REG_MOD_A_BK00_1F_L,0x0202);
2978
2979 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x80E8, 0xFFFF); //[0]:reg_vby1_8v4o_mode
2980
2981 //The threshold value be set too strict ( ori: MOD_5C =0x0 )
2982 //And this reg should be set before enable serializer function
2983 //[15]reg_sw_rptr_fix_en: pointer fix by sw mode enable
2984 //[14:12]reg_sw_wptr_check: sw mode to decision write point check point
2985 //[10:8]reg_sw_rptr_fix_ini: sw mode to decision read point initial value
2986 //[6:4]reg_sw_rptr_fix_hi_th: sw mode to decision read pointer hi boundary
2987 //[2:0]reg_sw_rptr_fix_lo_th: sw mode to decision read pointer low boundary
2988 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF);
2989 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF);
2990
2991 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
2992 //[1]enable serializer auto fix read/write point mis-balance
2993 //[2]enable osd serializer auto fix read/write point mis-balance
2994 //[7]for OSD, switch chanel 8~13 as OSD path
2995 }
2996 else
2997 {
2998 // non-VBY1 case
2999 MOD_W2BYTE(REG_MOD_BK00_49_L, pstPanelInitData->u16MOD_CTRL9); //{L_BK_MOD(0x49), 0x00}, // [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit, bit shift
3000 MHal_Output_Channel_Order(pInstance,
3001 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
3002 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
3003 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
3004 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
3005 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
3006 }
3007
3008 MOD_W2BYTE(REG_MOD_BK00_4A_L, pstPanelInitData->u16MOD_CTRLA);
3009 MOD_W2BYTE(REG_MOD_BK00_4B_L, pstPanelInitData->u8MOD_CTRLB); //[1:0]ti_bitmode 10:8bit 11:6bit 0x:10bit
3010
3011 #if 0 // no need this for Maxim 23x23 8V case
3012 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, (_u8PnlDiffSwingLevel << 1), 0xFE); //differential output swing level
3013 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
3014 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
3015 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000, 0xF000); //bank selection for skew clock
3016 #endif
3017
3018 //if(!MHal_PNL_MOD_Control_Out_Swing(_u8PnlDiffSwingLevel))
3019 // printf(">>Swing Level setting error!!\n");
3020 if(pstPanelInitData->eLPLL_Type != E_PNL_TYPE_MINILVDS)
3021 {
3022 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07);
3023 }
3024
3025 //// Patch for Vx1 and it should be control by panel ini
3026 if( IsVBY1(pstPanelInitData->eLPLL_Type_Ext) )
3027 {
3028 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, 0x0FFF, 0x3FFF);
3029 }
3030 else
3031 {
3032 MOD_A_W2BYTE(REG_MOD_A_BK00_31_L, pstPanelInitData->u16LVDSTxSwapValue);
3033 }
3034
3035 #if 0 // Skip power down for bring up
3036 #ifdef CONFIG_MSTAR_SRAMPD
3037 // At initial step, if non TCON panel, enable OD/RGBW/M+/Demura/DGA_Gamma SRAM PD
3038 if((pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI34_8P)&&
3039 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI28_8P)&&
3040 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI34_6P)&&
3041 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI28_6P)&&
3042 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI34_2P)&&
3043 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI34_4P)&&
3044 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI28_2P)&&
3045 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI28_4P)&&
3046 (pstPanelInitData->eLPLL_Type_Ext != E_PNL_LPLL_EPI28_12P))
3047 {
3048 if(pPNLInstancePrivate->u32DeviceID == 0)
3049 {
3050 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_10_L, BIT(0), BIT(0)); //OD SRAM PD Enable : SC_SPD_BK3F_10[0]
3051 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, 0, BIT(8)); //OD Clock gate : ~SC_SPD_BK3F_50[8]
3052 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, BIT(15), BIT(15)); //OD Bypass Enable :SC_OD_BK16_6F[15]
3053
3054 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_10_L, BIT(1), BIT(1)); // RGBW SRAM PD Enable : SC_SPD_BK3F_10[1]
3055 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, 0, BIT(9)); // RGBW Clock Gate : ~SC_SPD_BK3F_50[9]
3056 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, BIT(12), BIT(12)); // RGBW bypass enable :SC_OD_BK16_6F[12]
3057 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(13)); // RGBW bypass enable : ~SC_OD_BK16_6F[13]
3058
3059 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_17_L, BIT(0), BIT(0)); //M+ SRAM PD Enable : SC_SPD_BK3F_17[0]
3060 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_50_L, 0, BIT(10)); //M+ Clock gate : ~SC_SPD_BK3F_50[10]
3061 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L,0 , BIT(12)); // M+ bypass enable :SC_OD_BK16_6F[12]
3062 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_6F_L, 0, BIT(13)); // M+ bypass enable : ~SC_OD_BK16_6F[13]
3063
3064 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_0B_L, BIT(4), BIT(4)); //Demura SRAM PD Enable : SC_SPD_BK3F_0B[4]
3065 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK77_26_L, BIT(14), BIT(14)); //Demura Clock Gate : SC_BK77_26[14]
3066 W2BYTEMSK(REG_RVD_45_L, BIT(0), BIT(0)); //Demura Clock gate : BK100A_CLKGEN2_45[0]
3067 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK77_26_L, BIT(15), BIT(15)); //Demura Clock Gate : SC_BK77_26[15]
3068
3069 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK3F_0B_L, BIT(5), BIT(5)); //DGA_GAMMA SRAM PD Enable : SC_SPD_BK3F_0B[5]
3070 }
3071 }
3072
3073 // At initial step, SRAM PD for LD
3074 // To avoid mantis 1082875: boot logo flash issue, remove SRAM PD for LD from XC_init to PNL_init
3075 if(pPNLInstancePrivate->u32DeviceID == 0)
3076 {
3077 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BKC9_65_L, (BIT(0)), 0x0001);
3078 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BKCE_01_L, (0x0000), 0x1000);
3079 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BKCE_37_L, (BIT(15)), 0x8000);
3080 //non-FO setting
3081 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK3F_12_L, (BIT(0)| BIT(1)), 0x0003);
3082 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK3F_50_L, (0x0000), 0x3800);
3083 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK2E_37_L, (BIT(15)), 0x8000);
3084 }
3085 #endif
3086 #endif
3087
3088 // TODO: move from MDrv_Scaler_Init(), need to double check!
3089 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0));
3090
3091
3092 //--------------------------------------------------------------
3093 //Depend On Bitmode to set Dither
3094 //--------------------------------------------------------------
3095
3096
3097 // always enable noise dither and disable TAILCUT
3098 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, ((pstPanelInitData->u8PanelNoiseDith ? XC_PAFRC_DITH_NOISEDITH_EN : (1 - XC_PAFRC_DITH_NOISEDITH_EN)) <<3) , BIT(3));
3099 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, XC_PAFRC_DITH_TAILCUT_DISABLE, BIT(4));
3100
3101 switch(pstPanelInitData->u8MOD_CTRLB & 0x03)//[1:0]ti_bitmode b'10:8bit 11:6bit 0x:10bit
3102 {
3103 case HAL_TI_6BIT_MODE:
3104 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
3105 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(2), BIT(2));
3106 break;
3107
3108 case HAL_TI_8BIT_MODE:
3109 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
3110 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
3111 break;
3112
3113 case HAL_TI_10BIT_MODE:
3114 default:
3115 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(0));
3116 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
3117 break;
3118 }
3119
3120
3121 //-----depend on bitmode to set Dither------------------------------
3122 MHal_PNL_SetOutputType(pInstance, pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type); // TTL to Ursa
3123
3124 //dual port lvds _start_//
3125 // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
3126 if (IsVBY1(pstPanelInitData->eLPLL_Type_Ext))
3127 {
3128 MS_U16 u16ChannelClk_En = BIT(0); // bit0 is en_clk
3129 MS_U16 u16OutputCFG0_7 = OUTPUT_CHANNEL_ALL, u16OutputCFG8_15 = OUTPUT_CHANNEL_ALL;
3130 if(pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type == LVDS_OUTPUT_User)
3131 {
3132 u16OutputCFG0_7 = pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7;
3133 u16OutputCFG8_15 = pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15;
3134 }
3135
3136 if(u16OutputCFG0_7 & OUTPUT_CHANNEL_PART_A)
3137 u16ChannelClk_En |= BIT(1); //bit1: partA - ch0~3
3138 if(u16OutputCFG0_7 & OUTPUT_CHANNEL_PART_B)
3139 u16ChannelClk_En |= BIT(2); //bit2: partB - ch4~7
3140 if(u16OutputCFG8_15 & OUTPUT_CHANNEL_PART_C)
3141 u16ChannelClk_En |= BIT(3); //bit3: partC - ch8~10
3142 if(u16OutputCFG8_15 & OUTPUT_CHANNEL_PART_D)
3143 u16ChannelClk_En |= BIT(4); //bit4: partD - ch11~13
3144
3145 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u16ChannelClk_En, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck // original is MDrv_WriteByteMask(L_BK_MOD(0x77), 0x0F, BITMASK(7:2));
3146 }
3147 else
3148 {
3149 // LVDS
3150 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck // original is MDrv_WriteByteMask(L_BK_MOD(0x77), 0x0F, BITMASK(7:2));
3151 }
3152 //dual port lvds _end_//
3153 //MHal_PNL_Bringup(pInstance);
3154
3155 MHal_PNL_MISC_Control(pInstance, pstPanelInitData->u32PNL_MISC);
3156
3157 PNL_DBG(PNL_DBGLEVEL_INIT, "OutputType = %x, eLPLL_Type = %x\n", pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type);
3158 PNL_DBG(PNL_DBGLEVEL_INIT, "u32PNL_MISC = %tx\n", (ptrdiff_t)pstPanelInitData->u32PNL_MISC);
3159
3160 }
3161
MHal_PNL_DumpMODReg(void * pInstance,MS_U32 u32Addr,MS_U16 u16Value,MS_BOOL bHiByte,MS_U16 u16Mask)3162 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask)
3163 {
3164 if (bHiByte)
3165 {
3166 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
3167 }
3168 else
3169 {
3170 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask);
3171 }
3172 }
3173
MHal_MOD_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)3174 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
3175 {
3176 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3177 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3178 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3179 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3180 // Setup the default swing level
3181 pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel = pstModCaliInitData->u16ExpectSwingLevel; //mv
3182 #if 0
3183 // Pair setting
3184 // =========
3185 // Select calibration source pair, 00: ch2, 01: ch6, 10:ch8, 11:ch12
3186 //MOD_7D_L[3:2]
3187 // =========
3188 //in msModCurrentCalibration, it will transfer to the real data
3189
3190 switch(pstModCaliInitData->u8ModCaliPairSel)
3191 {
3192 default:
3193 case 0:
3194 //ch 2
3195 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x00; // ch2
3196 break;
3197 case 1:
3198 //ch 6
3199 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x01; // ch6, calibration initialized value
3200 break;
3201 case 2:
3202 //ch 8
3203 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x02;
3204 break;
3205 case 3:
3206 //ch 12
3207 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x03;
3208 break;
3209 }
3210 #endif
3211 // Target setting
3212 // =========
3213 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
3214 // =========
3215 //in msModCurrentCalibration, it will transfer to the real data
3216 switch(pstModCaliInitData->u8ModCaliTarget)
3217 {
3218 default:
3219 case 0:
3220 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 0;
3221 break;
3222 case 1:
3223 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 1;
3224 break;
3225 case 2:
3226 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 2;
3227 break;
3228 case 3:
3229 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 3;
3230 break;
3231 }
3232 // Offset setting, for fine tune
3233 //_usMOD_CALI_OFFSET = pstModCaliInitData->s8ModCaliOffset;
3234 // _u8MOD_CALI_VALUE is a real value; the _u8MOD_CALI_VALUE is an idea value
3235 // Target value should be the same with _u8MOD_CALI_VALUE to be a default value
3236 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE= pstModCaliInitData->u8ModCaliTarget;
3237 // PVDD setting
3238 pPNLResourcePrivate->sthalPNL._bPVDD_2V5 = pstModCaliInitData->bPVDD_2V5;
3239
3240 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
3241 PNL_DBG(PNL_DBGLEVEL_INIT, "u16ExpectSwingLevel = %u\n", pstModCaliInitData->u16ExpectSwingLevel);
3242 PNL_DBG(PNL_DBGLEVEL_INIT, "u8ModCaliTarget = %x\n", pstModCaliInitData->u8ModCaliTarget);
3243 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_TARGET = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET);
3244 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_VALUE = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE);
3245 PNL_DBG(PNL_DBGLEVEL_INIT, "bPVDD_2V5 = %x\n", pstModCaliInitData->bPVDD_2V5);
3246
3247 }
3248
MHal_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)3249 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type)
3250 {
3251 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3252 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3253 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3254 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3255 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
3256 {
3257 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift = LVDS_DUAL_OUTPUT_SPECIAL;
3258 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = 1;
3259 }
3260 else
3261 {
3262 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = Type;
3263 }
3264 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
3265 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_LVDS_Pair_Type = %u\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
3266
3267 }
3268
msModCalDDAOUT(void)3269 MS_BOOL msModCalDDAOUT(void)
3270 {
3271 // W2BYTEMSK(BK_MOD(0x7D), ENABLE, 8:8);
3272 // MsOS_DelayTask(10); //10ms
3273 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_A_BK00_74_L, BIT(8))) >> 8);
3274 }
3275
msModCurrentCalibration(void * pInstance)3276 MS_U8 msModCurrentCalibration(void *pInstance)
3277 {
3278 #if MOD_CAL_TIMER
3279 MS_U32 delay_start_time;
3280 delay_start_time=MsOS_GetSystemTime();
3281 #endif
3282
3283 #if (!ENABLE_Auto_ModCurrentCalibration)
3284 return 0x60;
3285 #else
3286 MS_U8 u8cur_ibcal=0;
3287 MS_U16 u16reg_32da = 0, u16reg_32dc = 0;
3288 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3289 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3290 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3291 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3292 u16reg_32da = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3293 u16reg_32dc = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3294
3295 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s][%d]\n", __FUNCTION__, __LINE__);
3296
3297 // (1) Set keep mode to auto write calibration result into register.
3298 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15));
3299
3300 // (2) Set calibration step waiting time
3301 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0x0080); // (about 5us)
3302 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, 0x00FF);
3303
3304 // (3) Set calibration toggle time
3305 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00);
3306
3307 // (4) Select calibration level (LVDS is 250mV)
3308 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(1)|BIT(0)); // Select calibration target voltage, 00: 250mV, 01:350mV, 10: 300mV, 11: 200mV
3309
3310 // (5) Enable Calibration mode
3311 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function
3312
3313 // (6) Store output configuration value and Enable each pair test mode
3314 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0xFFFF);
3315 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0FFF);
3316
3317 MS_U8 u8CheckTimes = 0;
3318 while(1)
3319 {
3320 // (7) Enable Hardware calibration
3321 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, BIT(15), BIT(15));
3322
3323 // (8) Wait 2ms
3324 MsOS_DelayTask(2);
3325
3326 // (10) Disable Hardware calibration
3327 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, 0x00, BIT(15));
3328
3329 // (9)Check Finish and Fail flag bit
3330 //BK111E, 0x73[14], Finish flag=1
3331 //BK111E, 0x73[13], Fail flag=0
3332 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_73_L, 0x6000) == 0x4000)
3333 {
3334 //printf("\033[0;31m [%s][%d] cal ok, break \033[0m\n", __FUNCTION__, __LINE__);
3335 break;
3336 }
3337 else
3338 {
3339 u8CheckTimes ++;
3340 //printf("\033[0;31m [%s][%d] cal ng, u8CheckTimes: %d \033[0m\n", __FUNCTION__, __LINE__, u8CheckTimes);
3341 }
3342
3343 if (u8CheckTimes > 3)
3344 {
3345 // (13) If 3 times all fail, set all pair to nominal value by disable keep mode
3346 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15));
3347 //printf("\033[0;31m [%s][%d] If 3 times all fail, set all pair to nominal value by disable keep mode \033[0m\n", __FUNCTION__, __LINE__);
3348 break;
3349 }
3350 }
3351
3352 if (u8CheckTimes <=3)
3353 {
3354 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration ok \n");
3355 }
3356 else
3357 {
3358 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration fail: 0x%x \n", MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000));
3359 }
3360
3361 // Wait 2ms to make sure HW auto write calibration result into register
3362 MsOS_DelayTask(2);
3363
3364 // (14) Restore each pair output configuration
3365 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16reg_32da);
3366 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16reg_32dc);
3367
3368 // (15) Disable calibration mode
3369 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Disable calibration function
3370
3371 // With HW calibration mode, HW would cal for each channel, and each channel would get different value
3372 // Return channel 2 vaule
3373 u8cur_ibcal = MOD_A_R2BYTEMSK(REG_MOD_A_BK00_09_L, 0x007F); // return ch2 calibration result
3374
3375 #if MOD_CAL_TIMER
3376 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s] takes %ld ms\n", __FUNCTION__, (MsOS_GetSystemTime()-delay_start_time));
3377 #endif
3378 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n Calibration result= %x\n", u8cur_ibcal);
3379
3380 return (u8cur_ibcal&0x7F);//MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0D_L, 0x003F);
3381 #endif
3382 }
3383
MHal_PNL_MOD_Calibration(void * pInstance)3384 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance)
3385 {
3386 MS_U8 u8Cab;
3387 MS_U8 u8BackUSBPwrStatus;
3388 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3389 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3390 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3391 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3392
3393 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
3394
3395 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
3396
3397 u8Cab = msModCurrentCalibration(pInstance);
3398
3399 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
3400
3401 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type !=E_PNL_TYPE_MINILVDS)
3402 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07);
3403
3404 return E_PNL_OK;
3405
3406 }
3407
MHal_PNL_PowerDownLPLL(void * pInstance,MS_BOOL bEnable)3408 static void MHal_PNL_PowerDownLPLL(void *pInstance, MS_BOOL bEnable)
3409 {
3410 if(bEnable)
3411 {
3412 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5));
3413 }
3414 else
3415 {
3416 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5));
3417 }
3418 }
3419
MHal_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)3420 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn)
3421 {
3422 MS_U8 u8Cab;
3423 MS_U8 u8BackUSBPwrStatus;
3424 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3425 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3426 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3427 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3428
3429 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "[%s][%d]\n", __FUNCTION__, __LINE__);
3430
3431 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u32PNL_MISC = %tx\n", (ptrdiff_t)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC);
3432 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "bPanelOn = %x\n", bPanelOn);
3433 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "eLPLL_Type = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type);
3434 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "_u8MOD_LVDS_Pair_Type = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
3435 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
3436 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
3437 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3438
3439 MS_U16 u16PortA = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3440 MS_U16 u16PortB = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3441
3442 if((u16PortA!=0)||(u16PortB!=0))
3443 {
3444 MHal_BD_LVDS_Output_Type(pInstance, LVDS_OUTPUT_User);
3445 }
3446
3447 if(u16PortA!=0)
3448 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3449 if(u16PortB!=0)
3450 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3451
3452 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "==========================\n\n");
3453 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
3454 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
3455 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3456
3457
3458 if(bPanelOn)
3459 {
3460 // The order is PanelVCC -> delay pnlGetOnTiming1() -> VOP -> MOD
3461 // VOP
3462 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x4000, HBMASK);
3463
3464 // For Napoli compatible
3465 // need to wait 1ms to wait LDO stable before MOD power on
3466 MsOS_DelayTask(1);
3467
3468 // turn on LPLL
3469 MHal_PNL_PowerDownLPLL(pInstance, FALSE);
3470
3471 // for LG panel black video
3472 if(pPNLResourcePrivate->stapiPNL.ePrevPowerState != E_POWER_RESUME)
3473 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, DISABLE);
3474
3475 // mod power on
3476 MHal_MOD_PowerOn(pInstance
3477 , ENABLE
3478 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
3479 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
3480 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
3481 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
3482 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3483
3484 if(bCalEn)
3485 {
3486
3487 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
3488
3489 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
3490
3491 u8Cab = msModCurrentCalibration(pInstance);
3492
3493 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
3494
3495 }
3496 else
3497 {
3498 if( ( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) ) &&
3499 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE) == FALSE))
3500 {
3501 HAL_MOD_CAL_DBG(printf("Use RCON value \n", __FUNCTION__, __LINE__));
3502 msSetVBY1RconValue(pInstance);
3503 }
3504 else
3505 {
3506 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
3507
3508 if(!MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel))
3509 printf(">>Swing Level setting error!!\n");
3510 }
3511 }
3512
3513 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
3514 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, ENABLE);
3515 }
3516 else
3517 {
3518 // The order is LPLL -> MOD -> VOP -> delay for MOD power off -> turn off VCC
3519
3520 // LPLL
3521 // MHal_PNL_PowerDownLPLL(TRUE); //Remove to keep op vsync if panel off
3522
3523 MHal_MOD_PowerOn(pInstance
3524 , DISABLE
3525 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
3526 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
3527 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
3528 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
3529 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3530 // VOP
3531 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS ||
3532 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_I ||
3533 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_P)//(bIsLVDS)
3534 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0xFF, LBMASK);
3535 else
3536 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x00, 0xFF);
3537 }
3538
3539 return E_PNL_OK;
3540 }
3541
MHal_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)3542 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
3543 {
3544 if (bEnable)
3545 {
3546 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF);
3547 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF);
3548 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF);
3549 MsOS_DelayTask(10);
3550 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15));
3551 }
3552 else
3553 {
3554 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15));
3555 }
3556
3557 }
3558
MHal_PNL_Switch_LPLL_SubBank(void * pInstance,MS_U16 u16Bank)3559 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank)
3560 {
3561 UNUSED(u16Bank);
3562 }
3563
MHal_PNL_Switch_TCON_SubBank(void * pInstance,MS_U16 u16Bank)3564 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank)
3565 {
3566 W2BYTEMSK(L_BK_TCON(0x00), u16Bank&0xff, 0xFF);
3567 }
3568
MHal_PNL_Read_TCON_SubBank(void * pInstance)3569 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance)
3570 {
3571 return (MS_U16)R2BYTEMSK(L_BK_TCON(0x00),0xFF);
3572 }
3573
MHal_PNL_Is_VBY1_Locked(void * pInstance)3574 MS_BOOL MHal_PNL_Is_VBY1_Locked(void *pInstance)
3575 {
3576 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0300) == 0x00)
3577 {
3578 return TRUE;
3579 }
3580 else
3581 {
3582 return FALSE;
3583 }
3584 }
3585
MHal_PNL_Is_VBY1_LockN_Locked(void * pInstance)3586 MS_BOOL MHal_PNL_Is_VBY1_LockN_Locked(void *pInstance)
3587 {
3588 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0100) == 0x00)
3589 {
3590 return TRUE;
3591 }
3592 else
3593 {
3594 return FALSE;
3595 }
3596 }
3597
MHal_PNL_VBY1_Handshake(void * pInstance)3598 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance)
3599 {
3600 MS_BOOL bIsLock = FALSE;
3601
3602 if (MHal_PNL_Is_VBY1_Locked(pInstance) == FALSE)
3603 {
3604 MS_U16 u16CheckTimes = 0;
3605 //MS_U16 u16DeboundTimes = 0;
3606
3607 // need to toggle vby1 packer process start first
3608 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11));
3609 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11));
3610
3611 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value
3612 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by
3613 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition
3614 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
3615 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance
3616
3617 while(u16CheckTimes < 10)
3618 {
3619 #if 0
3620 u16DeboundTimes = 2;
3621 while ((!MHal_PNL_Is_VBY1_LockN_Locked()) && (u16DeboundTimes --))
3622 {
3623 MsOS_DelayTask(1); // can't remove
3624 }
3625 #endif
3626 if(MHal_PNL_Is_VBY1_LockN_Locked(pInstance))
3627 {
3628 //-------------------------------------------------------------------
3629 // step1. Toggle clock when training
3630 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
3631 //--------------------------------------------------------------------
3632 bIsLock = TRUE;
3633 // pass 2 times debound to make sure VBY1 is locked
3634 break;
3635 }
3636
3637 u16CheckTimes++;
3638 MsOS_DelayTaskUs(40);
3639 }
3640
3641 if(bIsLock)
3642 {
3643 // step3. Disable HW check when lock done, Enable when loss lock
3644 //MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
3645
3646 /// Add the delay to increase time to send
3647 //MDrv_TIMER_Delayms(10);
3648 }
3649 }
3650 else
3651 {
3652 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE)
3653 {
3654 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
3655 }
3656 bIsLock = TRUE;
3657 }
3658
3659 return bIsLock;
3660 }
3661
MHal_PNL_Is_VBY1_OC_Locked(void * pInstance)3662 MS_BOOL MHal_PNL_Is_VBY1_OC_Locked(void *pInstance)
3663 {
3664 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0C00) == 0x00) // MOD_BK00_56_L[11:10] for OSD
3665 {
3666 return TRUE;
3667 }
3668 else
3669 {
3670 return FALSE;
3671 }
3672 }
3673
MHal_PNL_Is_VBY1_OC_LockN_Locked(void * pInstance)3674 MS_BOOL MHal_PNL_Is_VBY1_OC_LockN_Locked(void *pInstance)
3675 {
3676 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0400) == 0x00) // MOD_BK00_56_L[11:10] for OSD
3677 {
3678 return TRUE;
3679 }
3680 else
3681 {
3682 return FALSE;
3683 }
3684 }
3685
MHal_PNL_VBY1_OC_Handshake(void * pInstance)3686 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance)
3687 {
3688 MS_BOOL bIsLock = FALSE;
3689
3690 if (MHal_PNL_Is_VBY1_OC_Locked(pInstance) == FALSE)
3691 {
3692 MS_U16 u16CheckTimes = 0;
3693 // MS_U16 u16DeboundTimes = 0;
3694
3695 // need to toggle vby1 packer process start first
3696 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11));
3697 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11));
3698
3699
3700 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value
3701 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by
3702 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition
3703 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
3704 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance
3705
3706 while(u16CheckTimes < 10)
3707 {
3708 #if 0
3709 u16DeboundTimes = 2;
3710 while ((!MHal_PNL_Is_VBY1_OC_LockN_Locked()) && (u16DeboundTimes --))
3711 {
3712 MsOS_DelayTask(1);
3713 }
3714 #endif
3715 if(MHal_PNL_Is_VBY1_OC_LockN_Locked(pInstance))
3716 {
3717 //-------------------------------------------------------------------
3718 // step1. Toggle clock when training
3719
3720 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
3721 bIsLock = TRUE;
3722 // pass 2 times debound to make sure VBY1 is locked
3723 break;
3724 }
3725
3726 u16CheckTimes++;
3727 MsOS_DelayTaskUs(40);
3728 }
3729
3730 if(bIsLock)
3731 {
3732 // step3. Disable HW check when lock done, Enable when loss lock
3733 // MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
3734 }
3735 }
3736 else
3737 {
3738 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE)
3739 {
3740 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
3741 }
3742 bIsLock = TRUE;
3743 }
3744
3745 return bIsLock;
3746 }
3747
MHal_PNL_IsYUVOutput(void * pInstance)3748 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance)
3749 {
3750 return FALSE;
3751 }
3752
MHal_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)3753 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
3754 {
3755 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3756 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3757
3758 if (bEnable == TRUE)
3759 {
3760 //interlace output vtotal modify
3761 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9), BIT(9));
3762
3763 // two different interlace information through channel A reserved bit
3764 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7));
3765 // two different interlace information through channel B reserved bit
3766 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11));
3767 }
3768 else
3769 {
3770 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L , 0, BIT(9));
3771 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7));
3772 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11));
3773 }
3774
3775 return TRUE;
3776 }
3777
MHal_PNL_GetOutputInterlaceTiming(void * pInstance)3778 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance)
3779 {
3780 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3781 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3782
3783 MS_BOOL bIsInterlaceOutput = FALSE;
3784 //interlace output vtotal modify
3785 if (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9)) == BIT(9))
3786 {
3787 if ((MOD_R2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7)) == (BIT(4) | BIT(7)))
3788 || (MOD_R2BYTEMSK(REG_MOD_BK00_42_L, BIT(10) | BIT(11)) == (BIT(10)|BIT(11))))
3789 {
3790 bIsInterlaceOutput = TRUE;
3791 }
3792 }
3793 else
3794 {
3795 bIsInterlaceOutput = FALSE;
3796 }
3797 return bIsInterlaceOutput;
3798 }
3799
3800 ////Ext LPLL setting
_MHal_PNL_Init_ExtLPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)3801 static void _MHal_PNL_Init_ExtLPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
3802 {
3803 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3804
3805 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_OSD);
3806
3807 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3808 {
3809 printf("Not Supported LPLL Type, skip LPLL Init\n");
3810 return;
3811 }
3812
3813 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_OSD);
3814 }
3815
_MHal_PNL_Get_ExtLPLL_LoopDIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3816 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopDIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3817 {
3818 MS_U16 u16loop_div = 0;
3819 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3820 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3821
3822 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3823 {
3824 u16loop_div = 0 ;
3825 }
3826 else
3827 {
3828 u16loop_div = u16EXT_LoopDiv[u8SupportedLPLLLIndex];
3829 }
3830
3831 u16loop_div *= 2;
3832 return u16loop_div;
3833 }
3834
_MHal_PNL_Get_ExtLPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3835 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3836 {
3837 MS_U16 u16loop_gain = 0;
3838 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3839 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3840
3841 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3842 {
3843 u16loop_gain = 0 ;
3844 }
3845 else
3846 {
3847 u16loop_gain = u16EXT_LoopGain[u8SupportedLPLLLIndex];
3848 }
3849 return u16loop_gain;
3850 }
3851
3852
3853 // Output Dclk
MHal_PNL_CalExtLPLLSETbyDClk(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U64 ldHz)3854 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz)
3855 {
3856
3857 MS_U64 u64LdPllSet = 0;
3858 MS_U64 u64DclkFactor = 0;
3859 MS_U32 u32Div = 0;
3860 // loop div and loop gain use default parameters to avoid dclk floating out of range and getting wrong value
3861 MS_U32 u32Factor = 10;
3862
3863 _MHal_PNL_Init_ExtLPLL(pInstance, u8LPLL_Type, u8LPLL_Mode, ldHz);
3864
3865 //the first " *2 " is from the dual mode
3866 u32Div=(MS_U32)(_MHal_PNL_Get_ExtLPLL_LoopDIV(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3867 u64DclkFactor=((MS_U64)LVDS_MPLL_CLOCK_MHZ * (MS_U64)524288 * (MS_U64)_MHal_PNL_Get_ExtLPLL_LoopGain(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3868 u64LdPllSet = (u64DclkFactor * 1000000 * u32Factor *2) + ((ldHz * u32Div) >> 1);
3869 do_div(u64LdPllSet, ldHz);
3870 do_div(u64LdPllSet, u32Div);
3871
3872 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet);
3873 //printf("MHal_PNL_CalExtLPLLSETbyDClk u32KHz = %u, u32LpllSet = %x\n", ldHz, (MS_U32)u64LdPllSet);
3874
3875 }
3876
MHal_PNL_SetOSDCOutputType(void * pInstance,PNL_TYPE eLPLL_Type,E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)3877 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)
3878 {
3879 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3880 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3881 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3882 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3883
3884 // VBy1 co-registers
3885 if( IsVBY1(eLPLL_Type) )
3886 {
3887 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1008); //[3]enable osd lvds channel
3888 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
3889
3890 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x4000, 0xF000); //bank selection for skew clock
3891
3892 //-------------------------------------
3893 //## pe
3894 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
3895 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
3896 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
3897 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
3898
3899 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
3900
3901 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(14)); //[14]:reg_lockn_to_acq
3902 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv
3903
3904 W2BYTE(REG_CLKGEN0_63_L,0x1410); //[11:8] clk_tx_mod_osd, [4:0] osd2mod
3905 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
3906
3907 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x0001, 0x0001); //[0]:reg_vby1_8v4o_mode
3908 }
3909
3910 if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
3911 {
3912 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14),BIT(14)|BIT(15)); //[15]enskew_path2[14]enclk_path2[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3913 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0055); //[7:0]reg_output_conf[27:16]
3914 W2BYTE(L_CLKGEN0(0x5A),0x8800); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
3915
3916 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1000); //[12]sw_rst, [3]enable osd lvds channel
3917 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001F, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3918 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); //[3:0] reg_ckg_tx_mod
3919 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); //reg_ckg_dot
3920
3921 MOD_W2BYTE(REG_MOD_BK00_71_L, 0xffff);
3922 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
3923 //[1]enable serializer auto fix read/write point mis-balance
3924 //[2]enable osd serializer auto fix read/write point mis-balance
3925 //[7]for OSD, switch chanel 8~13 as OSD path
3926 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000);
3927 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330);
3928 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd320);
3929 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f);
3930 //-------------------------------------
3931 //## icon (Swing)
3932 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3933 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x7f7f);
3934 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3935
3936 // vby1 osd 4 lane
3937 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa260); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap
3938
3939 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // 2 Divisoin
3940 {
3941 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x6420);
3942 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7531);
3943 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
3944 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
3945 }
3946 else
3947 {
3948 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
3949 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
3950 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
3951 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
3952 }
3953 }
3954 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
3955 {
3956 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14) ,BIT(14)|BIT(15));
3957 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0005);
3958 W2BYTE(L_CLKGEN0(0x5A),0x9900); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
3959 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001B, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3960 //-------------------------------------
3961 //## icon (Swing)
3962 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3963 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x0000);
3964 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3965
3966 //vby1 osd 2 lane
3967 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa240); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap[5]vby1_osd_4ch
3968
3969 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
3970 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
3971 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
3972 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
3973 }
3974
3975 // Control VBY1 output format and bit orders
3976 switch(eOC_OutputFormat)
3977 {
3978 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB1:
3979 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3980 break;
3981
3982 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB2:
3983 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1));
3984 break;
3985
3986 default:
3987 printf("OSDC output format uses default value\n");
3988 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3989 break;
3990 }
3991
3992
3993 }
3994
MHal_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)3995 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
3996 {
3997 MS_U16 u16Span;
3998 MS_U16 u16Step;
3999 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
4000
4001 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
4002 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
4003 // Set SPAN
4004 if(u16Fmodulation < 200 || u16Fmodulation > 400)
4005 u16Fmodulation = 300;
4006 u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) / ((MS_U32)u32PLL_SET) ) ;
4007
4008 // Set STEP
4009 if(u16Rdeviation > 300)
4010 u16Rdeviation = 300;
4011 u16Step = ((MS_U32)u32PLL_SET*u16Rdeviation) / ((MS_U32)u16Span*10000);
4012
4013 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP
4014 W2BYTE(L_BK_LPLL(0x4F), u16Span & 0x3FFF);// LPLL_SPAN
4015 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
4016
4017
4018 return TRUE;
4019 }
4020
MHal_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)4021 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
4022 {
4023 //printf("bEnable = %d\n", bEnable);
4024 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
4025 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
4026 }
4027
MHal_PNL_Set_T3D_Setting(void * pInstance)4028 void MHal_PNL_Set_T3D_Setting(void *pInstance)
4029 {
4030 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
4031 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
4032 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
4033 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
4034
4035 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_55_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x1FFF);//pixel width
4036 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_66_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
4037 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_51_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x1FFF);//reg_ln_width
4038 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_52_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
4039 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_61_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x3FFF);//reg_ln_width
4040 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_62_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
4041
4042 //per designer, should always enable t3d, since it will affect osd/video's pipeline
4043 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_61_L, BIT(0), BIT(0));//Enable Depth Render, for osd pipe line adjustment
4044 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_08_L, BIT(4), BIT(4));//mtv bypass mode
4045 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_57_L,(BIT(0)|BIT(1)),(BIT(0)|BIT(1)));//T3D fix subde enable, fix for T3D/PIP conflict issue (bit 0) Bug Fix miu eco (bit 1)
4046
4047 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
4048 }
4049
MHal_PNL_Set_Device_Bank_Offset(void * pInstance)4050 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance)
4051 {
4052 UNUSED(pInstance);
4053 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM);
4054 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg bank offset
4055 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg bank offset
4056 }
4057
MHal_PNL_Init(void * pInstance)4058 void MHal_PNL_Init(void *pInstance)
4059 {
4060 // Do nothing
4061 //UNUSED(pInstance);
4062 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
4063 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
4064
4065 // STGEN reset
4066 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK68_50_L, (BIT(0)|BIT(3)), (BIT(0)|BIT(3)) );
4067
4068 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK68_52_L, FRC_PIPE_DELAY_HCNT_FSC_FHD, 0x3FFF);
4069 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK68_51_L, FRC_PIPE_DELAY_VCNT_FSC_FHD, 0x1FFF);
4070
4071 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK68_20_L, BIT(5), BIT(5)); // reg_stgen_en: use simple tgen to trigger op/vip
4072 }
4073
MHal_PNL_Bringup(void * pInstance)4074 void MHal_PNL_Bringup(void *pInstance)
4075 {
4076 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
4077 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
4078 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
4079 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
4080
4081 ///patch for bring up
4082 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
4083 {
4084 }
4085 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
4086 {
4087 }
4088
4089 }
4090
MHal_PNL_GetPanelVStart(void)4091 MS_U16 MHal_PNL_GetPanelVStart(void)
4092 {
4093 return 8;
4094 }
4095
MHal_PNL_Check_VBY1_Handshake_Status(void * pInstance)4096 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance)
4097 {
4098 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE)
4099 {
4100 //printf("VBY1 handshake return because the reg value is 0x%u, not 0xFAE.\n", MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF));
4101 return FALSE;
4102 }
4103 else
4104 {
4105 //printf("VBY handshake check success.\n");
4106 return TRUE;
4107 }
4108 }
4109
MHal_PNL_ChannelFIFOPointerADjust(void * pInstance)4110 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance)
4111 {
4112 // 0 to 1 then will do write and read point capture to
4113 // Read : REG_MOD_BK00_5F_L[14:12]
4114 // write : REG_MOD_BK00_5F_L[10:8]
4115 // it takes 3 ticks to capture and riu takes 5 ticks to write
4116 // so we don't have to do any delay between rising capture and
4117 // read/write pointer recognition
4118 MsOS_DelayTaskUs(500);
4119 MOD_A_W2BYTE(REG_MOD_A_BK00_5C_L, 0x3300);
4120
4121 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
4122 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
4123
4124 //split Video & OSD process start bit
4125 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
4126 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
4127 {
4128 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
4129 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
4130 }
4131
4132 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
4133 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
4134
4135 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
4136 MS_U16 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4137 MS_S8 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4138 MS_S8 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4139
4140 //OSD part
4141 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
4142 MS_U16 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4143 MS_S8 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4144 MS_S8 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4145
4146 MS_BOOL bOSDC = ((MOD_A_R2BYTE(REG_MOD_A_BK00_58_L)&0x00F0) == 0x0040)?TRUE:FALSE;
4147 while (((abs(u8WritePointer-u8ReadPointer) >4) && (abs(u8WritePointer-u8ReadPointer)<2))
4148 ||(((abs(OSDu8WritePointer-OSDu8ReadPointer) >4) && (abs(OSDu8WritePointer-OSDu8ReadPointer)<2))&&bOSDC))
4149 {
4150 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
4151 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
4152
4153 //split Video & OSD process start bit
4154 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
4155 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
4156 {
4157 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
4158 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
4159 }
4160
4161 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
4162 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
4163
4164 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
4165 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4166 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4167 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4168
4169 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
4170 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4171 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4172 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4173 printf("bOSDC [%d]\n",bOSDC);
4174
4175 }
4176
4177 }
4178
MHal_PNL_VBY1_Hardware_TrainingMode_En(void * pInstance,MS_BOOL bIsVideoMode,MS_BOOL bEnable)4179 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable)
4180 {
4181 if(bIsVideoMode)
4182 {
4183 if(bEnable)
4184 {
4185 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE);
4186 }
4187 else
4188 {
4189 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AA6);
4190 }
4191 }
4192 else
4193 {
4194 if(bEnable)
4195 {
4196 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE);
4197 }
4198 else
4199 {
4200 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6);
4201 }
4202 }
4203 }
4204
MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void * pInstance)4205 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance)
4206 {
4207 #ifdef SUPPORT_VBY1_HWTRAINING_MODE
4208 return TRUE;
4209 #else
4210 return FALSE;
4211 #endif
4212 }
4213
MHal_PNL_TCON_Patch(void)4214 void MHal_PNL_TCON_Patch(void)
4215 {
4216 //tcon apply new tcon.bin in maxim
4217 //so change patch
4218 //step 1: enable param.
4219 //step 2: delay one vysnc
4220 //step 3: disable param.
4221
4222 W2BYTEMSK(REG_SC2_00_L, 0x0008, 0x000F);
4223 W2BYTEMSK(REG_SC2_03_L, 0x0002, 0x0002);
4224 MsOS_DelayTask(20);
4225 W2BYTEMSK(REG_SC2_03_L, 0x0000, 0x0002);
4226 #if 0
4227 // MOD sw reset
4228 MOD_W2BYTE(REG_MOD_BK00_42_L,0x0000);
4229 MOD_W2BYTE(REG_MOD_BK00_42_L,0x1000);
4230
4231 // Setting TCON signal through MOD PAD
4232 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1811);
4233 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9811);
4234 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
4235 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1912);
4236 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9912);
4237 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
4238 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1a13);
4239 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9a13);
4240 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
4241 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1b17);
4242 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9b17);
4243 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
4244 #endif
4245
4246 }
4247
_Hal_MOD_External_eFuse(void)4248 static MS_BOOL _Hal_MOD_External_eFuse(void)
4249 {
4250 #ifdef MOD_EFUSE_IN_MBOOT
4251 return TRUE;
4252 #else
4253 return FALSE;
4254 #endif
4255 }
4256
4257 #endif
4258
4259
4260