Lines Matching refs:L_CLKGEN0

1778 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK);      // select source tobe LPLL cl…  in MHal_PNL_Init_XC_Clk()
1779     W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT);               // clock not invert  in MHal_PNL_Init_XC_Clk()
1780     W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED);                // enable clock  in MHal_PNL_Init_XC_Clk()
1782     W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0);      //  reg_ckg_odclk_mft  in MHal_PNL_Init_XC_Clk()
1785 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_BT656_CLK_LPLL, CKG_BT656_MASK);      // select source tobe LPLL cl…  in MHal_PNL_Init_XC_Clk()
1786     W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT);               // clock not invert  in MHal_PNL_Init_XC_Clk()
1787     W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED);                // enable clock  in MHal_PNL_Init_XC_Clk()
1789     W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo  in MHal_PNL_Init_XC_Clk()
1790     W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod  in MHal_PNL_Init_XC_Clk()
1791     W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod  in MHal_PNL_Init_XC_Clk()
1803         W2BYTE(L_CLKGEN0(0x63), 0x0410);   //[11:8]ckg_tx_mod_osd[4:0]osd2mod  in MHal_PNL_Init_XC_Clk()