1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _HAL_PNL_C_
79 #define _HAL_PNL_C_
80
81 //-------------------------------------------------------------------------------------------------
82 // Include Files
83 //-------------------------------------------------------------------------------------------------
84
85 #include "MsCommon.h"
86 #include "MsTypes.h"
87 #include "utopia.h"
88 #include "utopia_dapi.h"
89 #include "apiPNL.h"
90 #include "apiPNL_v2.h"
91 #include "drvPNL.h"
92 #include "halPNL.h"
93 #include "PNL_private.h"
94 #include "pnl_hwreg_utility2.h"
95 #include "Mooney_pnl_lpll_tbl.h"
96 #include "Mooney_pnl_lpll_ext_tbl.h"
97
98 #ifdef MSOS_TYPE_LINUX_KERNEL
99 #include <linux/string.h>
100 #include <linux/delay.h>
101 #include <asm/div64.h>
102 #else
103 #include "string.h"
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114
115 #define UNUSED(x) (x=x)
116 #if 1
117 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) printf("PNL:"_fmt, ##_args); }
118 #define HAL_MOD_CAL_DBG(x) //x
119 #else
120 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { }
121 #endif
122
123 #define DAC_LPLL_ICTRL 0x0002
124 #define LVDS_LPLL_ICTRL 0x0001
125
126 //Get MOD calibration time
127 #define MOD_CAL_TIMER FALSE
128
129 //if mboot read eFuse and fill the register, then add this define to mark utopia efuse code flow
130 #define MOD_EFUSE_IN_MBOOT
131 //-------------------------------------------------------------------------------------------------
132 // Local Structurs
133 //-------------------------------------------------------------------------------------------------
134
135 //-------------------------------------------------------------------------------------------------
136 // Global Variables
137 //-------------------------------------------------------------------------------------------------
138 #define LANE_NUM_EACH_PINMAPPING_GROUP1 4
139 #define LANE_NUM_EACH_PINMAPPING_GROUP2 4
140 #define LANE_NUM_EACH_PINMAPPING_GROUP3 4
141 #define LANE_NUM_EACH_PINMAPPING_GROUP4 2
142
143 #define PINMAPPING_EXP 16
144 //-------------------------------------------------------------------------------------------------
145 // Local Variables
146 //-------------------------------------------------------------------------------------------------
147 MS_U8 LANE_AND_CLK_TBL[VBY1_CLK_TBL_ROW][3]=
148 { //lane(from) lane(to) bit(mask)
149 { 0, 3, 0x02, },
150 { 4, 6, 0x04, },
151 { 7, 9, 0x08, },
152 { 10, 13, 0x10, }
153 };
154 //-------------------------------------------------------------------------------------------------
155 // Debug Functions
156 //-------------------------------------------------------------------------------------------------
157
158 //-------------------------------------------------------------------------------------------------
159 // Local Functions
160 //-------------------------------------------------------------------------------------------------
161 static void _MHal_PNL_Auto_Set_Config(void *pInstance,
162 MS_U16 u16OutputOrder0_3,
163 MS_U16 u16OutputOrder4_7,
164 MS_U16 u16OutputOrder8_11,
165 MS_U16 u16OutputOrder12_13);
166 #if 0
167 static void _MHal_PNL_Set_Clk(void *pInstance,
168 MS_U8 u8LaneNum,
169 MS_U16 u16OutputOrder0_3,
170 MS_U16 u16OutputOrder4_7,
171 MS_U16 u16OutputOrder8_11,
172 MS_U16 u16OutputOrder12_13);
173 #endif
174
175 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance);
176
177 static MS_BOOL _Hal_MOD_External_eFuse(void);
178
179 //-------------------------------------------------------------------------------------------------
180 // Global Function
181 //-------------------------------------------------------------------------------------------------
182 /**
183 * @brief: Power On MOD. but not mutex protected
184 *
185 */
MHal_MOD_PowerOn(void * pInstance,MS_BOOL bEn,MS_U8 u8LPLL_Type,MS_U8 DualModeType,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)186 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
187 {
188 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
189 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
190 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
191 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
192
193 if( bEn )
194 {
195 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8));
196
197 //analog MOD power down. 1: power down, 0: power up
198 // For Mod2 no output signel
199 ///////////////////////////////////////////////////
200
201 //2. Power on MOD (current and regulator)
202 if(u8LPLL_Type == E_PNL_TYPE_TTL)
203 {
204 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0) , BIT(0));
205 }
206 else
207 {
208 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0));
209 }
210 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8));
211
212
213 // 3. 4. 5.
214 MHal_Output_LVDS_Pair_Setting(pInstance, DualModeType, u16OutputCFG0_7, u16OutputCFG8_15, u16OutputCFG16_21);
215
216
217 //enable ib, enable ck
218 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0)));
219
220 // clock gen of dot-mini
221 if(u8LPLL_Type == E_PNL_TYPE_MINILVDS)
222 {
223 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x4400);
224 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x4400);
225 }
226 else if((u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
227 (u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)||
228 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE) ||
229 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_2LANE))
230
231 {
232 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
233 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
234 // [7:4]reg_ckg_dot_mini_pre_osd
235 }
236 //// for osd dedicated output port, 1 port for video and 1 port for osd
237 else if((u8LPLL_Type == E_PNL_TYPE_HS_LVDS)&&
238 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
239 {
240 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
241 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
242 // [7:4]reg_ckg_dot_mini_pre_osd
243 }
244 #if 0 // this only for 8V4O case, no need this for Maxim 23x23 8V case
245 else if(u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
246 {
247 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); // [11:8]reg_ckg_dot_mini_pre2_osd
248 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
249 }
250 #endif
251 else
252 {
253 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0000);
254 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0000);
255 }
256
257 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0x0008, 0x0008); // reg_fix_cnt_clr
258 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0x0000, 0x0008);
259
260 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0080, 0x0080); // reg_proc_st_clr
261 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0000, 0x0080);
262
263 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0080, 0x0080); // reg_unlock_cnt_clr
264 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x0080);
265
266 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x0000, 0x8000);
267 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x8000, 0x8000);
268 }
269 else
270 {
271 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8));
272 if(u8LPLL_Type !=E_PNL_TYPE_MINILVDS)
273 {
274 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: power up
275 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8));
276 }
277
278 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib, enable ck
279
280 // clock gen of dot-mini
281 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x1100);
282 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x1100);
283
284 if( IsVBY1(u8LPLL_Type) )
285 {
286 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
287 MsOS_DelayTask(1);
288 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
289 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
290 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
291 }
292 }
293 return 1;
294 }
295
296 /**
297 * @brief: Setup the PVDD power 1:2.5V, 0:3.3V
298 *
299 */
MHal_MOD_PVDD_Power_Setting(void * pInstance,MS_BOOL bIs2p5)300 void MHal_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5)
301 {
302 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, ((bIs2p5)? BIT(6):0), BIT(6)); //MOD PVDD=1: 0.9
303 }
304
MHal_PNL_TCON_Init(void * pInstance)305 void MHal_PNL_TCON_Init(void *pInstance)
306 {
307
308 }
309
MHal_Shift_LVDS_Pair(void * pInstance,MS_U8 Type)310 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type)
311 {
312 if(Type == 1)
313 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LVDS Mode3
314 else
315 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6)));
316
317 }
318
MHal_Output_LVDS_Pair_Setting(void * pInstance,MS_U8 Type,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)319 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
320 {
321
322 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
323 {
324 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
325 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x1554);
326 }
327 else if(Type == LVDS_SINGLE_OUTPUT_A)
328 {
329 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
330 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
331 }
332 else if( Type == LVDS_SINGLE_OUTPUT_B)
333 {
334 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
335 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
336 }
337 else if( Type == LVDS_OUTPUT_User)
338 {
339 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16OutputCFG0_7);
340 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16OutputCFG8_15);
341 }
342 else
343 {
344 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
345 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
346 }
347
348 MsOS_DelayTask(2);
349
350
351 }
352
_MHal_PNL_Get_LaneNum(void * pInstance)353 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance)
354 {
355 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
356 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
357 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
358 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
359
360 MS_U8 u8LaneNum = 0;
361 //check lane num
362 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
363 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
364 {
365 u8LaneNum = 8;
366 }
367 else if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
368 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
369 {
370 u8LaneNum = 4;
371 }
372 else if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)
373 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
374 {
375 u8LaneNum = 2;
376 }
377 else
378 {
379 u8LaneNum = 0;
380 }
381 return u8LaneNum;
382 }
383
384
_MHal_PNL_Auto_Set_Config(void * pInstance,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)385 static void _MHal_PNL_Auto_Set_Config(void *pInstance,
386 MS_U16 u16OutputOrder0_3,
387 MS_U16 u16OutputOrder4_7,
388 MS_U16 u16OutputOrder8_11,
389 MS_U16 u16OutputOrder12_13)
390 {
391 //attention : This function just support vby1 now.
392 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
393 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
394 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
395 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
396
397
398 MS_U8 u8OutputConfigCount = 0;
399 MS_U16 u16Config =0;
400 MS_U8 u8Count = 0;
401 MS_U8 u8LaneNum = 0;
402 MS_BOOL bSkip = TRUE;
403
404 //check lane num
405 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
406 if(u8LaneNum!=0)
407 {
408 bSkip = FALSE;
409 }
410 else
411 {
412 bSkip = TRUE;
413
414 //use default config
415 MHal_Output_LVDS_Pair_Setting(pInstance,
416 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
417 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
418 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
419 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
420 }
421
422 if(!bSkip)
423 {
424 //set output config
425 u16Config = 0;
426 u8OutputConfigCount = 0;
427 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP1 ; u8Count++ )
428 {
429 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
430 {
431 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
432 }
433 u16OutputOrder0_3 = u16OutputOrder0_3 / PINMAPPING_EXP;
434 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
435 }
436 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP2 ; u8Count++ )
437 {
438 if( (u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
439 {
440 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
441 }
442 u16OutputOrder4_7 = u16OutputOrder4_7 / PINMAPPING_EXP;
443 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
444 }
445 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16Config);
446
447 u16Config =0;
448 u8OutputConfigCount = 0;
449 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP3 ; u8Count++ )
450 {
451 if( (u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
452 {
453 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
454 }
455 u16OutputOrder8_11 = u16OutputOrder8_11 / PINMAPPING_EXP;
456 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
457 }
458 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP4 ; u8Count++ )
459 {
460 if( (u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
461 {
462 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
463 }
464 u16OutputOrder12_13 = u16OutputOrder12_13 / PINMAPPING_EXP;
465 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
466 }
467 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16Config);
468
469 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
470 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
471 }
472 }
473
474 #if 0
475 static void _MHal_PNL_Set_Clk(void *pInstance,
476 MS_U8 Type,
477 MS_U16 u16OutputOrder0_3,
478 MS_U16 u16OutputOrder4_7,
479 MS_U16 u16OutputOrder8_11,
480 MS_U16 u16OutputOrder12_13)
481 {
482 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
483 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
484 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
485 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
486
487 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
488 {
489 MS_U8 u8Clk = 0;
490 MS_U8 u8LaneNum = 0;
491 MS_BOOL bSkip = TRUE;
492 MS_U8 u8Count = 0;
493 MS_U8 u8Count1 = 0;
494 MS_U8 u8StartLane = 0;
495
496 //check lane num
497 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
498 if(u8LaneNum!=0)
499 {
500 bSkip = FALSE;
501 }
502 else
503 {
504 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //open all clk
505 bSkip = TRUE;
506 }
507
508 //count clk
509 if(!bSkip)
510 {
511 u8Clk = 0;
512 u8StartLane = 0;
513 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP1) ; u8Count++ )
514 {//lane 0 - lane 3
515 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
516 {
517 u8Count1 = 0;
518 do
519 {
520 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
521 {
522 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
523 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
524 break;
525 }
526 u8Count1 ++;
527 }
528 while(u8Count1<VBY1_CLK_TBL_ROW);
529 }
530 u16OutputOrder0_3 /= PINMAPPING_EXP;
531 }
532
533 u8StartLane = 4;
534 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP2) ; u8Count++ )
535 {//lane 4 - lane 7
536 if( ( u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
537 {
538 u8Count1 = 0;
539 do
540 {
541 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
542 {
543 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
544 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
545 break;
546 }
547 u8Count1 ++;
548 }
549 while(u8Count1<VBY1_CLK_TBL_ROW);
550 }
551 u16OutputOrder4_7 /= PINMAPPING_EXP;
552 }
553
554 u8StartLane = 8;
555 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP3) ; u8Count++ )
556 {//lane 8 - lane 11
557 if( ( u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
558 {
559 u8Count1 = 0;
560 do
561 {
562 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
563 {
564 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
565 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
566 break;
567 }
568 u8Count1 ++;
569 }
570 while(u8Count1<VBY1_CLK_TBL_ROW);
571 }
572 u16OutputOrder8_11 /= PINMAPPING_EXP;
573
574 }
575
576 u8StartLane = 12;
577 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP4) ; u8Count++ )
578 {//lane 12 - lane 13
579 if( ( u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
580 {
581 u8Count1 = 0;
582 do
583 {
584 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
585 {
586 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
587 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
588 break;
589 }
590 u8Count1 ++;
591 }
592 while(u8Count1<VBY1_CLK_TBL_ROW);
593 }
594 u16OutputOrder12_13 /= PINMAPPING_EXP;
595 }
596
597 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u8Clk, 0x1F);
598 }
599 }
600 else
601 {
602 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
603 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
604 {
605 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
606 {
607 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
608 }
609 else
610 {
611 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0F, 0x1F);
612 }
613 }
614 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
615 {//LVDS
616 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
617 }
618 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
619 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
620 {
621 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
622 }
623 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)
624 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
625 {
626 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x03, 0x1F);
627 }
628 else
629 {
630 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
631 }
632 }
633 }
634 #endif
635
MHal_Output_Channel_Order(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)636 void MHal_Output_Channel_Order(void *pInstance,
637 MS_U8 Type,
638 MS_U16 u16OutputOrder0_3,
639 MS_U16 u16OutputOrder4_7,
640 MS_U16 u16OutputOrder8_11,
641 MS_U16 u16OutputOrder12_13)
642 {
643 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
644 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
645 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
646 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
647
648 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
649 {
650 MOD_W2BYTE(REG_MOD_BK00_08_L, u16OutputOrder0_3);
651 MOD_W2BYTE(REG_MOD_BK00_09_L, u16OutputOrder4_7);
652 MOD_W2BYTE(REG_MOD_BK00_0A_L, u16OutputOrder8_11);
653 MOD_W2BYTE(REG_MOD_BK00_0B_L, u16OutputOrder12_13);
654 }
655 else
656 {
657 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
658 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
659 {
660 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // 2 Divisoin
661 {
662 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x0000);
663 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x6420);
664 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7531);
665 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
666 }
667 else
668 {
669 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x0000);
670 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x3210);
671 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7654);
672 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
673 }
674 }
675 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
676 {//LVDS
677 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x10DC);
678 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x5432);
679 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x9876);
680 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0xFEBA);
681 }
682 else
683 {// default is VB1 4lane/2lane
684 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x0000);
685 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x3210);
686 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7654);
687 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
688 }
689 }
690
691 }
692
MHal_PQ_Clock_Gen_For_Gamma(void * pInstance)693 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance)
694 {
695 W2BYTEMSK(REG_CLKGEN0_52_L, 0x00, 0x07);
696 }
697
MHal_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)698 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping)
699 {
700 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
701 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
702
703 if(u8Mapping & GAMMA_MAPPING)
704 {
705 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_74_L, (u8Mapping & GAMMA_10BIT_MAPPING)? BIT(15):0, BIT(15));
706 }
707 else
708 {
709 PNL_ASSERT(0, "Invalid eSupportGammaMapMode [%d] Passed to [%s], please make sure the u8Mapping[%d] is valid\n.",
710 u8Mapping, __FUNCTION__, u8Mapping);
711 }
712 }
713
Hal_VOP_Is_GammaMappingMode_enable(void * pInstance)714 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance)
715 {
716 // Only support 1024 entry
717 return TRUE;
718 }
719
720 // After A5, 8 bit mode only support burst write!!!
Hal_VOP_Is_GammaSupportSignalWrite(void * pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)721 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)
722 {
723 if( u8Mapping == E_DRVPNL_GAMMA_10BIT_MAPPING )
724 return TRUE;
725 else
726 return FALSE;
727 }
728
729
hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)730 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
731 {
732 MS_U16 u16Delay = 0xFFFF;
733 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
734 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
735
736 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write SC%tu [ch %d][addr 0x%x]: 0x%x \n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16Addr, u16GammaValue);
737
738 if (!bBurstWrite )
739 {
740 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
741 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
742
743 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6C_L, u16Addr, 0x3FF); // set address port
744 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_6E_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
745
746 // kick off write
747 switch(u8Channel)
748 {
749 case 0: // Red
750 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(5), BIT(5));
751 break;
752
753 case 1: // Green
754 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(6), BIT(6));
755 break;
756
757 case 2: // Blue
758 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(7), BIT(7));
759 break;
760 }
761
762 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
763 }
764 else
765 {
766
767 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_72_L, u16GammaValue, 0xFFF);
768 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK00_7F_L, 0x00); // make little time delay
769 }
770
771
772 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
773
774 }
775
776
hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)777 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
778 {
779 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
780 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
781
782 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of SC%tu %d is 0x%x\n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16MaxGammaValue);
783 #ifdef MONACO_SC2
784 if(pPNLInstancePrivate->u32DeviceID == 0)
785 {
786 #endif
787 switch(u8Channel)
788 {
789 case 0: // max. Red
790 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 0
791 break;
792
793 case 1: // max. Green
794 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 1
795 break;
796
797 case 2: //max. Blue
798 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
799 break;
800 }
801 #ifdef MONACO_SC2
802 }else //Nike
803 {
804 switch(u8Channel)
805 {
806 case 0: // max. Red
807 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7A_L , u16MaxGammaValue, 0xFFF); // max. base 0
808 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7B_L , u16MaxGammaValue, 0xFFF); // max. base 1
809 break;
810
811 case 1: // max. Green
812 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7C_L , u16MaxGammaValue, 0xFFF); // max. base 0
813 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 1
814 break;
815
816 case 2: //max. Blue
817 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 0
818 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
819 break;
820 }
821
822 }
823 #endif
824 }
825
826 /////////////////////////////////////////////////////////////////////////////
827 // Gamma format (12 bit LUT)
828 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
829 // 1 set uses 2 bytes of memory.
830 //
831 // [T2 and before ] N = 256
832 // [T3] N = 256 or 1024
833 // ______________________________________________________________________________
834 // Byte | 0 1 2 n-1 n
835 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
836 // 3:0 3:0 11:4 11:4 3:0 11:4
837 //
838
Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)839 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
840 {
841 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
842 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
843
844 MS_U16 u16Addr = 0;
845 MS_U16 u16CodeTableIndex = u16Addr/2*3;
846 MS_U16 u16GammaValue = 0;
847 MS_U16 u16MaxGammaValue = 0;
848 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
849 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
850
851 // Go to burst write if not support
852 if ( bUsingBurstWrite )
853 {
854 // 1. initial burst write address, LUT_ADDR[7:0]
855 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_71_L, 0x00 , 0x3FF);
856
857 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
858 switch(u8Channel)
859 {
860 case 0: // Red
861 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, 0x00 , BIT(6) | BIT(5) );
862 break;
863
864 case 1: // Green
865 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(5) , BIT(6) | BIT(5) );
866 break;
867
868 case 2: // Blue
869 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(6) , BIT(6) | BIT(5) );
870 break;
871 }
872
873 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
874 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(7) , BIT(7)); // Burst write enable
875
876 }
877
878 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
879 // write gamma table per one channel
880 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
881 {
882 // gamma x
883 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
884 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
885
886 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
887 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
888
889 if(u16MaxGammaValue < u16GammaValue)
890 {
891 u16MaxGammaValue = u16GammaValue;
892 }
893
894 // write gamma value
895 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
896 u16Addr++;
897
898 // gamma x+1
899 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
900 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
901
902 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
903
904 if(u16MaxGammaValue < u16GammaValue)
905 {
906 u16MaxGammaValue = u16GammaValue;
907 }
908
909 // write gamma value
910 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
911 u16Addr++;
912 }
913
914 if ( bUsingBurstWrite )
915 {
916 // 5. after finish burst write data of one channel, disable burst write mode
917 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, 0x00 , BIT(7));
918 }
919
920 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
921 }
922 /////////////////////////////////////////////////////////////////////////////
923 // Gamma format (12 bit LUT)
924 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
925 // 1 set uses 2 bytes of memory.
926 //
927 // [T2 and before ] N = 256
928 // [T3] N = 256 or 1024
929 // ______________________________________________________________________________
930 // Byte | 0 1 2 n-1 n
931 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
932 // 3:0 3:0 11:4 11:4 3:0 11:4
933 //
934 #ifdef MONACO_SC2
Hal_PNL_Set12BitGammaPerChannel_SC2(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)935 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
936 {
937 MS_U16 u16Addr = 0;
938 MS_U16 u16CodeTableIndex = u16Addr/2*3;
939 MS_U16 u16GammaValue = 0;
940 MS_U16 u16MaxGammaValue = 0;
941 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
942 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
943 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
944 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
945
946 // Go to burst write if not support
947 if ( bUsingBurstWrite )
948 {
949 // 1. initial burst write address, LUT_ADDR[7:0]
950 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
951
952 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
953 switch(u8Channel)
954 {
955 case 0: // Red
956 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
957 break;
958
959 case 1: // Green
960 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
961 break;
962
963 case 2: // Blue
964 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
965 break;
966 }
967
968 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
969 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
970
971 }
972
973 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
974 // write gamma table per one channel
975 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
976 {
977 // gamma x
978 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
979 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
980
981 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
982 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
983
984 if(u16MaxGammaValue < u16GammaValue)
985 {
986 u16MaxGammaValue = u16GammaValue;
987 }
988
989 // write gamma value
990 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
991 u16Addr++;
992
993 // gamma x+1
994 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
995 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
996
997 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
998
999 if(u16MaxGammaValue < u16GammaValue)
1000 {
1001 u16MaxGammaValue = u16GammaValue;
1002 }
1003
1004 // write gamma value
1005 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
1006 u16Addr++;
1007 }
1008
1009 if ( bUsingBurstWrite )
1010 {
1011 // 5. after finish burst write data of one channel, disable burst write mode
1012 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(0));
1013 }
1014
1015 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
1016 }
1017 #endif
1018 // src : 1 (scaler lpll)
1019 // src : 0 (frc lpll)
MHal_PNL_FRC_lpll_src_sel(void * pInstance,MS_U8 u8src)1020 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src)
1021 {
1022 if (u8src > 1)
1023 {
1024 return FALSE;
1025 }
1026 else
1027 {
1028 //Not support FRCINSIDE(frc lpll) for Monet
1029 #if 0
1030 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F);
1031 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8));
1032
1033 if(u8src==0)
1034 {
1035 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F);
1036 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8));
1037 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0
1038 }
1039 #endif
1040 return TRUE;
1041 }
1042
1043 }
1044
_MHal_PNL_GetSupportedLPLLIndex(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz,PNL_LPLL_TYPE_SEL lpll_type_sel)1045 static MS_U8 _MHal_PNL_GetSupportedLPLLIndex(void *pInstance,
1046 PNL_TYPE eLPLL_Type,
1047 PNL_MODE eLPLL_Mode,
1048 MS_U64 ldHz, PNL_LPLL_TYPE_SEL lpll_type_sel)
1049 {
1050 MS_U8 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1051 #if defined (__aarch64__)
1052 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
1053 #else
1054 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
1055 #endif
1056
1057 /// Mini LVDS, EPI34/28, LVDS_1CH, Vx1_1P are 1P structure
1058 if(!((eLPLL_Type == E_PNL_TYPE_TTL)||
1059 ((eLPLL_Type == E_PNL_TYPE_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
1060 ((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
1061 (eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_1LANE)||(eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_1LANE)||
1062 ((eLPLL_Type >= E_PNL_LPLL_MINILVDS_2CH_3P_8BIT)&&(eLPLL_Type <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT))||
1063 ((eLPLL_Type >= E_PNL_LPLL_EPI34_2P)&&(eLPLL_Type <= E_PNL_LPLL_EPI28_4P))))
1064 {
1065 ldHz/=2;
1066 }
1067
1068 switch(lpll_type_sel)
1069 {
1070 default:
1071 case E_PNL_LPLL_VIDEO:
1072 {
1073 switch (eLPLL_Type)
1074 {
1075 case E_PNL_TYPE_TTL:
1076 if ((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1077 {
1078 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_75to100MHz;
1079 }
1080 else if((ldHz >= 1000000000UL) && (ldHz < 1500000000UL))
1081 {
1082 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_100to150MHz;
1083 }
1084 else
1085 {
1086 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_75to75MHz;
1087 }
1088 break;
1089
1090 case E_PNL_TYPE_LVDS:
1091 switch (eLPLL_Mode)
1092 {
1093 case E_PNL_MODE_SINGLE:
1094 if ((ldHz >= 550000000UL) && (ldHz < 800000000UL))
1095 {
1096 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_55to80MHz;
1097 }
1098 else if ((ldHz >= 400000000UL) && (ldHz < 550000000UL))
1099 {
1100 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to55MHz;
1101 }
1102 else
1103 {
1104 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to40MHz;
1105 }
1106 break;
1107
1108 default:
1109 case E_PNL_MODE_DUAL:
1110 if ((ldHz >= 500000000UL) && (ldHz < 750000000UL))
1111 {
1112 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz;
1113 }
1114 else if ((ldHz >= 375000000UL) && (ldHz < 500000000UL))
1115 {
1116 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to50MHz;
1117 }
1118 else
1119 {
1120 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to37_5MHz;
1121 }
1122 break;
1123 }
1124 break;
1125
1126 case E_PNL_TYPE_HS_LVDS:
1127
1128 switch (eLPLL_Mode)
1129 {
1130 case E_PNL_MODE_SINGLE:
1131 if((ldHz >= 1000000000UL) && (ldHz < 1500000000UL))
1132 {
1133 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz;
1134 }
1135 else if((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1136 {
1137 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to100MHz;
1138 }
1139 else
1140 {
1141 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to75MHz;
1142 }
1143 break;
1144
1145 default:
1146 case E_PNL_MODE_DUAL:
1147 if((ldHz >= 1000000000UL) && (ldHz < 1500000000UL))
1148 {
1149 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz;
1150 }
1151 else if((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1152 {
1153 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to100MHz;
1154 }
1155 else
1156 {
1157 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to75MHz;
1158 }
1159 break;
1160 }
1161 break;
1162
1163 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
1164 if((ldHz >= 400000000UL) && (ldHz < 800000000UL))
1165 {
1166 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to80MHz;
1167 }
1168 else
1169 {
1170 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to40MHz;
1171 }
1172
1173 break;
1174
1175 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
1176 if((ldHz >= 750000000UL) && (ldHz < 1500000000UL))
1177 {
1178 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to150MHz;
1179 }
1180 else
1181 {
1182 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to75MHz;
1183 }
1184 break;
1185
1186 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
1187 if((ldHz >= 750000000UL) && (ldHz < 1500000000UL))
1188 {
1189 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to150MHz;
1190 }
1191 else
1192 {
1193 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to75MHz;
1194 }
1195 break;
1196
1197 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
1198 if((ldHz >= 666700000UL) && (ldHz < 800000000UL))
1199 {
1200 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz;
1201 }
1202 else if((ldHz >= 400000000UL) && (ldHz < 666700000UL))
1203 {
1204 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to66_67MHz;
1205 }
1206 else
1207 {
1208 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to40MHz;
1209 }
1210 break;
1211
1212 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
1213 if ((ldHz <= 1333300000UL) && (ldHz < 1500000000UL))
1214 {
1215 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_133_33to150MHz;
1216 }
1217 else if((ldHz >= 750000000UL) && (ldHz < 1333300000UL))
1218 {
1219 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to133_33MHz;
1220 }
1221 else
1222 {
1223 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to75MHz;
1224 }
1225 break;
1226
1227 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
1228 if ((ldHz <= 1333300000UL) && (ldHz < 1500000000UL))
1229 {
1230 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_133_33to150MHz;
1231 }
1232 else if((ldHz >= 750000000UL) && (ldHz < 1333300000UL))
1233 {
1234 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to133_33MHz;
1235 }
1236 else
1237 {
1238 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to75MHz;
1239 }
1240 break;
1241
1242
1243 #if 0
1244 //not support in mooney
1245 case E_PNL_LPLL_EPI34_2P:
1246 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_2PAIR_150to150MHz;
1247 break;
1248
1249 case E_PNL_LPLL_EPI34_4P:
1250 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_80to150MHz;
1251 break;
1252
1253 case E_PNL_LPLL_EPI34_6P:
1254 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz;
1255 break;
1256
1257 case E_PNL_LPLL_EPI34_8P:
1258 if((ldHz >= 800000000UL) && (ldHz < 1880000000UL))
1259 {
1260 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to188MHz;
1261 }
1262 else
1263 {
1264 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz;
1265 }
1266 break;
1267 #endif
1268
1269 case E_PNL_LPLL_EPI28_2P:
1270 if((ldHz >= 1150000000UL) && (ldHz < 1500000000UL))
1271 {
1272 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_115to150MHz;
1273 }
1274 else if((ldHz >= 750000000UL) && (ldHz < 1150000000UL))
1275 {
1276 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to115MHz;
1277 }
1278 else
1279 {
1280 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to75MHz;
1281 }
1282 break;
1283
1284 case E_PNL_LPLL_EPI28_4P:
1285 if((ldHz >= 1150000000UL) && (ldHz < 1500000000UL))
1286 {
1287 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_115to150MHz;
1288 }
1289 else if((ldHz >= 750000000UL) && (ldHz < 1150000000UL))
1290 {
1291 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to115MHz;
1292 }
1293 else
1294 {
1295 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to75MHz;
1296 }
1297 break;
1298
1299 case E_PNL_LPLL_EPI28_6P:
1300 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1301 {
1302 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to300MHz;
1303 }
1304 else
1305 {
1306 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to150MHz;
1307 }
1308 break;
1309
1310 case E_PNL_LPLL_EPI28_8P:
1311 if((ldHz >= 2300000000UL) && (ldHz < 3000000000UL))
1312 {
1313 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_230to300MHz;
1314 }
1315 else if((ldHz >= 1500000000UL) && (ldHz < 2300000000UL))
1316 {
1317 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to230MHz;
1318 }
1319 else
1320 {
1321 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to150MHz;
1322 }
1323 break;
1324
1325
1326 case E_PNL_LPLL_EPI28_12P:
1327 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1328 {
1329 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to300MHz;
1330 }
1331 else
1332 {
1333 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to150MHz;
1334 }
1335 break;
1336
1337 case E_PNL_LPLL_EPI28_16P:
1338 if((ldHz >= 2000000000UL) && (ldHz < 3000000000UL))
1339 {
1340 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_200to300MHz;
1341 }
1342 else if((ldHz >= 1500000000UL) && (ldHz < 2000000000UL))
1343 {
1344 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to200MHz;
1345 }
1346 else
1347 {
1348 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to150MHz;
1349 }
1350 break;
1351
1352 case E_PNL_LPLL_EPI24_12P:
1353 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1354 {
1355 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to300MHz;
1356 }
1357 else
1358 {
1359 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to150MHz;
1360 }
1361 break;
1362
1363 case E_PNL_LPLL_EPI24_16P:
1364 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1365 {
1366 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to300MHz;
1367 }
1368 else
1369 {
1370 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to150MHz;
1371 }
1372 break;
1373
1374 case E_PNL_LPLL_EPI28_6P_EPI3G:
1375 if((ldHz >= 1800000000UL) && (ldHz < 3000000000UL))
1376 {
1377 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz;
1378 }
1379 else if((ldHz >= 1500000000UL) && (ldHz < 1800000000UL))
1380 {
1381 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz;
1382 }
1383 else
1384 {
1385 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz;
1386 }
1387 break;
1388
1389 case E_PNL_LPLL_EPI28_8P_EPI3G:
1390 if((ldHz >= 2400000000UL) && (ldHz < 3000000000UL))
1391 {
1392 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_240to300MHz;
1393 }
1394 else if((ldHz >= 1500000000UL) && (ldHz < 2400000000UL))
1395 {
1396 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to240MHz;
1397 }
1398 else
1399 {
1400 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to150MHz;
1401 }
1402 break;
1403
1404
1405 case E_PNL_LPLL_CMPI24_10BIT_12P:
1406 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1407 {
1408 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to300MHz;
1409 }
1410 else
1411 {
1412 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to150MHz;
1413 }
1414 break;
1415
1416 case E_PNL_LPLL_CMPI27_8BIT_12P:
1417 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1418 {
1419 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to300MHz;
1420 }
1421 else
1422 {
1423 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to150MHz;
1424 }
1425 break;
1426
1427 case E_PNL_LPLL_USI_T_8BIT_12P:
1428 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1429 {
1430 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz;
1431 }
1432 else
1433 {
1434 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz;
1435 }
1436 break;
1437
1438 case E_PNL_LPLL_USI_T_10BIT_12P:
1439 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1440 {
1441 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz;
1442 }
1443 else
1444 {
1445 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz;
1446 }
1447 break;
1448
1449 case E_PNL_LPLL_ISP_8BIT_12P:
1450 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1451 {
1452 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz;
1453 }
1454 else
1455 {
1456 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz;
1457 }
1458 break;
1459
1460 case E_PNL_LPLL_ISP_8BIT_6P_D:
1461 if((ldHz >= 2000000000UL) && (ldHz < 3000000000UL))
1462 {
1463 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_200to300MHz;
1464 }
1465 else if((ldHz >= 1500000000UL) && (ldHz < 2000000000UL))
1466 {
1467 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to200MHz;
1468 }
1469 else
1470 {
1471 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz;
1472 }
1473 break;
1474
1475 case E_PNL_LPLL_ISP_8BIT_8P:
1476 if((ldHz >= 2490000000UL) && (ldHz < 3000000000UL))
1477 {
1478 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz;
1479 }
1480 else if((ldHz >= 1500000000UL) && (ldHz < 2490000000UL))
1481 {
1482 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz;
1483 }
1484 else
1485 {
1486 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz;
1487 }
1488 break;
1489
1490 case E_PNL_LPLL_ISP_10BIT_12P:
1491 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1492 {
1493 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz;
1494 }
1495 else
1496 {
1497 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz;
1498 }
1499 break;
1500
1501 case E_PNL_LPLL_ISP_10BIT_6P_D:
1502 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1503 {
1504 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to300MHz;
1505 }
1506 else
1507 {
1508 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to150MHz;
1509 }
1510 break;
1511
1512 case E_PNL_LPLL_ISP_10BIT_8P:
1513 if((ldHz >= 1992000000UL) && (ldHz < 3000000000UL))
1514 {
1515 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz;
1516 }
1517 else if((ldHz >= 1500000000UL) && (ldHz < 1992000000UL))
1518 {
1519 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz;
1520 }
1521 else
1522 {
1523 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz;
1524 }
1525 break;
1526
1527 /*
1528 case E_PNL_LPLL_EPI34_12P:
1529 break;
1530 */
1531
1532 case E_PNL_LPLL_VBY1_10BIT_8LANE:
1533 if((ldHz >= 1500000000UL) && (ldHz < 3000000000UL))
1534 {
1535 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz;
1536 }
1537 else
1538 {
1539 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz;
1540 }
1541 break;
1542
1543 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1544 if((ldHz >= 750000000UL) && (ldHz < 1500000000UL))
1545 {
1546 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz;
1547 }
1548 else
1549 {
1550 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz;
1551 }
1552 break;
1553
1554 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1555 if((ldHz >= 375000000UL) && (ldHz < 750000000UL))
1556 {
1557 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz;
1558 }
1559 else
1560 {
1561 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz;
1562 }
1563 break;
1564
1565 case E_PNL_LPLL_VBY1_8BIT_8LANE:
1566 if((ldHz >= 2000000000UL) && (ldHz < 3000000000UL))
1567 {
1568 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz;
1569 }
1570 else if((ldHz >= 1500000000UL) && (ldHz < 2000000000UL))
1571 {
1572 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz;
1573 }
1574 else
1575 {
1576 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz;
1577 }
1578 break;
1579
1580 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1581 if((ldHz >= 1000000000UL) && (ldHz < 1500000000UL))
1582 {
1583 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz;
1584 }
1585 else if((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1586 {
1587 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz;
1588 }
1589 else
1590 {
1591 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz;
1592 }
1593 break;
1594
1595 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1596 if((ldHz >= 500000000UL) && (ldHz < 750000000UL))
1597 {
1598 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz;
1599 }
1600 else if((ldHz >= 375000000UL) && (ldHz < 500000000UL))
1601 {
1602 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz;
1603 }
1604 else
1605 {
1606 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz;
1607 }
1608 break;
1609
1610 default:
1611 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1612 break;
1613 }
1614 }
1615 break;
1616 case E_PNL_LPLL_OSD:
1617 {
1618 switch (eLPLL_Type)
1619 {
1620 case E_PNL_TYPE_HS_LVDS:
1621 {
1622 if((ldHz >= 1000000000UL) && (ldHz < 1500000000UL))
1623 {
1624 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_100to150MHz;
1625 }
1626 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1627 {
1628 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_50to100MHz;
1629 }
1630 else if((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1631 {
1632 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to50MHz;
1633 }
1634 else
1635 {
1636 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz;
1637 }
1638 }
1639 break;
1640
1641 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1642 if((ldHz >= 1500000000UL) && (ldHz < 3400000000UL))
1643 {
1644 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to340MHz;
1645 }
1646 else
1647 {
1648 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to150MHz;
1649 }
1650 break;
1651
1652 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1653 if((ldHz >= 750000000UL) && (ldHz < 1500000000UL))
1654 {
1655 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to150MHz;
1656 }
1657 else
1658 {
1659 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to75MHz;
1660 }
1661 break;
1662
1663 case E_PNL_LPLL_VBY1_10BIT_1LANE:
1664 if((ldHz >= 375000000UL) && (ldHz < 750000000UL))
1665 {
1666 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to75MHz;
1667 }
1668 else
1669 {
1670 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to37_5MHz;
1671 }
1672 break;
1673
1674 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1675 if((ldHz >= 2000000000UL) && (ldHz < 3400000000UL))
1676 {
1677 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_200to340MHz;
1678 }
1679 else if((ldHz >= 1500000000UL) && (ldHz < 2000000000UL))
1680 {
1681 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to200MHz;
1682 }
1683 else
1684 {
1685 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to150MHz;
1686 }
1687 break;
1688
1689 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1690 if((ldHz >= 1000000000UL)&& (ldHz < 1500000000UL))
1691 {
1692 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_100to150MHz;
1693 }
1694 else if((ldHz >= 750000000UL)&& (ldHz < 1000000000UL))
1695 {
1696 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to100MHz;
1697 }
1698 else
1699 {
1700 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to75MHz;
1701 }
1702 break;
1703
1704 case E_PNL_LPLL_VBY1_8BIT_1LANE:
1705 if((ldHz >= 500000000UL) && (ldHz < 750000000UL))
1706 {
1707 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_50to75MHz;
1708 }
1709 else if((ldHz >= 375000000UL) && (ldHz < 500000000UL))
1710 {
1711 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to50MHz;
1712 }
1713 else
1714 {
1715 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to37_5MHz;
1716 }
1717 break;
1718
1719 default:
1720 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
1721 break;
1722 }
1723 }
1724 break;
1725 }
1726 return u8SupportedLPLLIndex;
1727 }
1728
_MHal_PNL_DumpLPLLTable(void * pInstance,MS_U8 LPLLTblIndex,PNL_LPLL_TYPE_SEL lpll_type_sel)1729 static void _MHal_PNL_DumpLPLLTable(void *pInstance, MS_U8 LPLLTblIndex, PNL_LPLL_TYPE_SEL lpll_type_sel)
1730 {
1731 if(lpll_type_sel == E_PNL_LPLL_VIDEO)
1732 {
1733 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_MAX)
1734 {
1735 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1736 return;
1737 }
1738
1739 int indexCounter = 0;
1740
1741 for(indexCounter = 0 ; indexCounter<LPLL_REG_NUM; indexCounter++)
1742 {
1743 if (LPLLSettingTBL[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1744 {
1745 MsOS_DelayTaskUs(LPLLSettingTBL[LPLLTblIndex][indexCounter].value);
1746 continue; // step forward to next register setting.
1747 }
1748
1749 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address),
1750 LPLLSettingTBL[LPLLTblIndex][indexCounter].value,
1751 LPLLSettingTBL[LPLLTblIndex][indexCounter].mask);
1752 }
1753 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1754 }
1755 else
1756 {
1757 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
1758 {
1759 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1760 return;
1761 }
1762
1763 int indexCounter = 0;
1764
1765 for(indexCounter = 0 ; indexCounter<LPLL_EXT_REG_NUM; indexCounter++)
1766 {
1767 if (LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1768 {
1769 MsOS_DelayTaskUs(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value);
1770 continue; // step forward to next register setting.
1771 }
1772
1773 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address),
1774 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value,
1775 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].mask);
1776 }
1777 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1778 }
1779 }
1780
MHal_PNL_Init_LPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)1781 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
1782 {
1783 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1784 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1785 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1786 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1787 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1788 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1789
1790 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_VIDEO);
1791
1792 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1793 {
1794 printf("Not Supported LPLL Type, skip LPLL Init\n");
1795 return;
1796 }
1797
1798 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_VIDEO);
1799
1800
1801 MHal_MOD_PVDD_Power_Setting(pInstance, pPNLResourcePrivate->sthalPNL._bPVDD_2V5); // Einstein is always use 3.3V PVDD Power.
1802 }
1803
MHal_PNL_Get_Loop_DIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1804 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1805 {
1806 MS_U16 u16loop_div = 0;
1807 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1808 #if defined (__aarch64__)
1809 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1810 #else
1811 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1812 #endif
1813 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1814
1815 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1816 {
1817 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1818 u16loop_div = 0 ;
1819 }
1820 else
1821 {
1822 u16loop_div = u16LoopDiv[u8SupportedLPLLLIndex];
1823 }
1824 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_div=%u\n", u16loop_div);
1825
1826 u16loop_div *= 2;
1827 return u16loop_div;
1828 }
1829
MHal_PNL_Get_LPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1830 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1831 {
1832 MS_U16 u16loop_gain = 0;
1833 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1834 #if defined (__aarch64__)
1835 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1836 #else
1837 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1838 #endif
1839 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1840
1841 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1842 {
1843 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1844 u16loop_gain = 0 ;
1845 }
1846 else
1847 {
1848 u16loop_gain = u16LoopGain[u8SupportedLPLLLIndex];
1849 }
1850 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_gain=%u\n", u16loop_gain);
1851 return u16loop_gain;
1852 }
1853
1854 #define SKIP_TIMING_CHANGE_CAP TRUE
Hal_PNL_SkipTimingChange_GetCaps(void * pInstance)1855 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance)
1856 {
1857 #if (SKIP_TIMING_CHANGE_CAP)
1858 return TRUE;
1859 #else
1860 return FALSE;
1861 #endif
1862 }
1863
MHal_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1864 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1865 {
1866 if (bSetMode == TRUE)
1867 {
1868 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15));
1869 }
1870 else
1871 {
1872 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15));
1873 }
1874 }
1875
MHal_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)1876 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo)
1877 {
1878 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1879 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1880 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1881 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1882
1883 if (lvdsresinfo.bEnable)
1884 {
1885 if (lvdsresinfo.u16channel & BIT(0)) // Channel A
1886 {
1887 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1888 {
1889 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15));
1890 }
1891 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1892 {
1893 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14));
1894 }
1895 }
1896 if (lvdsresinfo.u16channel & BIT(1)) // Channel B
1897 {
1898 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1899 {
1900 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13));
1901 }
1902 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1903 {
1904 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12));
1905 }
1906 }
1907
1908 if( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) )
1909 {
1910 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1: three_d_flag
1911 }
1912 }
1913 else
1914 {
1915 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12)));
1916
1917 if( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) )
1918 {
1919 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1: three_d_flag
1920 }
1921 }
1922 }
1923
1924 ////////////////////////////////////////////////////////////////////////
1925 // Turn OD function
1926 ////////////////////////////////////////////////////////////////////////
MHal_PNL_OverDriver_Init(void * pInstance,MS_PHY u32OD_MSB_Addr,MS_PHY u32OD_MSB_limit,MS_U32 u32OD_LSB_Addr,MS_U32 u32OD_LSB_limit,MS_U8 u8MIUSel)1927 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit, MS_U8 u8MIUSel)
1928 {
1929 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1930 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1931 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK16_61_L,u8MIUSel<<8,BIT(8)|BIT(9)); // OD MIU select
1932
1933 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_15_L, (MS_U16)(u32OD_MSB_Addr & 0xFFFF)); // OD MSB request base address
1934 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_16_L, (MS_U16)((u32OD_MSB_Addr >> 16) & 0x00FF), 0x00FF); // OD MSB request base address
1935 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_Addr >> 24) & 0x0003), 0x0003); // OD MSB request base address
1936 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_17_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD MSB request address limit
1937 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_18_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD MSB request address limit
1938 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_limit >> 24) & 0x0003)<<2, 0x000C); // OD MSB request address limit
1939 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_39_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer write address limit
1940 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer write address limit
1941 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3B_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer read address limit
1942 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3C_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer read address limit
1943 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_4F_L, (MS_U16)(u32OD_LSB_Addr & 0xFFFF)); // OD LSB request base address
1944 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_Addr >> 16) & 0x00FF), 0x00FF); // OD LSB request base address
1945 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_limit & 0x00FF) << 8), 0xFF00); // OD LSB request limit address
1946 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_51_L, (MS_U16)((u32OD_LSB_limit >> 8) & 0xFFFF)); // OD LSB request limit address
1947
1948 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1A_L, 0x4020); // OD request rFIFO limit threshold, priority threshold
1949 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1C_L, 0x4020); // OD request wFIFO limit threshold, priority threshold
1950 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x00, BIT(14)); // OD strength gradually bypass
1951 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x2F00, 0x3F00); // OD strength gradually slop
1952 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_12_L, 0x0C, 0xFF); // OD active threshold
1953
1954 }
1955
MHal_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1956 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable)
1957 {
1958 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1959 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1960
1961 // OD mode
1962 // OD used user weight to output blending directly
1963 // OD Enable
1964 if (bEnable)
1965 {
1966 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2D, 0x2F);
1967 }
1968 else
1969 {
1970 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2C, 0x2F);
1971 }
1972 }
1973
MHal_PNL_OverDriver_TBL(void * pInstance,MS_U8 u8ODTbl[1056])1974 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056])
1975 {
1976 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1977 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1978
1979 MS_U16 i;
1980 MS_U8 u8target;
1981 MS_BOOL bEnable;
1982
1983 bEnable = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, BIT(0));
1984 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x00, BIT(0)); // OD enable
1985 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x0E, 0x0E); // OD table SRAM enable, RGB channel
1986
1987 u8target= u8ODTbl[9];
1988 for (i=0; i<272; i++)
1989 {
1990 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_03_L, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
1991 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1992 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, BIT(15)));
1993 }
1994
1995 u8target= u8ODTbl[(272+19)];
1996 for (i=0; i<272; i++)
1997 {
1998 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_06_L, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
1999 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, (i|0x8000), 0x81FF);
2000 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, BIT(15)));
2001 }
2002
2003 u8target= u8ODTbl[(272*2+29)];
2004 for (i=0; i<256; i++)
2005 {
2006 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_09_L, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
2007 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
2008 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, BIT(15)));
2009 }
2010
2011 u8target= u8ODTbl[(272*2+256+39)];
2012 for (i=0; i<256; i++)
2013 {
2014 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0C_L, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
2015 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0B_L, (i|0x8000), 0x81FF);
2016 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0D_L, BIT(15)));
2017 }
2018
2019 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x00, 0x0E); // OD table SRAM enable, RGB channel
2020 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, bEnable, BIT(0)); // OD enable
2021 }
2022
_MHal_PNL_MOD_Swing_Refactor_AfterCAL(void * pInstance,MS_U16 u16Swing_Level)2023 MS_U16 _MHal_PNL_MOD_Swing_Refactor_AfterCAL(void *pInstance, MS_U16 u16Swing_Level)
2024 {
2025 MS_U8 u8ibcal = 0x00;
2026 MS_U16 u16AfterCal_value = 0;
2027 MS_U16 u16Cus_value = 0;
2028
2029 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2030 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2031 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2032 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2033 // =========
2034 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
2035 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
2036 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
2037 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
2038 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
2039 // =========
2040 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
2041 {
2042 default:
2043 case 0:
2044 u8ibcal = 0x15;
2045 break;
2046 case 1:
2047 u8ibcal = 0x1F;
2048 break;
2049 case 2:
2050 u8ibcal = 0x1A;
2051 break;
2052 case 3:
2053 u8ibcal = 0x10;
2054 break;
2055 }
2056 u16Cus_value = (u16Swing_Level) * (pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4)/(u8ibcal + 4);
2057 u16AfterCal_value = (u16Cus_value-40)/10+2;
2058
2059 HAL_MOD_CAL_DBG(printf("\r\n--Swing value after refactor = %d\n", u16AfterCal_value));
2060
2061 return u16AfterCal_value;
2062 }
2063
MHal_PNL_MODSwingRegToRealLevelValue(void * pInstance,MS_U16 u16SwingRegValue)2064 MS_U16 MHal_PNL_MODSwingRegToRealLevelValue(void *pInstance, MS_U16 u16SwingRegValue)
2065 {
2066 MS_U8 u8ibcal = 0x00;
2067 MS_U16 u16SwingRealLevelValue = 0;
2068 MS_U16 u16CusValue = 0;
2069 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2070 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2071 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2072 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2073 // =========
2074 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
2075 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
2076 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
2077 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
2078 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
2079 // =========
2080 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
2081 {
2082 default:
2083 case 0:
2084 u8ibcal = 0x15;
2085 break;
2086 case 1:
2087 u8ibcal = 0x1F;
2088 break;
2089 case 2:
2090 u8ibcal = 0x1A;
2091 break;
2092 case 3:
2093 u8ibcal = 0x10;
2094 break;
2095 }
2096
2097 u16CusValue = ((u16SwingRegValue-2)*10)+40;
2098 u16SwingRealLevelValue=(u16CusValue*(u8ibcal + 4))/(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4);
2099
2100 HAL_MOD_CAL_DBG(printf("\r\n--Swing Real Level Value = %d\n", u16SwingRealLevelValue));
2101
2102 return u16SwingRealLevelValue;
2103 }
2104
MHal_PNL_MOD_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)2105 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level)
2106 {
2107 MS_BOOL bStatus = FALSE;
2108
2109 MS_U16 u16ValidSwing = 0;
2110 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2111 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2112 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2113 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2114
2115 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)||
2116 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS))
2117 {
2118 if(u16Swing_Level>600)
2119 u16Swing_Level=600;
2120 if(u16Swing_Level<40)
2121 u16Swing_Level=40;
2122
2123 u16ValidSwing = _MHal_PNL_MOD_Swing_Refactor_AfterCAL(pInstance, u16Swing_Level);
2124 }
2125 else
2126 {
2127 u16ValidSwing = u16Swing_Level;
2128 }
2129
2130 // Disable HW calibration keep mode first, to make SW icon value can write into register.
2131 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
2132
2133 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2134 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
2135 {
2136 u16ValidSwing &=0x0F;
2137 // vby1 vreg
2138 // ch0+ch1+ch2+ch3
2139 MOD_A_W2BYTE(REG_MOD_A_BK00_20_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2140 // ch4+ch5+ch6+ch7
2141 MOD_A_W2BYTE(REG_MOD_A_BK00_21_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2142 // ch8+ch9+ch10+ch11
2143 MOD_A_W2BYTE(REG_MOD_A_BK00_22_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2144 // ch12+ch13+ch14+ch15
2145 MOD_A_W2BYTE(REG_MOD_A_BK00_23_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
2146 }
2147 else
2148 {
2149 u16ValidSwing &=0xFF;
2150 // LVDS fill ICON
2151 // ch0+ch1
2152 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, (u16ValidSwing << 8 | u16ValidSwing));
2153 // ch2+ch3
2154 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, (u16ValidSwing << 8 | u16ValidSwing));
2155 // ch4+ch5
2156 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, (u16ValidSwing << 8 | u16ValidSwing));
2157 // ch6+ch7
2158 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, (u16ValidSwing << 8 | u16ValidSwing));
2159 // ch8+ch9
2160 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, (u16ValidSwing << 8 | u16ValidSwing));
2161 // ch10+ch11
2162 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, (u16ValidSwing << 8 | u16ValidSwing));
2163 // ch12+ch13
2164 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, (u16ValidSwing << 8 | u16ValidSwing));
2165 // ch14+ch15
2166 MOD_A_W2BYTE(REG_MOD_A_BK00_0F_L, (u16ValidSwing << 8 | u16ValidSwing));
2167 }
2168 bStatus = TRUE;
2169
2170 return bStatus;
2171 }
2172
2173 ////////////////////////////////////////////////////////////////////////
2174 // Turn Pre-Emphasis Current function
2175 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_PE_Current(void * pInstance,MS_U16 u16Current_Level)2176 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level)
2177 {
2178 MS_BOOL bStatus = FALSE;
2179 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
2180
2181 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,
2182 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2183 |(u16ValidCurrent << 12 )));
2184
2185 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,
2186 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2187 |(u16ValidCurrent << 12 )));
2188
2189 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,
2190 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2191 |(u16ValidCurrent << 12 )));
2192
2193 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,
2194 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
2195 |(u16ValidCurrent << 12 )));
2196
2197 bStatus = TRUE;
2198
2199 return bStatus;
2200 }
2201
MHal_PNL_MOD_PECurrent_Setting(void * pInstance,MS_U16 u16Current_Level,MS_U16 u16Channel_Select)2202 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select)
2203 {
2204 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
2205 MS_U16 u16Ch00_03_mask,u16Ch04_07_mask,u16Ch08_11_mask,u16Ch12_15_mask = 0;
2206
2207 u16Ch00_03_mask = (((u16Channel_Select & BIT(0))? 0x000F:0x00)|((u16Channel_Select & BIT(1))? 0x00F0:0x00)
2208 |((u16Channel_Select & BIT(2))? 0x0F00:0x00)|((u16Channel_Select & BIT(3))? 0xF000:0x00));
2209 u16Ch04_07_mask = (((u16Channel_Select & BIT(4))? 0x000F:0x00)|((u16Channel_Select & BIT(5))? 0x00F0:0x00)
2210 |((u16Channel_Select & BIT(6))? 0x0F00:0x00)|((u16Channel_Select & BIT(7))? 0xF000:0x00));
2211 u16Ch08_11_mask = (((u16Channel_Select & BIT(8))? 0x000F:0x00)|((u16Channel_Select & BIT(9))? 0x00F0:0x00)
2212 |((u16Channel_Select & BIT(10))? 0x0F00:0x00)|((u16Channel_Select & BIT(11))? 0xF000:0x00));
2213 u16Ch12_15_mask = (((u16Channel_Select & BIT(12))? 0x000F:0x00)|((u16Channel_Select & BIT(13))? 0x00F0:0x00)
2214 |((u16Channel_Select & BIT(14))? 0x0F00:0x00)|((u16Channel_Select & BIT(15))? 0xF000:0x00));
2215
2216 if(u16Ch00_03_mask)
2217 {
2218 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L,
2219 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch00_03_mask);
2220 }
2221 else
2222 {
2223 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x00);
2224 }
2225
2226 if(u16Ch04_07_mask)
2227 {
2228 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L,
2229 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch04_07_mask);
2230 }
2231 else
2232 {
2233 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x00);
2234 }
2235
2236 if(u16Ch08_11_mask)
2237 {
2238 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L,
2239 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch08_11_mask);
2240 }
2241 else
2242 {
2243 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x00);
2244 }
2245
2246 if(u16Ch12_15_mask)
2247 {
2248 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L,
2249 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch12_15_mask);
2250 }
2251 else
2252 {
2253 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x00);
2254 }
2255 }
2256
2257 ////////////////////////////////////////////////////////////////////////
2258 // 1.Turn TTL low-power mode function
2259 // 2.Turn internal termination function
2260 // 3.Turn DRIVER BIAS OP function
2261 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_TTL_Resistor_OP(void * pInstance,MS_BOOL bEnble)2262 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL bEnble)
2263 {
2264 MS_BOOL bStatus = FALSE;
2265 if(bEnble)
2266 {
2267 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode
2268 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x001E, 0x001E);
2269
2270 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open)
2271 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F);
2272
2273 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP
2274 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F);
2275 }
2276 else
2277 {
2278 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode
2279 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x0000, 0x001E);
2280
2281 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close)
2282 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F);
2283
2284 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP
2285 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F);
2286 }
2287
2288 bStatus = TRUE;
2289 return bStatus;
2290 }
2291
MHal_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)2292 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam)
2293 {
2294 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2295 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2296 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2297 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2298 pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions = eParam;
2299 }
2300
MHal_PNL_Get_Output_MODE(void * pInstance)2301 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance)
2302 {
2303 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2304 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2305 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2306 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2307 PNL_OUTPUT_MODE eParam = pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions;
2308
2309 return eParam;
2310 }
2311
msReadEfuse(void * pInstance,MS_U8 u8Bank,MS_U32 u32Mask)2312 MS_U32 msReadEfuse(void *pInstance, MS_U8 u8Bank, MS_U32 u32Mask)
2313 {
2314 MS_U32 u32Result = 0;
2315 MS_U8 u8Count = 0;
2316
2317 W2BYTEMSK(0x2050, u8Bank<<2, BMASK(8:2)); /// reg28[8:2]Addr 6~0
2318 W2BYTEMSK(0x2050, BIT(13), BIT(13)); /// Reg28[13] Margin Read
2319 while(R2BYTEMSK(0x2050, BIT(13)) == BIT(13))
2320 {
2321 MsOS_DelayTask(1);
2322 u8Count ++;
2323
2324 if (u8Count >10)
2325 break;
2326 }
2327
2328 u32Result = (R4BYTE(0x2058)& u32Mask); /// reg2C,2D read value
2329 printf("[%s][%d]u32Result=%x, after mask u32Result=%x\n", __FUNCTION__, __LINE__, R4BYTE(0x2058), u32Result);
2330 return u32Result;
2331
2332 }
2333
msSetVBY1RconValue(void * pInstance)2334 void msSetVBY1RconValue(void *pInstance)
2335 {
2336 MS_U16 u16DefaultICON_Max = 40, u16DefaultICON_Min = 7;
2337 MS_U16 u16DefaultICON = 18;
2338 MS_U32 u32Mask = 0x3F;
2339 MS_BOOL bEfuseMode = FALSE;
2340 MS_U16 u16SwingOffset = 0; // by HW RD request
2341 MS_U16 u16temp = 0;
2342
2343 if(!(_Hal_MOD_External_eFuse()))
2344 {
2345 if (msReadEfuse(pInstance, 0x4E, BIT(6)) == BIT(6))
2346 bEfuseMode = TRUE;
2347
2348 // Disable HW calibration keep mode first, to make SW icon value can write into register.
2349 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
2350
2351 if (bEfuseMode)
2352 {
2353 if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) > u16DefaultICON_Max)
2354 u16temp = u16DefaultICON;
2355 else if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) < u16DefaultICON_Min)
2356 u16temp = u16DefaultICON;
2357 else
2358 u16temp = (MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset;
2359 }
2360 else
2361 {
2362 u16temp = u16DefaultICON;
2363 }
2364
2365 //ch0~ch13 rcon setting
2366 u16temp &= (u16temp&(MS_U16)u32Mask);
2367 printf("[%s][%d]u16temp= %x\n", __FUNCTION__, __LINE__, u16temp);
2368
2369 MOD_A_W2BYTE(REG_MOD_A_BK00_10_L, (u16temp<<8|u16temp));
2370 MOD_A_W2BYTE(REG_MOD_A_BK00_11_L, (u16temp<<8|u16temp));
2371 MOD_A_W2BYTE(REG_MOD_A_BK00_12_L, (u16temp<<8|u16temp));
2372 MOD_A_W2BYTE(REG_MOD_A_BK00_13_L, (u16temp<<8|u16temp));
2373 MOD_A_W2BYTE(REG_MOD_A_BK00_14_L, (u16temp<<8|u16temp));
2374 MOD_A_W2BYTE(REG_MOD_A_BK00_15_L, (u16temp<<8|u16temp));
2375 MOD_A_W2BYTE(REG_MOD_A_BK00_16_L, (u16temp<<8|u16temp));
2376 MOD_A_W2BYTE(REG_MOD_A_BK00_17_L, (u16temp<<8|u16temp));
2377 }
2378 }
2379
MHal_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)2380 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
2381 {
2382 MS_U16 u16ValidSwing2 = 0;
2383 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2384 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2385 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2386 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2387 if( eLPLL_Type == E_PNL_TYPE_TTL)
2388 {
2389 // select pair output to be TTL
2390 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2391 MsOS_DelayTask(1);
2392 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2393 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2394 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2395
2396 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair
2397
2398 // other TTL setting
2399 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x0000); // TTL output enable
2400
2401 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0x0000);
2402 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2403 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000);
2404
2405 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew
2406
2407 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007);//[2:0]reg_mft_mode
2408
2409 MOD_A_W2BYTE(REG_MOD_A_BK00_38_L, 0x0000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2410
2411 // GPO gating
2412 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating
2413 }
2414 else if(( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)||
2415 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
2416 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE))
2417 {
2418 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2
2419
2420 // rcon
2421 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE)
2422 {
2423 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
2424 MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel);
2425 }
2426 else
2427 {
2428 HAL_MOD_CAL_DBG(printf("Use RconValue\n", __FUNCTION__, __LINE__));
2429 msSetVBY1RconValue(pInstance);
2430 }
2431
2432 // rint
2433 MOD_A_W2BYTE(REG_MOD_A_BK00_32_L, 0x0000);
2434
2435 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003f);
2436
2437 //-------------------------------------
2438 //## pe
2439 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
2440 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
2441 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
2442 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
2443
2444 // VBY1 setting
2445 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0xFFFF);
2446
2447 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8F3F); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
2448 // MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2449
2450 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0xFFFF);
2451 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2452 MOD_A_W2BYTE(REG_MOD_A_BK00_48_L, 0xFFFF);
2453 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2454 MOD_A_W2BYTE(REG_MOD_A_BK00_42_L, 0xFFFF);
2455 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0xFFFF);
2456
2457 switch(eOutputMode)
2458 {
2459 case E_PNL_OUTPUT_NO_OUTPUT:
2460 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2461 MsOS_DelayTask(1);
2462 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2463 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2464 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2465 if(1)//( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2466 {
2467 //-------------------------------------
2468 //## icon (Swing)
2469 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
2470 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
2471
2472 //-------------------------------------
2473 //vby1
2474 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
2475 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2476 }
2477 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2478 {
2479 //-------------------------------------
2480 //## icon (Swing)
2481 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
2482 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
2483
2484 //vby1
2485 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f);
2486 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF);
2487 }
2488 break;
2489
2490 case E_PNL_OUTPUT_CLK_ONLY:
2491 case E_PNL_OUTPUT_DATA_ONLY:
2492 case E_PNL_OUTPUT_CLK_DATA:
2493 default:
2494 if(eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
2495 {
2496 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC100);
2497 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2498 {
2499 _MHal_PNL_Auto_Set_Config(pInstance,
2500 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2501 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2502 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2503 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2504 }
2505 else
2506 {
2507 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x5500); //[15:0]reg_output_conf[15:0]
2508 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0055); //[15:0]reg_output_conf[15:0]
2509 }
2510 }
2511 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2512 {
2513 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2514 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0002); //[1]reg_dualmode[0]abswitch
2515 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2516 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x7f7f);
2517
2518 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2519 {
2520 _MHal_PNL_Auto_Set_Config(pInstance,
2521 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2522 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2523 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2524 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2525 }
2526 else
2527 {
2528 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000); //[15:0]reg_output_conf[15:0]
2529 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0055); //[15:0]reg_output_conf[15:0]
2530 }
2531 }
2532 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2533 {
2534 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2535 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0000);
2536 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2537 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x0000);
2538
2539 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2540 {
2541 _MHal_PNL_Auto_Set_Config(pInstance,
2542 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2543 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2544 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2545 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2546 }
2547 else
2548 {
2549 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2550 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0005); //[15:0]reg_output_conf[15:0]
2551 }
2552
2553 }
2554 break;
2555 }
2556 }
2557 //// for osd dedicated output port, 1 port for video and 1 port for osd
2558 else if((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&
2559 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
2560 {
2561 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2562 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path
2563 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
2564 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2565 }
2566 else
2567 {
2568 switch(eOutputMode)
2569 {
2570 case E_PNL_OUTPUT_NO_OUTPUT:
2571 // if MOD_45[5:0] = 0x3F && XC_MOD_EXT_DATA_EN_L = 0x0,
2572 // then if XC_MOD_OUTPUT_CONF_L = 0x0 ---> output TTL as tri-state
2573 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2574 MsOS_DelayTask(1);
2575 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2576 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2577 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2578
2579 //----------------------------------
2580 // Purpose: Set the output to be the GPO, and let it's level to Low
2581 // 1. External Enable, Pair 0~5
2582 // 2. GPIO Enable, pair 0~5
2583 // 3. GPIO Output data : All low, pair 0~5
2584 // 4. GPIO OEZ: output piar 0~5
2585 //----------------------------------
2586
2587 //1.External Enable, Pair 0~5
2588 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF);
2589 //2.GPIO Enable, pair 0~5
2590 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF);
2591 //3.GPIO Output data : All low, pair 0~5
2592 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF);
2593 //4.GPIO OEZ: output piar 0~5
2594 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF);
2595
2596 //1.External Enable, Pair 6~15
2597 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000);
2598 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2599 //2.GPIO Enable, pair 6~15
2600 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000);
2601 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2602 //3.GPIO Output data : All low, pair 6~15
2603 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000);
2604 MOD_A_W2BYTE(REG_MOD_A_BK00_45_L, 0x0000);
2605 //4.GPIO OEZ: output piar 6~15
2606 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000);
2607 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0x0000);
2608
2609 //1234.External Enable, Pair 16~17
2610 MOD_W2BYTE(REG_MOD_BK00_7E_L, 0xFF00);
2611
2612 //1.External Enable, Pair 18~20, 2.GPIO Enable, pair 18~20
2613 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F);
2614 //3.GPIO Output data : All low, pair 18~20
2615 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00);
2616 //4.GPIO OEZ: output piar 18~20
2617 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00);
2618 break;
2619
2620 case E_PNL_OUTPUT_CLK_ONLY:
2621 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000);
2622 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x4004);
2623 break;
2624
2625 case E_PNL_OUTPUT_DATA_ONLY:
2626 case E_PNL_OUTPUT_CLK_DATA:
2627 default:
2628 // LVDS default setting
2629 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x5550);
2630 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
2631
2632 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000);
2633 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0x0000);
2634 //1. set GCR_PVDD_2P5=1¡¦b1; MOD PVDD power: 1: 2.5V
2635 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0, BIT(6));
2636 //2. set PD_IB_MOD=1¡¦b0;
2637 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(0));
2638 // save ch6 init value
2639 u16ValidSwing2 = (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0B_L, 0x3F00)>>8);
2640 //3. set Desired Pairs: GCR_ICON[5:0]=6h3f (current all open);
2641 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, 0x3F));
2642 //4. set Desired Pairs: GCR_PE_ADJ[2:0]=3h7 (pre-emphasis current all open )
2643 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x07);
2644 //5. Enable low-power modeinternal termination Open, Enable OP
2645 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 1);
2646
2647 MsOS_DelayTask(1);
2648
2649 //6. Enable low-power modeinternal termination Open, Enable OP
2650 MHal_Output_LVDS_Pair_Setting(pInstance,
2651 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
2652 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
2653 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
2654 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2655 MHal_Shift_LVDS_Pair(pInstance, pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift);
2656
2657 //7. set Desired Pairs: GCR_PE_ADJ[2:0]=3¡¦h0 (pre-emphasis current all Close)
2658 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x00);
2659 //8. set Desired Pairs: GCR_ICON[5:0] (current all init);
2660 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, u16ValidSwing2));
2661 //9. Disable low-power modeinternal termination Close, Disable OP
2662 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 0);
2663
2664 // other TTL setting
2665 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/ PANEL_miniLVDS/ PANEL_RSDS
2666
2667 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000);
2668 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2669 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F);
2670
2671 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew
2672
2673 // GPO gating
2674 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating
2675
2676 break;
2677 }
2678 }
2679
2680 // MHal_PNL_Bringup(pInstance);
2681 }
2682
Mhal_PNL_Flock_LPLLSet(void * pInstance,MS_U64 ldHz)2683 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz)
2684 {
2685 UNUSED(ldHz);
2686 }
2687
MHal_PNL_MISC_Control(void * pInstance,MS_U32 u32PNL_MISC)2688 void MHal_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC)
2689 {
2690 if(u32PNL_MISC & E_DRVPNL_MISC_MFC_ENABLE)
2691 {
2692 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair
2693 }
2694 }
2695
MHal_PNL_Init_XC_Clk(void * pInstance,PNL_InitData * pstPanelInitData)2696 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData)
2697 {
2698 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2699 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2700 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2701 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2702
2703 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2704
2705 // setup output dot clock
2706 if (pstPanelInitData->eLPLL_Type == E_PNL_TYPE_TTL)
2707 {
2708 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2709 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2710 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2711 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL clock div, TTL:DIV2
2712
2713 W2BYTEMSK(REG_RVD_44_L, 0x0004, 0x001F); //[4:0]reg_ckg_clk_misc
2714 W2BYTEMSK(L_CLKGEN0(0x58), 0x0001, 0x000F); //[3:0]ckg_tx_mod
2715 }
2716 else if ((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_LVDS) && ((pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE)))
2717 {
2718 // 1366x768, 1CH LVDS case
2719 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2720 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2721 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2722 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL clock div, TTL:DIV2
2723
2724 W2BYTEMSK(REG_RVD_44_L, 0x0004, 0x001F); //[4:0]reg_ckg_clk_misc
2725 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod
2726 }
2727 else
2728 {
2729 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock
2730 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock
2731 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out
2732 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div
2733
2734 W2BYTEMSK(REG_RVD_44_L, 0x000C, 0x001F); //[4:0]reg_ckg_clk_misc
2735 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod
2736 }
2737
2738 // reg_ckg_odclk_mft
2739 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_MFT_GATED); // [8] disable clock
2740 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_MFT_INVERT); // [9] invert clock
2741 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_MFT_SEL_LPLL, CKG_ODCLK_MFT_SEL_SOURCE); // [10] select source tobe LPLL clock, 0:synthetic clock out, 1:LPLL clock out // 0:synthetic clock out, 1:LPLL clock out
2742 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_MFT_XTAL, CKG_ODCLK_MFT_MASK); // [12:11] LPLL clock div
2743
2744 W2BYTE(L_CLKGEN1(0x31), 0x0000); //[11:8]ckg_odclk_frc
2745
2746 W2BYTEMSK(REG_RVD_43_L, 0x0400,0x0F00); //for scaler tgen
2747
2748 if( IsVBY1(pstPanelInitData->eLPLL_Type) )
2749 {
2750 W2BYTEMSK(REG_CLKGEN0_57_L, 0x000C, 0x000F); //[3:0]ckg_fifo
2751 W2BYTE(REG_RVD_09_L, 0x0800); //[13:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2752 //W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc
2753 W2BYTEMSK(L_CLKGEN0(0x56),0x0010, 0x00F0); //[7:4]reg_ckg_odclk_a
2754 W2BYTE(L_CLKGEN0(0x63),0x1001); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod
2755
2756 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
2757 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
2758 {
2759 W2BYTE(L_CLKGEN0(0x5A),0x0800); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
2760 }
2761 else if ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
2762 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
2763 {
2764 W2BYTE(L_CLKGEN0(0x5A),0x0900); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
2765 }
2766 else
2767 {
2768 W2BYTE(L_CLKGEN0(0x5A),0x0A00); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
2769 }
2770 }
2771 else
2772 {
2773
2774 if (pstPanelInitData->eLPLL_Type == E_PNL_TYPE_TTL)
2775 {
2776 W2BYTEMSK(REG_CLKGEN0_57_L, 0x0001, 0x000F); //[3:0]ckg_fifo
2777 W2BYTEMSK(L_CLKGEN0(0x56),0x0040, 0x00F0); //[7:4]reg_ckg_odclk_a
2778 W2BYTE(L_CLKGEN0(0x63),0x1101); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod
2779 }
2780 else if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2781 {
2782 W2BYTE(L_CLKGEN0(0x63),0x1000); //[7:4]reg_ckg_odclk_a
2783 W2BYTEMSK(REG_CLKGEN0_57_L, 0x000C, 0x000F); //[3:0]ckg_fifo
2784 W2BYTEMSK(L_CLKGEN0(0x56),0x0000, 0x000F); //[7:4]reg_ckg_odclk_a
2785 }
2786 else
2787 {
2788 W2BYTEMSK(L_CLKGEN0(0x56),0x0010, 0x00F0); //[7:4]reg_ckg_odclk_a
2789 W2BYTEMSK(REG_CLKGEN0_57_L, 0x0000, 0x000F); //[3:0]ckg_fifo
2790 W2BYTEMSK(L_CLKGEN0(0x63),0x0001, 0x00FF); //[7:4]reg_ckg_odclk_a
2791 }
2792
2793 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
2794 {
2795 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+
2796 }
2797 else if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2798 {
2799 W2BYTE(REG_RVD_09_L, 0x0800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2800 }
2801 else
2802 {
2803 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2804 }
2805 }
2806
2807 if( (E_PNL_TYPE_TTL == pstPanelInitData->eLPLL_Type)||
2808 ((E_PNL_TYPE_LVDS == pstPanelInitData->eLPLL_Type)&&(E_PNL_MODE_SINGLE==pstPanelInitData->eLPLL_Mode))||
2809 ((E_PNL_TYPE_HS_LVDS == pstPanelInitData->eLPLL_Type)&&(E_PNL_MODE_SINGLE==pstPanelInitData->eLPLL_Mode)))
2810 {
2811 //set LPLL mux
2812 W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0_reserved0[7:2]
2813 //[0] : diable clock
2814 //[1] : invert clock
2815 //[4:2] : xx0 : floclk_odclk_synth_out
2816 // 011 / 111: LPLL output clock
2817 }
2818 else
2819 {
2820 //set LPLL mux
2821 W2BYTEMSK(L_CLKGEN0(0x7E), 0x0030, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_clkgen0_reserved0[7:2]
2822 //[0] : diable clock
2823 //[1] : invert clock
2824 //[4:2] : xx0 : floclk_odclk_synth_out
2825 // 011 / 111: LPLL output clock
2826 }
2827
2828 if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2829 {
2830 W2BYTEMSK(REG_CHIP_50_L, 0x000F, 0x000F);
2831 }
2832 }
2833
2834 #define OUTPUT_CHANNEL_PART_A 0x0055 // CH0~3
2835 #define OUTPUT_CHANNEL_PART_B 0x5500 // CH4~7
2836 #define OUTPUT_CHANNEL_PART_C 0x0015 // CH8~10
2837 #define OUTPUT_CHANNEL_PART_D 0x0540 // CH11~13
2838 #define OUTPUT_CHANNEL_ALL 0x5555
2839
MHal_PNL_Init_MOD(void * pInstance,PNL_InitData * pstPanelInitData)2840 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData)
2841 {
2842 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2843 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2844 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2845 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2846
2847 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2848
2849 //------------------------------------------------------------------------
2850
2851 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL0 = %x\n", pstPanelInitData->u16MOD_CTRL0);
2852 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL9 = %x\n", pstPanelInitData->u16MOD_CTRL9);
2853 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRLA = %x\n", pstPanelInitData->u16MOD_CTRLA);
2854 PNL_DBG(PNL_DBGLEVEL_INIT, "u8MOD_CTRLB = %x\n", pstPanelInitData->u8MOD_CTRLB);
2855
2856 //-------------------------------------------------------------------------
2857 // Set MOD registers
2858 //-------------------------------------------------------------------------
2859
2860 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK);
2861
2862 // GPIO is controlled in drvPadConf.c
2863 // MDrv_Write2Byte(L_BK_MOD(0x46), 0x0000); //EXT GPO disable
2864 // MDrv_Write2Byte(L_BK_MOD(0x47), 0x0000); //EXT GPO disable
2865 if(IsVBY1(pstPanelInitData->eLPLL_Type_Ext))
2866 {
2867 //0x1032, h27, [14] = 0x0 //disable Vsync/Hsync/VFDE signal align by Time Slot vld
2868 //0x1032, h27, [13:8] = 0xF //valid wrap counter for fix htt to times of lanes
2869 //Register setting is recommand by HW RD Roy.Yeh (For Mooney boot logo shake with SEC panel issue)
2870 MOD_W2BYTEMSK(REG_MOD_BK00_27_L, 0x0F00, 0x3F00);
2871
2872 ///u16MOD_CTRL9 [6] : 62[9]reg_vby1_pair_swap
2873 ///u16MOD_CTRL9 [12:11] : 62[5:4]reg_vby1_pair_mirror
2874 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2875
2876 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9));
2877 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|BIT(4));
2878
2879 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2880 {
2881 if(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
2882 {
2883 // 2 divison just be supported in monet vby1 8 lane
2884 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2885 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode
2886
2887 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value
2888 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize
2889 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len
2890 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage
2891 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask
2892 }
2893 else
2894 {
2895 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode
2896 }
2897 }
2898 else
2899 {
2900 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2901 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x0000, 0xFFFF); //[11:0]reg_dly_value
2902 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007); //[2:0]reg_mft_mode
2903 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFFFF); //[2:0]reg_sram_usage
2904 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask
2905 }
2906
2907 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(14), BIT(14)); //[14]:reg_lockn_to_acq
2908 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0003, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv
2909
2910 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
2911 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1
2912 else
2913 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1
2914
2915
2916 ///u16MOD_CTRL9 [7] : 63[13]reg_vby1_pair_swap_osd
2917 ///u16MOD_CTRL9 [14:13] : 63[11:10]reg_vby1_pair_mirror2
2918 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13));
2919 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|BIT(10));
2920
2921 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
2922 {
2923 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1
2924
2925 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
2926 {
2927 // 2 Divisoin
2928 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2
2929 }
2930 else
2931 {
2932 // 1 Division
2933 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2
2934 }
2935 }
2936 else //if ///E_PNL_LPLL_VBY1_10BIT_4LANE, E_PNL_LPLL_VBY1_10BIT_2LANE
2937 {
2938 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(12)); // [12] enable 8ch vx1 mode : 0
2939 }
2940
2941 MHal_Output_Channel_Order(pInstance,
2942 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2943 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2944 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2945 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2946 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2947
2948
2949 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2950 {
2951 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2952 }
2953 else
2954 {
2955 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2956 }
2957
2958 ////per RD's suggestion ---Start
2959 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, 0xFFFF, 0xFFFF); //reg_gcr_pe_en_ch
2960 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //reg_gcr_en_rint_ch
2961 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //reg_gcr_test_ch
2962
2963 ////per RD's suggestion, for VBY1 channel skew
2964 MOD_A_W2BYTE(REG_MOD_A_BK00_02_L, 0x4444); //Fine tune skew for channel 0~7
2965 MOD_A_W2BYTE(REG_MOD_A_BK00_03_L, 0x4444); //Fine tune skew for channel 8~15
2966
2967 /// reg_gcr_pe_adj ch0~ch15
2968 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x0202);
2969 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x0202);
2970 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x0202);
2971 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x0202);
2972 MOD_A_W2BYTE(REG_MOD_A_BK00_1C_L,0x0202);
2973 MOD_A_W2BYTE(REG_MOD_A_BK00_1D_L,0x0202);
2974 MOD_A_W2BYTE(REG_MOD_A_BK00_1E_L,0x0202);
2975 MOD_A_W2BYTE(REG_MOD_A_BK00_1F_L,0x0202);
2976
2977 /// reg_gcr_vby1_vreg
2978 MOD_A_W2BYTE(REG_MOD_A_BK00_20_L,0x4444);
2979 MOD_A_W2BYTE(REG_MOD_A_BK00_21_L,0x4444);
2980 MOD_A_W2BYTE(REG_MOD_A_BK00_22_L,0x4444);
2981 MOD_A_W2BYTE(REG_MOD_A_BK00_23_L,0x4444);
2982
2983 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x80E8, 0xFFFF); //[0]:reg_vby1_8v4o_mode
2984
2985 //The threshold value be set too strict ( ori: MOD_5C =0x0 )
2986 //And this reg should be set before enable serializer function
2987 //[15]reg_sw_rptr_fix_en: pointer fix by sw mode enable
2988 //[14:12]reg_sw_wptr_check: sw mode to decision write point check point
2989 //[10:8]reg_sw_rptr_fix_ini: sw mode to decision read point initial value
2990 //[6:4]reg_sw_rptr_fix_hi_th: sw mode to decision read pointer hi boundary
2991 //[2:0]reg_sw_rptr_fix_lo_th: sw mode to decision read pointer low boundary
2992 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF);
2993 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF);
2994
2995 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
2996 //[1]enable serializer auto fix read/write point mis-balance
2997 //[2]enable osd serializer auto fix read/write point mis-balance
2998 //[7]for OSD, switch chanel 8~13 as OSD path
2999 }
3000 else
3001 {
3002 // non-VBY1 case
3003 MOD_W2BYTE(REG_MOD_BK00_49_L, pstPanelInitData->u16MOD_CTRL9); //{L_BK_MOD(0x49), 0x00}, // [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit, bit shift
3004 MHal_Output_Channel_Order(pInstance,
3005 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
3006 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
3007 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
3008 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
3009 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
3010 }
3011
3012 MOD_W2BYTE(REG_MOD_BK00_4A_L, pstPanelInitData->u16MOD_CTRLA);
3013 MOD_W2BYTE(REG_MOD_BK00_4B_L, pstPanelInitData->u8MOD_CTRLB); //[1:0]ti_bitmode 10:8bit 11:6bit 0x:10bit
3014
3015 #if 0 // no need this for Maxim 23x23 8V case
3016 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, (_u8PnlDiffSwingLevel << 1), 0xFE); //differential output swing level
3017 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
3018 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
3019 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000, 0xF000); //bank selection for skew clock
3020 #endif
3021
3022 //if(!MHal_PNL_MOD_Control_Out_Swing(_u8PnlDiffSwingLevel))
3023 // printf(">>Swing Level setting error!!\n");
3024 if(pstPanelInitData->eLPLL_Type != E_PNL_TYPE_MINILVDS)
3025 {
3026 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07);
3027 }
3028
3029 //// Patch for Vx1 and it should be control by panel ini
3030 if( IsVBY1(pstPanelInitData->eLPLL_Type_Ext) )
3031 {
3032 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, 0x0FFF, 0x3FFF);
3033 }
3034 else
3035 {
3036 MOD_A_W2BYTE(REG_MOD_A_BK00_31_L, pstPanelInitData->u16LVDSTxSwapValue);
3037 }
3038
3039
3040 // TODO: move from MDrv_Scaler_Init(), need to double check!
3041 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0));
3042
3043
3044 //--------------------------------------------------------------
3045 //Depend On Bitmode to set Dither
3046 //--------------------------------------------------------------
3047
3048
3049 // always enable noise dither and disable TAILCUT
3050 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, ((pstPanelInitData->u8PanelNoiseDith ? XC_PAFRC_DITH_NOISEDITH_EN : (1 - XC_PAFRC_DITH_NOISEDITH_EN)) <<3) , BIT(3));
3051 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, XC_PAFRC_DITH_TAILCUT_DISABLE, BIT(4));
3052
3053 switch(pstPanelInitData->u8MOD_CTRLB & 0x03)//[1:0]ti_bitmode b'10:8bit 11:6bit 0x:10bit
3054 {
3055 case HAL_TI_6BIT_MODE:
3056 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
3057 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(2), BIT(2));
3058 break;
3059
3060 case HAL_TI_8BIT_MODE:
3061 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
3062 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
3063 break;
3064
3065 case HAL_TI_10BIT_MODE:
3066 default:
3067 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(0));
3068 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
3069 break;
3070 }
3071
3072
3073 //-----depend on bitmode to set Dither------------------------------
3074 MHal_PNL_SetOutputType(pInstance, pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type); // TTL to Ursa
3075
3076 //dual port lvds _start_//
3077 // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
3078 if (IsVBY1(pstPanelInitData->eLPLL_Type_Ext))
3079 {
3080 MS_U16 u16ChannelClk_En = BIT(0); // bit0 is en_clk
3081 MS_U16 u16OutputCFG0_7 = OUTPUT_CHANNEL_ALL, u16OutputCFG8_15 = OUTPUT_CHANNEL_ALL;
3082 if(pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type == LVDS_OUTPUT_User)
3083 {
3084 u16OutputCFG0_7 = pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7;
3085 u16OutputCFG8_15 = pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15;
3086 }
3087
3088 if(u16OutputCFG0_7 & OUTPUT_CHANNEL_PART_A)
3089 u16ChannelClk_En |= BIT(1); //bit1: partA - ch0~3
3090 if(u16OutputCFG0_7 & OUTPUT_CHANNEL_PART_B)
3091 u16ChannelClk_En |= BIT(2); //bit2: partB - ch4~7
3092 if(u16OutputCFG8_15 & OUTPUT_CHANNEL_PART_C)
3093 u16ChannelClk_En |= BIT(3); //bit3: partC - ch8~10
3094 if(u16OutputCFG8_15 & OUTPUT_CHANNEL_PART_D)
3095 u16ChannelClk_En |= BIT(4); //bit4: partD - ch11~13
3096
3097 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u16ChannelClk_En, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck // original is MDrv_WriteByteMask(L_BK_MOD(0x77), 0x0F, BITMASK(7:2));
3098 }
3099 else
3100 {
3101 // LVDS
3102 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck // original is MDrv_WriteByteMask(L_BK_MOD(0x77), 0x0F, BITMASK(7:2));
3103 }
3104 //dual port lvds _end_//
3105 //MHal_PNL_Bringup(pInstance);
3106
3107 MHal_PNL_MISC_Control(pInstance, pstPanelInitData->u32PNL_MISC);
3108
3109 PNL_DBG(PNL_DBGLEVEL_INIT, "OutputType = %x, eLPLL_Type = %x\n", pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type);
3110 PNL_DBG(PNL_DBGLEVEL_INIT, "u32PNL_MISC = %tx\n", (ptrdiff_t)pstPanelInitData->u32PNL_MISC);
3111
3112 }
3113
MHal_PNL_DumpMODReg(void * pInstance,MS_U32 u32Addr,MS_U16 u16Value,MS_BOOL bHiByte,MS_U16 u16Mask)3114 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask)
3115 {
3116 if (bHiByte)
3117 {
3118 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
3119 }
3120 else
3121 {
3122 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask);
3123 }
3124 }
3125
MHal_MOD_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)3126 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
3127 {
3128 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3129 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3130 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3131 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3132 // Setup the default swing level
3133 pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel = pstModCaliInitData->u16ExpectSwingLevel; //mv
3134 #if 0
3135 // Pair setting
3136 // =========
3137 // Select calibration source pair, 00: ch2, 01: ch6, 10:ch8, 11:ch12
3138 //MOD_7D_L[3:2]
3139 // =========
3140 //in msModCurrentCalibration, it will transfer to the real data
3141
3142 switch(pstModCaliInitData->u8ModCaliPairSel)
3143 {
3144 default:
3145 case 0:
3146 //ch 2
3147 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x00; // ch2
3148 break;
3149 case 1:
3150 //ch 6
3151 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x01; // ch6, calibration initialized value
3152 break;
3153 case 2:
3154 //ch 8
3155 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x02;
3156 break;
3157 case 3:
3158 //ch 12
3159 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x03;
3160 break;
3161 }
3162 #endif
3163 // Target setting
3164 // =========
3165 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
3166 // =========
3167 //in msModCurrentCalibration, it will transfer to the real data
3168 switch(pstModCaliInitData->u8ModCaliTarget)
3169 {
3170 default:
3171 case 0:
3172 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 0;
3173 break;
3174 case 1:
3175 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 1;
3176 break;
3177 case 2:
3178 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 2;
3179 break;
3180 case 3:
3181 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 3;
3182 break;
3183 }
3184 // Offset setting, for fine tune
3185 //_usMOD_CALI_OFFSET = pstModCaliInitData->s8ModCaliOffset;
3186 // _u8MOD_CALI_VALUE is a real value; the _u8MOD_CALI_VALUE is an idea value
3187 // Target value should be the same with _u8MOD_CALI_VALUE to be a default value
3188 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE= pstModCaliInitData->u8ModCaliTarget;
3189 // PVDD setting
3190 pPNLResourcePrivate->sthalPNL._bPVDD_2V5 = pstModCaliInitData->bPVDD_2V5;
3191
3192 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
3193 PNL_DBG(PNL_DBGLEVEL_INIT, "u16ExpectSwingLevel = %u\n", pstModCaliInitData->u16ExpectSwingLevel);
3194 PNL_DBG(PNL_DBGLEVEL_INIT, "u8ModCaliTarget = %x\n", pstModCaliInitData->u8ModCaliTarget);
3195 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_TARGET = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET);
3196 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_VALUE = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE);
3197 PNL_DBG(PNL_DBGLEVEL_INIT, "bPVDD_2V5 = %x\n", pstModCaliInitData->bPVDD_2V5);
3198
3199 }
3200
MHal_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)3201 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type)
3202 {
3203 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3204 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3205 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3206 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3207 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
3208 {
3209 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift = LVDS_DUAL_OUTPUT_SPECIAL;
3210 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = 1;
3211 }
3212 else
3213 {
3214 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = Type;
3215 }
3216 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
3217 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_LVDS_Pair_Type = %u\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
3218
3219 }
3220
msModCalDDAOUT(void)3221 MS_BOOL msModCalDDAOUT(void)
3222 {
3223 // W2BYTEMSK(BK_MOD(0x7D), ENABLE, 8:8);
3224 // MsOS_DelayTask(10); //10ms
3225 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_A_BK00_74_L, BIT(8))) >> 8);
3226 }
3227
msModCurrentCalibration(void * pInstance)3228 MS_U8 msModCurrentCalibration(void *pInstance)
3229 {
3230 #if MOD_CAL_TIMER
3231 MS_U32 delay_start_time;
3232 delay_start_time=MsOS_GetSystemTime();
3233 #endif
3234
3235 #if (!ENABLE_Auto_ModCurrentCalibration)
3236 return 0x60;
3237 #else
3238 MS_U8 u8cur_ibcal=0;
3239 MS_U16 u16reg_32da = 0, u16reg_32dc = 0;
3240 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3241 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3242 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3243 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3244 u16reg_32da = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3245 u16reg_32dc = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3246
3247 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s][%d]\n", __FUNCTION__, __LINE__);
3248
3249 // (1) Set keep mode to auto write calibration result into register.
3250 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15));
3251
3252 // (2) Set calibration step waiting time
3253 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0x0080); // (about 5us)
3254 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, 0x00FF);
3255
3256 // (3) Set calibration toggle time
3257 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00);
3258
3259 // (4) Select calibration level (LVDS is 250mV)
3260 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(1)|BIT(0)); // Select calibration target voltage, 00: 250mV, 01:350mV, 10: 300mV, 11: 200mV
3261
3262 // (5) Enable Calibration mode
3263 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function
3264
3265 // (6) Store output configuration value and Enable each pair test mode
3266 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0xFFFF);
3267 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0FFF);
3268
3269 MS_U8 u8CheckTimes = 0;
3270 while(1)
3271 {
3272 // (7) Enable Hardware calibration
3273 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, BIT(15), BIT(15));
3274
3275 // (8) Wait 2ms
3276 MsOS_DelayTask(2);
3277
3278 // (10) Disable Hardware calibration
3279 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_73_L, 0x00, BIT(15));
3280
3281 // (9)Check Finish and Fail flag bit
3282 //BK111E, 0x73[14], Finish flag=1
3283 //BK111E, 0x73[13], Fail flag=0
3284 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_73_L, 0x6000) == 0x4000)
3285 {
3286 //printf("\033[0;31m [%s][%d] cal ok, break \033[0m\n", __FUNCTION__, __LINE__);
3287 break;
3288 }
3289 else
3290 {
3291 u8CheckTimes ++;
3292 //printf("\033[0;31m [%s][%d] cal ng, u8CheckTimes: %d \033[0m\n", __FUNCTION__, __LINE__, u8CheckTimes);
3293 }
3294
3295 if (u8CheckTimes > 3)
3296 {
3297 // (13) If 3 times all fail, set all pair to nominal value by disable keep mode
3298 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15));
3299 //printf("\033[0;31m [%s][%d] If 3 times all fail, set all pair to nominal value by disable keep mode \033[0m\n", __FUNCTION__, __LINE__);
3300 break;
3301 }
3302 }
3303
3304 if (u8CheckTimes <=3)
3305 {
3306 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration ok \n");
3307 }
3308 else
3309 {
3310 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration fail: 0x%x \n", MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000));
3311 }
3312
3313 // Wait 2ms to make sure HW auto write calibration result into register
3314 MsOS_DelayTask(2);
3315
3316 // (14) Restore each pair output configuration
3317 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16reg_32da);
3318 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16reg_32dc);
3319
3320 // (15) Disable calibration mode
3321 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Disable calibration function
3322
3323 // With HW calibration mode, HW would cal for each channel, and each channel would get different value
3324 // Return channel 2 vaule
3325 u8cur_ibcal = MOD_A_R2BYTEMSK(REG_MOD_A_BK00_09_L, 0x007F); // return ch2 calibration result
3326
3327 #if MOD_CAL_TIMER
3328 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s] takes %ld ms\n", __FUNCTION__, (MsOS_GetSystemTime()-delay_start_time));
3329 #endif
3330 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n Calibration result= %x\n", u8cur_ibcal);
3331
3332 return (u8cur_ibcal&0x7F);//MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0D_L, 0x003F);
3333 #endif
3334 }
3335
MHal_PNL_MOD_Calibration(void * pInstance)3336 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance)
3337 {
3338 MS_U8 u8Cab;
3339 MS_U8 u8BackUSBPwrStatus;
3340 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3341 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3342 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3343 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3344
3345 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
3346
3347 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
3348
3349 u8Cab = msModCurrentCalibration(pInstance);
3350
3351 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
3352
3353 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type !=E_PNL_TYPE_MINILVDS)
3354 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07);
3355
3356 return E_PNL_OK;
3357
3358 }
3359
MHal_PNL_PowerDownLPLL(void * pInstance,MS_BOOL bEnable)3360 static void MHal_PNL_PowerDownLPLL(void *pInstance, MS_BOOL bEnable)
3361 {
3362 if(bEnable)
3363 {
3364 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5));
3365 }
3366 else
3367 {
3368 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5));
3369 }
3370 }
3371
MHal_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)3372 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn)
3373 {
3374 MS_U8 u8Cab;
3375 MS_U8 u8BackUSBPwrStatus;
3376 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3377 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3378 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3379 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3380
3381 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "[%s][%d]\n", __FUNCTION__, __LINE__);
3382
3383 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u32PNL_MISC = %tx\n", (ptrdiff_t)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC);
3384 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "bPanelOn = %x\n", bPanelOn);
3385 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "eLPLL_Type = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type);
3386 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "_u8MOD_LVDS_Pair_Type = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
3387 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
3388 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
3389 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3390
3391 MS_U16 u16PortA = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3392 MS_U16 u16PortB = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3393
3394 if((u16PortA!=0)||(u16PortB!=0))
3395 {
3396 MHal_BD_LVDS_Output_Type(pInstance, LVDS_OUTPUT_User);
3397 }
3398
3399 if(u16PortA!=0)
3400 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3401 if(u16PortB!=0)
3402 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3403
3404 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "==========================\n\n");
3405 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
3406 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
3407 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3408
3409
3410 if(bPanelOn)
3411 {
3412 // The order is PanelVCC -> delay pnlGetOnTiming1() -> VOP -> MOD
3413 // VOP
3414 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x4000, HBMASK);
3415
3416 // For Napoli compatible
3417 // need to wait 1ms to wait LDO stable before MOD power on
3418 MsOS_DelayTask(1);
3419
3420 // turn on LPLL
3421 MHal_PNL_PowerDownLPLL(pInstance, FALSE);
3422
3423 if(pPNLResourcePrivate->stapiPNL.ePrevPowerState != E_POWER_RESUME)
3424 {
3425 // for LG panel black video
3426 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, DISABLE);
3427 }
3428
3429 // mod power on
3430 MHal_MOD_PowerOn(pInstance
3431 , ENABLE
3432 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
3433 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
3434 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
3435 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
3436 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3437
3438 if(bCalEn)
3439 {
3440
3441 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
3442
3443 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
3444
3445 u8Cab = msModCurrentCalibration(pInstance);
3446
3447 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
3448
3449 }
3450 else
3451 {
3452 if( ( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) ) &&
3453 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE) == FALSE))
3454 {
3455 HAL_MOD_CAL_DBG(printf("Use RCON value \n", __FUNCTION__, __LINE__));
3456 msSetVBY1RconValue(pInstance);
3457 }
3458 else
3459 {
3460 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
3461
3462 if(!MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel))
3463 printf(">>Swing Level setting error!!\n");
3464 }
3465 }
3466
3467 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
3468 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, ENABLE);
3469 }
3470 else
3471 {
3472 // The order is LPLL -> MOD -> VOP -> delay for MOD power off -> turn off VCC
3473
3474 // LPLL
3475 // MHal_PNL_PowerDownLPLL(TRUE); //Remove to keep op vsync if panel off
3476
3477 MHal_MOD_PowerOn(pInstance
3478 , DISABLE
3479 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
3480 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
3481 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
3482 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
3483 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3484 // VOP
3485 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS ||
3486 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_I ||
3487 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_P)//(bIsLVDS)
3488 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0xFF, LBMASK);
3489 else
3490 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x00, 0xFF);
3491 }
3492
3493 return E_PNL_OK;
3494 }
3495
MHal_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)3496 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
3497 {
3498 if (bEnable)
3499 {
3500 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF);
3501 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF);
3502 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF);
3503 MsOS_DelayTask(10);
3504 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15));
3505 }
3506 else
3507 {
3508 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15));
3509 }
3510
3511 }
3512
MHal_PNL_Switch_LPLL_SubBank(void * pInstance,MS_U16 u16Bank)3513 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank)
3514 {
3515 UNUSED(u16Bank);
3516 }
3517
MHal_PNL_Switch_TCON_SubBank(void * pInstance,MS_U16 u16Bank)3518 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank)
3519 {
3520 W2BYTEMSK(L_BK_TCON(0x00), u16Bank&0xff, 0xFF);
3521 }
3522
MHal_PNL_Read_TCON_SubBank(void * pInstance)3523 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance)
3524 {
3525 return (MS_U16)R2BYTEMSK(L_BK_TCON(0x00),0xFF);
3526 }
3527
MHal_PNL_Is_VBY1_Locked(void * pInstance)3528 MS_BOOL MHal_PNL_Is_VBY1_Locked(void *pInstance)
3529 {
3530 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0300) == 0x00)
3531 {
3532 return TRUE;
3533 }
3534 else
3535 {
3536 return FALSE;
3537 }
3538 }
3539
MHal_PNL_Is_VBY1_LockN_Locked(void * pInstance)3540 MS_BOOL MHal_PNL_Is_VBY1_LockN_Locked(void *pInstance)
3541 {
3542 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0100) == 0x00)
3543 {
3544 return TRUE;
3545 }
3546 else
3547 {
3548 return FALSE;
3549 }
3550 }
3551
MHal_PNL_VBY1_Handshake(void * pInstance)3552 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance)
3553 {
3554 MS_BOOL bIsLock = FALSE;
3555
3556 if (MHal_PNL_Is_VBY1_Locked(pInstance) == FALSE)
3557 {
3558 MS_U16 u16CheckTimes = 0;
3559 //MS_U16 u16DeboundTimes = 0;
3560
3561 // need to toggle vby1 packer process start first
3562 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11));
3563 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11));
3564
3565 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value
3566 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by
3567 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition
3568 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
3569 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance
3570
3571 while(u16CheckTimes < 10)
3572 {
3573 #if 0
3574 u16DeboundTimes = 2;
3575 while ((!MHal_PNL_Is_VBY1_LockN_Locked()) && (u16DeboundTimes --))
3576 {
3577 MsOS_DelayTask(1); // can't remove
3578 }
3579 #endif
3580 if(MHal_PNL_Is_VBY1_LockN_Locked(pInstance))
3581 {
3582 //-------------------------------------------------------------------
3583 // step1. Toggle clock when training
3584 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
3585 //--------------------------------------------------------------------
3586 bIsLock = TRUE;
3587 // pass 2 times debound to make sure VBY1 is locked
3588 break;
3589 }
3590
3591 u16CheckTimes++;
3592 MsOS_DelayTaskUs(40);
3593 }
3594
3595 if(bIsLock)
3596 {
3597 // step3. Disable HW check when lock done, Enable when loss lock
3598 //MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
3599
3600 /// Add the delay to increase time to send
3601 //MDrv_TIMER_Delayms(10);
3602 }
3603 }
3604 else
3605 {
3606 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE)
3607 {
3608 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
3609 }
3610 bIsLock = TRUE;
3611 }
3612
3613 return bIsLock;
3614 }
3615
MHal_PNL_Is_VBY1_OC_Locked(void * pInstance)3616 MS_BOOL MHal_PNL_Is_VBY1_OC_Locked(void *pInstance)
3617 {
3618 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0C00) == 0x00) // MOD_BK00_56_L[11:10] for OSD
3619 {
3620 return TRUE;
3621 }
3622 else
3623 {
3624 return FALSE;
3625 }
3626 }
3627
MHal_PNL_Is_VBY1_OC_LockN_Locked(void * pInstance)3628 MS_BOOL MHal_PNL_Is_VBY1_OC_LockN_Locked(void *pInstance)
3629 {
3630 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0400) == 0x00) // MOD_BK00_56_L[11:10] for OSD
3631 {
3632 return TRUE;
3633 }
3634 else
3635 {
3636 return FALSE;
3637 }
3638 }
3639
MHal_PNL_VBY1_OC_Handshake(void * pInstance)3640 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance)
3641 {
3642 MS_BOOL bIsLock = FALSE;
3643
3644 if (MHal_PNL_Is_VBY1_OC_Locked(pInstance) == FALSE)
3645 {
3646 MS_U16 u16CheckTimes = 0;
3647 // MS_U16 u16DeboundTimes = 0;
3648
3649 // need to toggle vby1 packer process start first
3650 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11));
3651 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11));
3652
3653
3654 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value
3655 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by
3656 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition
3657 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
3658 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance
3659
3660 while(u16CheckTimes < 10)
3661 {
3662 #if 0
3663 u16DeboundTimes = 2;
3664 while ((!MHal_PNL_Is_VBY1_OC_LockN_Locked()) && (u16DeboundTimes --))
3665 {
3666 MsOS_DelayTask(1);
3667 }
3668 #endif
3669 if(MHal_PNL_Is_VBY1_OC_LockN_Locked(pInstance))
3670 {
3671 //-------------------------------------------------------------------
3672 // step1. Toggle clock when training
3673
3674 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
3675 bIsLock = TRUE;
3676 // pass 2 times debound to make sure VBY1 is locked
3677 break;
3678 }
3679
3680 u16CheckTimes++;
3681 MsOS_DelayTaskUs(40);
3682 }
3683
3684 if(bIsLock)
3685 {
3686 // step3. Disable HW check when lock done, Enable when loss lock
3687 // MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
3688 }
3689 }
3690 else
3691 {
3692 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE)
3693 {
3694 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
3695 }
3696 bIsLock = TRUE;
3697 }
3698
3699 return bIsLock;
3700 }
3701
MHal_PNL_IsYUVOutput(void * pInstance)3702 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance)
3703 {
3704 return FALSE;
3705 }
3706
MHal_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)3707 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
3708 {
3709 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3710 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3711
3712 if (bEnable == TRUE)
3713 {
3714 //interlace output vtotal modify
3715 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9), BIT(9));
3716
3717 // two different interlace information through channel A reserved bit
3718 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7));
3719 // two different interlace information through channel B reserved bit
3720 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11));
3721 }
3722 else
3723 {
3724 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L , 0, BIT(9));
3725 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7));
3726 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11));
3727 }
3728
3729 return TRUE;
3730 }
3731
MHal_PNL_GetOutputInterlaceTiming(void * pInstance)3732 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance)
3733 {
3734 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3735 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3736
3737 MS_BOOL bIsInterlaceOutput = FALSE;
3738 //interlace output vtotal modify
3739 if (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9)) == BIT(9))
3740 {
3741 if ((MOD_R2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7)) == (BIT(4) | BIT(7)))
3742 || (MOD_R2BYTEMSK(REG_MOD_BK00_42_L, BIT(10) | BIT(11)) == (BIT(10)|BIT(11))))
3743 {
3744 bIsInterlaceOutput = TRUE;
3745 }
3746 }
3747 else
3748 {
3749 bIsInterlaceOutput = FALSE;
3750 }
3751 return bIsInterlaceOutput;
3752 }
3753
3754 ////Ext LPLL setting
_MHal_PNL_Init_ExtLPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)3755 static void _MHal_PNL_Init_ExtLPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
3756 {
3757 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3758
3759 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_OSD);
3760
3761 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3762 {
3763 printf("Not Supported LPLL Type, skip LPLL Init\n");
3764 return;
3765 }
3766
3767 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_OSD);
3768 }
3769
_MHal_PNL_Get_ExtLPLL_LoopDIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3770 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopDIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3771 {
3772 MS_U16 u16loop_div = 0;
3773 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3774 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3775
3776 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3777 {
3778 u16loop_div = 0 ;
3779 }
3780 else
3781 {
3782 u16loop_div = u16EXT_LoopDiv[u8SupportedLPLLLIndex];
3783 }
3784
3785 u16loop_div *= 2;
3786 return u16loop_div;
3787 }
3788
_MHal_PNL_Get_ExtLPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3789 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3790 {
3791 MS_U16 u16loop_gain = 0;
3792 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3793 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3794
3795 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3796 {
3797 u16loop_gain = 0 ;
3798 }
3799 else
3800 {
3801 u16loop_gain = u16EXT_LoopGain[u8SupportedLPLLLIndex];
3802 }
3803 return u16loop_gain;
3804 }
3805
3806
3807 // Output Dclk
MHal_PNL_CalExtLPLLSETbyDClk(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U64 ldHz)3808 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz)
3809 {
3810
3811 MS_U64 u64LdPllSet = 0;
3812 MS_U64 u64DclkFactor = 0;
3813 MS_U32 u32Div = 0;
3814 // loop div and loop gain use default parameters to avoid dclk floating out of range and getting wrong value
3815 MS_U32 u32Factor = 10;
3816
3817 _MHal_PNL_Init_ExtLPLL(pInstance, u8LPLL_Type, u8LPLL_Mode, ldHz);
3818
3819 //the first " *2 " is from the dual mode
3820 u32Div=(MS_U32)(_MHal_PNL_Get_ExtLPLL_LoopDIV(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3821 u64DclkFactor=((MS_U64)LVDS_MPLL_CLOCK_MHZ * (MS_U64)524288 * (MS_U64)_MHal_PNL_Get_ExtLPLL_LoopGain(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3822 u64LdPllSet = (u64DclkFactor * 1000000 * u32Factor *2) + ((ldHz * u32Div) >> 1);
3823 do_div(u64LdPllSet, ldHz);
3824 do_div(u64LdPllSet, u32Div);
3825
3826 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet);
3827 //printf("MHal_PNL_CalExtLPLLSETbyDClk u32KHz = %u, u32LpllSet = %x\n", ldHz, (MS_U32)u64LdPllSet);
3828
3829 }
3830
MHal_PNL_SetOSDCOutputType(void * pInstance,PNL_TYPE eLPLL_Type,E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)3831 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)
3832 {
3833 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3834 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3835 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3836 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3837
3838 // VBy1 co-registers
3839 if( IsVBY1(eLPLL_Type) )
3840 {
3841 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1008); //[3]enable osd lvds channel
3842 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
3843
3844 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x4000, 0xF000); //bank selection for skew clock
3845
3846 //-------------------------------------
3847 //## pe
3848 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
3849 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
3850 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
3851 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
3852
3853 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
3854
3855 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(14)); //[14]:reg_lockn_to_acq
3856 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv
3857
3858 W2BYTE(REG_CLKGEN0_63_L,0x1410); //[11:8] clk_tx_mod_osd, [4:0] osd2mod
3859 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
3860
3861 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x0001, 0x0001); //[0]:reg_vby1_8v4o_mode
3862 }
3863
3864 if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
3865 {
3866 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14),BIT(14)|BIT(15)); //[15]enskew_path2[14]enclk_path2[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3867 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0055); //[7:0]reg_output_conf[27:16]
3868 W2BYTE(L_CLKGEN0(0x5A),0x8800); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
3869
3870 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1000); //[12]sw_rst, [3]enable osd lvds channel
3871 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001F, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3872 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); //[3:0] reg_ckg_tx_mod
3873 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); //reg_ckg_dot
3874
3875 MOD_W2BYTE(REG_MOD_BK00_71_L, 0xffff);
3876 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
3877 //[1]enable serializer auto fix read/write point mis-balance
3878 //[2]enable osd serializer auto fix read/write point mis-balance
3879 //[7]for OSD, switch chanel 8~13 as OSD path
3880 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000);
3881 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330);
3882 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd320);
3883 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f);
3884 //-------------------------------------
3885 //## icon (Swing)
3886 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3887 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x7f7f);
3888 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3889
3890 // vby1 osd 4 lane
3891 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa260); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap
3892
3893 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // 2 Divisoin
3894 {
3895 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x6420);
3896 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7531);
3897 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
3898 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
3899 }
3900 else
3901 {
3902 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
3903 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
3904 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
3905 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
3906 }
3907 }
3908 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
3909 {
3910 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14) ,BIT(14)|BIT(15));
3911 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0005);
3912 W2BYTE(L_CLKGEN0(0x5A),0x9900); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode
3913 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x001B, 0x001F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3914 //-------------------------------------
3915 //## icon (Swing)
3916 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3917 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x0000);
3918 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3919
3920 //vby1 osd 2 lane
3921 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa240); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap[5]vby1_osd_4ch
3922
3923 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
3924 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
3925 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
3926 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
3927 }
3928
3929 // Control VBY1 output format and bit orders
3930 switch(eOC_OutputFormat)
3931 {
3932 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB1:
3933 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3934 break;
3935
3936 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB2:
3937 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1));
3938 break;
3939
3940 default:
3941 printf("OSDC output format uses default value\n");
3942 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3943 break;
3944 }
3945
3946
3947 }
3948
MHal_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)3949 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
3950 {
3951 MS_U16 u16Span;
3952 MS_U16 u16Step;
3953 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
3954
3955 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
3956 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
3957 // Set SPAN
3958 if(u16Fmodulation < 200 || u16Fmodulation > 400)
3959 u16Fmodulation = 300;
3960 u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) / ((MS_U32)u32PLL_SET) ) ;
3961
3962 // Set STEP
3963 if(u16Rdeviation > 300)
3964 u16Rdeviation = 300;
3965 u16Step = ((MS_U32)u32PLL_SET*u16Rdeviation) / ((MS_U32)u16Span*10000);
3966
3967 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP
3968 W2BYTE(L_BK_LPLL(0x4F), u16Span & 0x3FFF);// LPLL_SPAN
3969 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
3970
3971
3972 return TRUE;
3973 }
3974
MHal_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)3975 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
3976 {
3977 //printf("bEnable = %d\n", bEnable);
3978 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
3979 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
3980 }
3981
MHal_PNL_Set_T3D_Setting(void * pInstance)3982 void MHal_PNL_Set_T3D_Setting(void *pInstance)
3983 {
3984 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3985 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3986 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3987 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3988
3989 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_55_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x1FFF);//pixel width
3990 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_66_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
3991 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_51_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x1FFF);//reg_ln_width
3992 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_52_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
3993 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_61_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x3FFF);//reg_ln_width
3994 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_62_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
3995
3996 //per designer, should always enable t3d, since it will affect osd/video's pipeline
3997 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_61_L, BIT(0), BIT(0));//Enable Depth Render, for osd pipe line adjustment
3998 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_08_L, BIT(4), BIT(4));//mtv bypass mode
3999 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_57_L,(BIT(0)|BIT(1)),(BIT(0)|BIT(1)));//T3D fix subde enable, fix for T3D/PIP conflict issue (bit 0) Bug Fix miu eco (bit 1)
4000
4001 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
4002 }
4003
MHal_PNL_Set_Device_Bank_Offset(void * pInstance)4004 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance)
4005 {
4006 UNUSED(pInstance);
4007 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM);
4008 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg bank offset
4009 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg bank offset
4010 }
4011
MHal_PNL_Init(void * pInstance)4012 void MHal_PNL_Init(void *pInstance)
4013 {
4014 // Do nothing
4015 //UNUSED(pInstance);
4016 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
4017 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
4018
4019 // STGEN reset
4020 //SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK68_50_L, (BIT(0)|BIT(3)), (BIT(0)|BIT(3)) );
4021 }
4022
MHal_PNL_Bringup(void * pInstance)4023 void MHal_PNL_Bringup(void *pInstance)
4024 {
4025 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
4026 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
4027 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
4028 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
4029
4030 ///patch for bring up
4031 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
4032 {
4033 }
4034 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
4035 {
4036 }
4037
4038 }
4039
MHal_PNL_GetPanelVStart(void)4040 MS_U16 MHal_PNL_GetPanelVStart(void)
4041 {
4042 return 6;
4043 }
4044
MHal_PNL_Check_VBY1_Handshake_Status(void * pInstance)4045 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance)
4046 {
4047 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE)
4048 {
4049 //printf("VBY1 handshake return because the reg value is 0x%u, not 0xFAE.\n", MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF));
4050 return FALSE;
4051 }
4052 else
4053 {
4054 //printf("VBY handshake check success.\n");
4055 return TRUE;
4056 }
4057 }
4058
MHal_PNL_ChannelFIFOPointerADjust(void * pInstance)4059 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance)
4060 {
4061 // 0 to 1 then will do write and read point capture to
4062 // Read : REG_MOD_BK00_5F_L[14:12]
4063 // write : REG_MOD_BK00_5F_L[10:8]
4064 // it takes 3 ticks to capture and riu takes 5 ticks to write
4065 // so we don't have to do any delay between rising capture and
4066 // read/write pointer recognition
4067 MsOS_DelayTaskUs(500);
4068 MOD_A_W2BYTE(REG_MOD_A_BK00_5C_L, 0x3300);
4069
4070 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
4071 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
4072
4073 //split Video & OSD process start bit
4074 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
4075 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
4076 {
4077 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
4078 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
4079 }
4080
4081 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
4082 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
4083
4084 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
4085 MS_U16 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4086 MS_S8 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4087 MS_S8 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4088
4089 //OSD part
4090 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
4091 MS_U16 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4092 MS_S8 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4093 MS_S8 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4094
4095 MS_BOOL bOSDC = ((MOD_A_R2BYTE(REG_MOD_A_BK00_58_L)&0x00F0) == 0x0040)?TRUE:FALSE;
4096 while (((abs(u8WritePointer-u8ReadPointer) >4) && (abs(u8WritePointer-u8ReadPointer)<2))
4097 ||(((abs(OSDu8WritePointer-OSDu8ReadPointer) >4) && (abs(OSDu8WritePointer-OSDu8ReadPointer)<2))&&bOSDC))
4098 {
4099 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
4100 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
4101
4102 //split Video & OSD process start bit
4103 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
4104 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
4105 {
4106 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
4107 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
4108 }
4109
4110 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
4111 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
4112
4113 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
4114 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4115 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4116 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4117
4118 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
4119 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
4120 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
4121 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
4122 printf("bOSDC [%d]\n",bOSDC);
4123
4124 }
4125
4126 }
4127
MHal_PNL_VBY1_Hardware_TrainingMode_En(void * pInstance,MS_BOOL bIsVideoMode,MS_BOOL bEnable)4128 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable)
4129 {
4130 if(bIsVideoMode)
4131 {
4132 if(bEnable)
4133 {
4134 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE);
4135 }
4136 else
4137 {
4138 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AA6);
4139 }
4140 }
4141 else
4142 {
4143 if(bEnable)
4144 {
4145 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE);
4146 }
4147 else
4148 {
4149 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6);
4150 }
4151 }
4152 }
4153
MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void * pInstance)4154 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance)
4155 {
4156 #ifdef SUPPORT_VBY1_HWTRAINING_MODE
4157 return TRUE;
4158 #else
4159 return FALSE;
4160 #endif
4161 }
4162
MHal_PNL_TCON_Patch(void * pInstance)4163 void MHal_PNL_TCON_Patch(void* pInstance)
4164 {
4165 //tcon apply new tcon.bin in maxim
4166 //so change patch
4167 //step 1: enable param.
4168 //step 2: delay one vysnc
4169 //step 3: disable param.
4170 MS_U16 u16CurrentBank = 0;
4171 u16CurrentBank = MHal_PNL_Read_TCON_SubBank(pInstance);
4172
4173 MHal_PNL_Switch_TCON_SubBank(pInstance, 0x04);
4174 W2BYTEMSK(L_BK_TCON(0x50), BIT(1), BIT(1));
4175 MsOS_DelayTask(20);
4176 W2BYTEMSK(L_BK_TCON(0x50), 0, BIT(1));
4177 MHal_PNL_Switch_TCON_SubBank(pInstance, u16CurrentBank);
4178 }
4179
_Hal_MOD_External_eFuse(void)4180 static MS_BOOL _Hal_MOD_External_eFuse(void)
4181 {
4182 #ifdef MOD_EFUSE_IN_MBOOT
4183 return TRUE;
4184 #else
4185 return FALSE;
4186 #endif
4187 }
4188
4189 #endif
4190
4191