1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _HAL_PNL_C_
79 #define _HAL_PNL_C_
80
81 //-------------------------------------------------------------------------------------------------
82 // Include Files
83 //-------------------------------------------------------------------------------------------------
84
85 #include "MsCommon.h"
86 #include "MsTypes.h"
87 #include <string.h>
88 #include "utopia.h"
89 #include "utopia_dapi.h"
90 #include "apiPNL.h"
91 #include "apiPNL_v2.h"
92 #include "drvPNL.h"
93 #include "halPNL.h"
94 #include "PNL_private.h"
95 #include "drvPNL.h"
96 #include "halPNL.h"
97 #include "pnl_hwreg_utility2.h"
98 #include "Munich_pnl_lpll_tbl.h"
99
100 //-------------------------------------------------------------------------------------------------
101 // Driver Compiler Options
102 //-------------------------------------------------------------------------------------------------
103
104 //-------------------------------------------------------------------------------------------------
105 // Local Defines
106 //-------------------------------------------------------------------------------------------------
107
108 #define UNUSED(x) (x=x)
109 #if 1
110 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) printf("PNL:"_fmt, ##_args); }
111 #define HAL_MOD_CAL_DBG(x) //x
112 #else
113 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { }
114 #endif
115
116 #define DAC_LPLL_ICTRL 0x0002
117 #define LVDS_LPLL_ICTRL 0x0001
118
119 //Get MOD calibration time
120 #define MOD_CAL_TIMER FALSE
121
122 //-------------------------------------------------------------------------------------------------
123 // Local Structurs
124 //-------------------------------------------------------------------------------------------------
125
126 //-------------------------------------------------------------------------------------------------
127 // Global Variables
128 //-------------------------------------------------------------------------------------------------
129
130 //-------------------------------------------------------------------------------------------------
131 // Local Variables
132 //-------------------------------------------------------------------------------------------------
133
134 // Output swing = 150mV + Code * 10mV.
135 // Designer recommand value. 0x15 = 21 = 250mv
136 static MS_U16 _u16PnlDefault_SwingLevel = 250;
137 static PNL_OUTPUT_MODE _eDrvPnlInitOptions = E_PNL_OUTPUT_CLK_DATA;
138 MS_U8 _u8MOD_CALI_TARGET = 0; ///< MOD_REG(0x7D),[10:9]00: 250mV ,01: 350mV ,10:300mV ,11:200mV
139 MS_S8 _usMOD_CALI_OFFSET = 0; ///< MOD_REG(0x7D),[5:0]+ _usMOD_CALI_OFFSET
140 MS_U8 _u8MOD_CALI_VALUE = 0x15; /// Final value
141
142 MS_U8 _u8MOD_LVDS_Pair_Shift = 0; ///< 0:default setting, LVDS pair Shift
143 MS_U8 _u8MOD_LVDS_Pair_Type = 0; ///< 0:default setting, LVDS data differential pair
144 //-------------------------------------------------------------------------------------------------
145 // Debug Functions
146 //-------------------------------------------------------------------------------------------------
147
148 //-------------------------------------------------------------------------------------------------
149 // Local Functions
150 //-------------------------------------------------------------------------------------------------
151
152 //-------------------------------------------------------------------------------------------------
153 // Global Function
154 //-------------------------------------------------------------------------------------------------
155 /**
156 * @brief: Power On MOD. but not mutex protected
157 *
158 */
MHal_MOD_PowerOn(void * pInstance,MS_BOOL bEn,MS_U8 u8LPLL_Type,MS_U8 DualModeType,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)159 MS_U8 MHal_MOD_PowerOn(void *pInstance,MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
160 {
161 if( bEn )
162 {
163 MOD_W2BYTEMSK(REG_MOD_BK00_37_L, 0x00, BIT(8));
164
165 //analog MOD power down. 1: power down, 0: power up
166 // For Mod2 no output signel
167 ///////////////////////////////////////////////////
168
169 //2. Power on MOD (current and regulator)
170 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x00 , BIT(0) | BIT(7) );
171
172 //enable ib, enable ck
173 MOD_W2BYTEMSK(REG_MOD_BK00_77_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0)));
174
175 // clock gen of dot-mini
176 if(u8LPLL_Type == E_PNL_TYPE_MINILVDS)
177 {
178 MOD_W2BYTE(REG_MOD_BK00_20_L, 0x4400);
179 }
180 else
181 {
182 MOD_W2BYTE(REG_MOD_BK00_20_L, 0x0000);
183 }
184
185 // 3. 4. 5.
186 MHal_Output_LVDS_Pair_Setting(pInstance,DualModeType, u16OutputCFG0_7, u16OutputCFG8_15, u16OutputCFG16_21);
187
188 }
189 else
190 {
191 MOD_W2BYTEMSK(REG_MOD_BK00_37_L, BIT(8), BIT(8));
192 if(u8LPLL_Type !=E_PNL_TYPE_MINILVDS)
193 {
194 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x00, BIT(0)); //analog MOD power down. 1: power down, 0: power up
195 }
196
197 MOD_W2BYTEMSK(REG_MOD_BK00_77_L, 0, (BIT(1) | BIT(0) )); //enable ib, enable ck
198
199 // clock gen of dot-mini
200 MOD_W2BYTE(REG_MOD_BK00_20_L, 0x1100);
201 }
202
203 return 1;
204 }
205 /**
206 * @brief: Setup the PVDD power 1:2.5V, 0:3.3V
207 *
208 */
MHal_MOD_PVDD_Power_Setting(void * pInstance,MS_BOOL bIs2p5)209 void MHal_MOD_PVDD_Power_Setting(void *pInstance,MS_BOOL bIs2p5)
210 {
211 MOD_W2BYTEMSK(REG_MOD_BK00_37_L, ((bIs2p5)? BIT(6):0), BIT(6)); //MOD PVDD=1: 2.5,PVDD=0: 3.3
212 }
213
MHal_PNL_TCON_Init(void * pInstance)214 void MHal_PNL_TCON_Init(void *pInstance)
215 {
216
217 }
218
MHal_Shift_LVDS_Pair(void * pInstance,MS_U8 Type)219 void MHal_Shift_LVDS_Pair(void *pInstance,MS_U8 Type)
220 {
221 if(Type == 1)
222 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LVDS Mode3
223 else
224 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6)));
225
226 }
227
MHal_Output_LVDS_Pair_Setting(void * pInstance,MS_U8 Type,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)228 void MHal_Output_LVDS_Pair_Setting(void *pInstance,MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
229 {
230 // Disable OP
231 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, BIT(1) , BIT(1) );
232
233 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
234 {
235 // for 100/128 pin special case
236 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0x1000, 0xFF00);
237 MOD_W2BYTE(REG_MOD_BK00_6D_L, 0x5555);
238 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x0055);
239 MOD_W2BYTE(REG_MOD_BK00_6F_L, 0x0000);
240 }
241 else if(Type == LVDS_SINGLE_OUTPUT_A)
242 {
243 MOD_W2BYTEMSK(REG_MOD_BK00_6D_L, 0x0000, 0xF000);
244 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x5500);
245 MOD_W2BYTEMSK(REG_MOD_BK00_6F_L, 0x0005, 0x000F);
246 }
247 else if( Type == LVDS_SINGLE_OUTPUT_B)
248 {
249 MOD_W2BYTEMSK(REG_MOD_BK00_6D_L, 0x5000, 0xF000);
250 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x0055);
251 MOD_W2BYTEMSK(REG_MOD_BK00_6F_L, 0x0000, 0x000F);
252 }
253 else if( Type == LVDS_OUTPUT_User)
254 {
255 MOD_W2BYTE(REG_MOD_BK00_6D_L, u16OutputCFG0_7);
256 MOD_W2BYTE(REG_MOD_BK00_6E_L, u16OutputCFG8_15);
257 MOD_W2BYTEMSK(REG_MOD_BK00_6F_L, u16OutputCFG16_21, 0x000F);
258 }
259 else
260 {
261 MOD_W2BYTE(REG_MOD_BK00_6D_L, 0x5550);
262 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x0555);
263 MOD_W2BYTE(REG_MOD_BK00_6F_L, 0x0000);
264 }
265
266 MsOS_DelayTask(2);
267
268 // Enable OP
269 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x00 , BIT(1) );
270
271 }
272
MHal_Output_Channel_Order(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)273 void MHal_Output_Channel_Order(void *pInstance,
274 MS_U8 Type,
275 MS_U16 u16OutputOrder0_3,
276 MS_U16 u16OutputOrder4_7,
277 MS_U16 u16OutputOrder8_11,
278 MS_U16 u16OutputOrder12_13)
279 {
280 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
281 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
282 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
283 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
284 #if 0
285 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
286 {
287 MOD_W2BYTE(REG_MOD_BK00_08_L, u16OutputOrder0_3);
288 MOD_W2BYTE(REG_MOD_BK00_09_L, u16OutputOrder4_7);
289 MOD_W2BYTE(REG_MOD_BK00_0A_L, u16OutputOrder8_11);
290 MOD_W2BYTE(REG_MOD_BK00_0B_L, u16OutputOrder12_13);
291 }
292 else
293 {
294 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
295 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
296 {
297 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
298 {
299 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x6420);
300 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7531);
301 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xB9A8);
302 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
303 }
304 else
305 {
306 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x5410);
307 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7632);
308 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xB9A8);
309 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
310 }
311 }
312 else
313 {
314 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x5410);
315 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x5410);
316 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xB9A8);
317 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
318 }
319 }
320 #endif
321
322 }
323
MHal_PQ_Clock_Gen_For_Gamma(void * pInstance)324 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance)
325 {
326 W2BYTEMSK(REG_CLKGEN0_52_L, 0x00, 0x07);
327 }
328
MHal_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)329 void MHal_VOP_SetGammaMappingMode(void *pInstance,MS_U8 u8Mapping)
330 {
331
332 if(u8Mapping & GAMMA_MAPPING)
333 {
334 SC_W2BYTEMSK(0,REG_SC_BK10_74_L, (u8Mapping & GAMMA_10BIT_MAPPING)? BIT(15):0, BIT(15));
335 }
336 else
337 {
338 PNL_ASSERT(0, "Invalid eSupportGammaMapMode [%d] Passed to [%s], please make sure the u8Mapping[%d] is valid\n.",
339 u8Mapping, __FUNCTION__, u8Mapping);
340 }
341 }
342
Hal_VOP_Is_GammaMappingMode_enable(void * pInstance)343 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance)
344 {
345 return SC_R2BYTEMSK(0,REG_SC_BK10_74_L, BIT(15));
346 }
347
348 // After A5, 8 bit mode only support burst write!!!
Hal_VOP_Is_GammaSupportSignalWrite(void * pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)349 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)
350 {
351 return TRUE;
352 }
353
354
hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)355 void hal_PNL_WriteGamma12Bit(void *pInstance,MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
356 {
357 MS_U16 u16Delay = 0xFFFF;
358
359 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write [ch %d][addr 0x%x]: 0x%x \n", u8Channel, u16Addr, u16GammaValue);
360
361 if (!bBurstWrite )
362 {
363 while (SC_R2BYTEMSK(0,REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
364 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
365
366 SC_W2BYTEMSK(0,REG_SC_BK10_6C_L, u16Addr, 0x3FF); // set address port
367 SC_W2BYTEMSK(0,(REG_SC_BK10_6E_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
368
369 // kick off write
370 switch(u8Channel)
371 {
372 case 0: // Red
373 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, BIT(5), BIT(5));
374 break;
375
376 case 1: // Green
377 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, BIT(6), BIT(6));
378 break;
379
380 case 2: // Blue
381 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, BIT(7), BIT(7));
382 break;
383 }
384
385 while (SC_R2BYTEMSK(0,REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
386 }
387 else
388 {
389 SC_W2BYTEMSK(0,REG_SC_BK10_6E_L, u16GammaValue, 0xFFF);
390 }
391
392
393 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
394
395 }
396
397
hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)398 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
399 {
400 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of %d is 0x%x\n", u8Channel, u16MaxGammaValue);
401
402 SC_W2BYTEMSK(0,(REG_SC_BK10_7A_L + 4 * u8Channel), u16MaxGammaValue, 0xFFF); // max. base 0
403 SC_W2BYTEMSK(0,(REG_SC_BK10_7B_L + 4 * u8Channel), u16MaxGammaValue, 0xFFF); // max. base 1
404 }
405
406
407 /////////////////////////////////////////////////////////////////////////////
408 // Gamma format (12 bit LUT)
409 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
410 // 1 set uses 2 bytes of memory.
411 //
412 // [T2 and before ] N = 256
413 // [T3] N = 256 or 1024
414 // ______________________________________________________________________________
415 // Byte | 0 1 2 n-1 n
416 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
417 // 3:0 3:0 11:4 11:4 3:0 11:4
418 //
419
Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)420 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
421 {
422 MS_U16 u16Addr = 0;
423 MS_U16 u16CodeTableIndex = u16Addr/2*3;
424 MS_U16 u16GammaValue = 0;
425 MS_U16 u16MaxGammaValue = 0;
426 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
427 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
428
429 // Go to burst write if not support
430 if ( bUsingBurstWrite )
431 {
432 // 1. initial burst write address, LUT_ADDR[7:0]
433 SC_W2BYTEMSK(0,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
434
435 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
436 switch(u8Channel)
437 {
438 case 0: // Red
439 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
440 break;
441
442 case 1: // Green
443 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
444 break;
445
446 case 2: // Blue
447 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
448 break;
449 }
450
451 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
452 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
453
454 }
455
456 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
457 // write gamma table per one channel
458 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
459 {
460 // gamma x
461 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
462 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
463
464 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
465 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
466
467 if(u16MaxGammaValue < u16GammaValue)
468 {
469 u16MaxGammaValue = u16GammaValue;
470 }
471
472 // write gamma value
473 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
474 u16Addr++;
475
476 // gamma x+1
477 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
478 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
479
480 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
481
482 if(u16MaxGammaValue < u16GammaValue)
483 {
484 u16MaxGammaValue = u16GammaValue;
485 }
486
487 // write gamma value
488 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
489 u16Addr++;
490 }
491
492 if ( bUsingBurstWrite )
493 {
494 // 5. after finish burst write data of one channel, disable burst write mode
495 SC_W2BYTEMSK(0,REG_SC_BK10_6D_L, 0x00 , BIT(0));
496 }
497
498 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
499 }
_MHal_PNL_GetSupportedLPLLIndex(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)500 static E_PNL_SUPPORTED_LPLL_TYPE _MHal_PNL_GetSupportedLPLLIndex(void *pInstance,
501 PNL_TYPE eLPLL_Type,
502 PNL_MODE eLPLL_Mode,
503 MS_U64 ldHz)
504 {
505 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
506
507 switch (eLPLL_Type)
508 {
509 case E_PNL_TYPE_LVDS:
510 switch (eLPLL_Mode)
511 {
512 case E_PNL_MODE_SINGLE:
513 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to90MHz;
514 break;
515
516 default:
517 case E_PNL_MODE_DUAL:
518 if ((ldHz >= 500000000UL) && (ldHz < 1100000000UL))
519 {
520 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to110MHz;
521 }
522 else
523 {
524 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_110to150MHz;
525 }
526 break;
527 }
528 break;
529
530 case E_PNL_TYPE_HS_LVDS:
531
532 switch (eLPLL_Mode)
533 {
534 case E_PNL_MODE_SINGLE:
535 if((ldHz >= 500000000UL) && (ldHz < 1100000000UL))
536 {
537 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to110MHz;
538 }
539 else
540 {
541 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_110to150MHz;
542 }
543 break;
544
545 default:
546 case E_PNL_MODE_DUAL:
547 if(ldHz >= 2300000000UL)
548 {
549 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_230to300MHz;
550 }
551 else if(ldHz >= 1145000000UL)
552 {
553 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_114_5to230MHz;
554 }
555 else
556 {
557 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to114_5MHz;
558 }
559 break;
560 }
561 break;
562
563 case E_PNL_TYPE_TTL:
564 if ((ldHz >= 250000000UL) && (ldHz < 500000000UL))
565 {
566 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to50MHz;
567 }
568 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
569 {
570 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_50to100MHz;
571 }
572 else
573 {
574 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_100to150MHz;
575 }
576 break;
577
578 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
579 //if (ldHz >= 500000000UL)
580 {
581 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz;
582 }
583 break;
584
585 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
586 if (ldHz >= 1000000000UL)
587 {
588 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz;
589 }
590 else //if (ldHz >= 500000000UL)
591 {
592 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz;
593 }
594 break;
595
596 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
597 if (ldHz >= 666700000UL)
598 {
599 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz;
600 }
601 else //if (ldHz >= 500000000UL)
602 {
603 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz;
604 }
605 break;
606
607 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
608 if (ldHz >= 1333300000UL)
609 {
610 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz;
611 }
612 else if (ldHz >= 666700000UL)
613 {
614 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz;
615 }
616 else
617 {
618 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz;
619 }
620 break;
621
622 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
623 if (ldHz >= 1000000000UL)
624 {
625 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz;
626 }
627 else //if (ldHz >= 500000000UL)
628 {
629 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz;
630 }
631 break;
632
633 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
634 if (ldHz >= 1333300000UL)
635 {
636 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133_33to150MHz;
637 }
638 else if (ldHz >= 666700000UL)
639 {
640 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_66_67to133_33MHz;
641 }
642 else
643 {
644 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to66_67MHz;
645 }
646 break;
647
648 case E_PNL_LPLL_EPI34_4P:
649 if (ldHz >= 950000000UL)
650 {
651 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_95to150MHz;
652 }
653 else //if (ldHz >= 800000000UL)
654 {
655 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to95MHz;
656 }
657 break;
658
659 case E_PNL_LPLL_EPI34_6P:
660 //if (ldHz >= 800000000UL)
661 {
662 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to150MHz;
663 }
664 break;
665
666 case E_PNL_LPLL_EPI34_8P:
667 if (ldHz >= 950000000UL)
668 {
669 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_95to150MHz;
670 }
671 else //if (ldHz >= 800000000UL)
672 {
673 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to95MHz;
674 }
675 break;
676
677 case E_PNL_LPLL_EPI28_4P:
678 if (ldHz >= 1150000000UL)
679 {
680 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_115to150MHz;
681 }
682 else //if (ldHz >= 800000000UL)
683 {
684 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to115MHz;
685 }
686 break;
687
688 case E_PNL_LPLL_EPI28_6P:
689 //if (ldHz >= 800000000UL)
690 {
691 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to150MHz;
692 }
693 break;
694
695 case E_PNL_LPLL_EPI28_8P:
696 if (ldHz >= 1150000000UL)
697 {
698 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_115to150MHz;
699 }
700 else //if (ldHz >= 800000000UL)
701 {
702 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to115MHz;
703 }
704 break;
705
706 default:
707 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
708 break;
709 }
710 return u8SupportedLPLLIndex;
711 }
_MHal_PNL_DumpLPLLTable(void * pInstance,E_PNL_SUPPORTED_LPLL_TYPE LPLLTblIndex)712 static void _MHal_PNL_DumpLPLLTable(void *pInstance, E_PNL_SUPPORTED_LPLL_TYPE LPLLTblIndex)
713 {
714 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_MAX)
715 {
716 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
717 return;
718 }
719
720 int indexCounter = 0;
721
722 for(indexCounter = 0 ; indexCounter<LPLL_REG_NUM; indexCounter++)
723 {
724 if (LPLLSettingTBL[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
725 {
726 MsOS_DelayTaskUs(LPLLSettingTBL[LPLLTblIndex][indexCounter].value);
727 continue; // step forward to next register setting.
728 }
729
730 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address),
731 LPLLSettingTBL[LPLLTblIndex][indexCounter].value,
732 LPLLSettingTBL[LPLLTblIndex][indexCounter].mask);
733 }
734
735 }
736
MHal_PNL_Init_LPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)737 void MHal_PNL_Init_LPLL(void *pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
738 {
739 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
740 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
741 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
742 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
743 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
744 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
745
746 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz);
747 W2BYTEMSK(L_BK_LPLL(0x6D), 0x84, 0xFF);
748 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
749 {
750 printf("Not Supported LPLL Type, skip LPLL Init\n");
751 return;
752 }
753
754 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex);
755
756
757 MHal_MOD_PVDD_Power_Setting(pInstance, pPNLResourcePrivate->sthalPNL._bPVDD_2V5); // Einstein is always use 3.3V PVDD Power.
758 //switch(eLPLL_Type)
759 //{
760 // case E_PNL_TYPE_LVDS:
761
762 // if(eLPLL_Mode == E_PNL_MODE_SINGLE)
763 // {
764 // W2BYTEMSK(L_BK_LPLL(0x02), 0x2000, 0x3000);// [13:12]reg_lpll1_scalar_div_first
765 // }
766 // else
767 // {
768 // W2BYTEMSK(L_BK_LPLL(0x02), 0x1000, 0x3000);// [13:12] reg_lpll1_scalar_div_first
769 // }
770
771 // W2BYTEMSK(L_BK_LPLL(0x01), 0x203, 0xFF03); // [15:8]|[1:0] reg_lpll1_loop_div_second | reg_lpll1_loop_div_first
772 // W2BYTEMSK(L_BK_LPLL(0x02), 0x0700, 0x0F00);// [11:8] reg_lpll1_scalar_div_second
773 // W2BYTEMSK(L_BK_LPLL(0x03), 0x12, 0x23F);// [9]|[5]|[4:2]|[1:0] reg_lpll1_en_skew_div | reg_lpll1_pd | reg_lpll1_ibias_ictrl | reg_lpll1_icp_ictrl
774 // W2BYTEMSK(L_BK_LPLL(0x2E), 0x20, 0x6F);// [6]|[5]|[3:0] reg_lpll_en_fifo | reg_lpll_vco_sel | reg_lpll_fifo_div
775 // W2BYTEMSK(L_BK_LPLL(0x30), 0x0, 0xFF00);// [15:8] reg_lpll2_input_div_second
776 // W2BYTEMSK(L_BK_LPLL(0x31), 0x0, 0xFF03);// [15:8]|[1:0] reg_lpll2_loop_div_second | reg_lpll2_loop_div_first
777 // W2BYTEMSK(L_BK_LPLL(0x32), 0x0, 0x3);// [1:0] reg_lpll2_output_div_first
778 // W2BYTEMSK(L_BK_LPLL(0x33), 0x20, 0x3F);// [5]|[4:2]|[1:0] reg_lpll2_pd | reg_lpll2_ibias_ictrl | reg_lpll2_icp_ictrl
779 // W2BYTEMSK(L_BK_LPLL(0x35), 0x1300, 0x7320);// [14:12]|[9:8]|[5] reg_lpll1_skew_div |reg_lpll_pd_phdac |reg_lpll_2ndpll_clk_sel
780 // W2BYTEMSK(L_BK_LPLL(0x37), 0x0, 0x4006);// [14]|[2]|[1] reg_lpll1_test[30] | reg_lpll1_test[18]| reg_lpll1_test[17]
781
782 // break;
783
784 // case E_PNL_TYPE_HS_LVDS:
785
786
787 // break;
788
789 // case E_PNL_TYPE_HF_LVDS:
790
791
792 // break;
793 // default:
794 // //Others
795 // break;
796 //}
797
798 //if( eLPLL_Type == E_PNL_TYPE_TTL)
799 // MHal_MOD_PVDD_Power_Setting(pInstance,FALSE);
800 //else
801 // MHal_MOD_PVDD_Power_Setting(pInstance,TRUE);
802 }
803
MHal_PNL_Get_Loop_DIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U32 ldHz)804 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U32 ldHz)
805 {
806 MS_U16 u16loop_div = 0;
807 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
808 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
809 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz);
810
811 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
812 {
813 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
814 u16loop_div = 0 ;
815 }
816 else
817 {
818 u16loop_div = u16LoopDiv[u8SupportedLPLLLIndex];
819 }
820 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_div=%u\n", u16loop_div);
821
822 u16loop_div *= 2;
823 return u16loop_div;
824 //MS_U16 u16loop_div=0;
825 //switch(eLPLL_Type)
826 //{
827 // case E_PNL_TYPE_MINILVDS:
828 // case E_PNL_TYPE_ANALOG_MINILVDS:
829 // case E_PNL_LPLL_MINILVDS_6P_1L:
830 // u16loop_div = 8;
831 // break;
832
833 // case E_PNL_TYPE_DIGITAL_MINILVDS: //E_PNL_TYPE_MINILVDS_6P_2L
834 // u16loop_div = 4;
835 // break;
836
837 // case E_PNL_LPLL_MINILVDS_4P_2L:
838 // u16loop_div = 12;
839 // break;
840
841 // case E_PNL_LPLL_MINILVDS_4P_1L:
842 // u16loop_div = 6;
843 // break;
844
845 // case E_PNL_LPLL_MINILVDS_3P_2L:
846 // u16loop_div = 16;
847 // break;
848 // case E_PNL_LPLL_MINILVDS_3P_1L:
849 // u16loop_div = 8;
850 // break;
851
852 // case E_PNL_TYPE_LVDS:
853 // if(u8LPLL_Mode == E_PNL_MODE_SINGLE)
854 // u16loop_div = 28;
855 // else if(u8LPLL_Mode == E_PNL_MODE_DUAL)
856 // u16loop_div = 14;
857 // break;
858
859 // case E_PNL_TYPE_TTL:
860 // case E_PNL_TYPE_RSDS:
861 // case E_PNL_TYPE_MFC:
862 // case E_PNL_TYPE_DAC_I:
863 // case E_PNL_TYPE_DAC_P:
864 // case E_PNL_TYPE_PDPLVDS:
865 // default:
866 // u16loop_div = 7;
867 // break;
868 //}
869 //u16loop_div *= 2;
870
871 //return u16loop_div;
872 }
873
MHal_PNL_Get_LPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U32 ldHz)874 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U32 ldHz)
875 {
876 MS_U8 u8loop_gain = 0;
877 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
878 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz);
879
880 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
881 {
882 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
883 u8loop_gain = 0 ;
884 }
885 else
886 {
887 u8loop_gain = u16LoopGain[u8SupportedLPLLLIndex];
888 }
889
890 return u8loop_gain;
891 //MS_U16 u16loop_gain = 0;
892
893 //switch(eLPLL_Type)
894 //{
895 // case E_PNL_TYPE_MINILVDS:
896 // case E_PNL_TYPE_ANALOG_MINILVDS:
897 // case E_PNL_LPLL_MINILVDS_6P_1L:
898 // u16loop_gain = LPLL_LOOPGAIN;
899 // break;
900
901 // case E_PNL_TYPE_DIGITAL_MINILVDS: //E_PNL_TYPE_MINILVDS_6P_2L
902 // u16loop_gain = 24;
903 // break;
904
905 // case E_PNL_LPLL_MINILVDS_4P_2L:
906 // case E_PNL_LPLL_MINILVDS_4P_1L:
907 // u16loop_gain = LPLL_LOOPGAIN;
908 // break;
909
910 // case E_PNL_LPLL_MINILVDS_3P_2L:
911 // case E_PNL_LPLL_MINILVDS_3P_1L:
912 // u16loop_gain = LPLL_LOOPGAIN;
913 // break;
914
915 // case E_PNL_TYPE_TTL:
916 // case E_PNL_TYPE_LVDS:
917 // case E_PNL_TYPE_RSDS:
918 // case E_PNL_TYPE_MFC:
919 // case E_PNL_TYPE_DAC_I:
920 // case E_PNL_TYPE_DAC_P:
921 // case E_PNL_TYPE_PDPLVDS:
922 // default:
923 // u16loop_gain = LPLL_LOOPGAIN;
924 // break;
925 //}
926
927 //return u16loop_gain;
928 }
929
930 #define SKIP_TIMING_CHANGE_CAP TRUE
Hal_PNL_SkipTimingChange_GetCaps(void * pInstance)931 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance)
932 {
933 #if (SKIP_TIMING_CHANGE_CAP)
934 return TRUE;
935 #else
936 return FALSE;
937 #endif
938 }
939
MHal_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)940 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)
941 {
942 if (lvdsresinfo.bEnable)
943 {
944 if (lvdsresinfo.u16channel & BIT(0)) // Channel A
945 {
946 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
947 {
948 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15));
949 }
950 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
951 {
952 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14));
953 }
954 }
955 if (lvdsresinfo.u16channel & BIT(1)) // Channel B
956 {
957 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
958 {
959 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13));
960 }
961 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
962 {
963 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12));
964 }
965 }
966 }
967 else
968 {
969 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12)));
970 }
971 }
972
973
974 ////////////////////////////////////////////////////////////////////////
975 // Turn OD function
976 ////////////////////////////////////////////////////////////////////////
MHal_PNL_OverDriver_Init(void * pInstance,MS_U32 u32OD_MSB_Addr,MS_U32 u32OD_MSB_limit,MS_U32 u32OD_LSB_Addr,MS_U32 u32OD_LSB_limit)977 void MHal_PNL_OverDriver_Init(void *pInstance,MS_U32 u32OD_MSB_Addr, MS_U32 u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit)
978 {
979 SC_W2BYTE(0,REG_SC_BK16_15_L, (MS_U16)(u32OD_MSB_Addr & 0xFFFF)); // OD MSB request base address
980 SC_W2BYTEMSK(0,REG_SC_BK16_16_L, (MS_U16)((u32OD_MSB_Addr >> 16) & 0x03FF), 0x03FF); // OD MSB request base address
981 SC_W2BYTE(0,REG_SC_BK16_17_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD MSB request address limit
982 SC_W2BYTEMSK(0,REG_SC_BK16_18_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x03FF), 0x03FF); // OD MSB request address limit
983
984 SC_W2BYTE(0,REG_SC_BK16_39_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD frame buffer write address limit
985 SC_W2BYTEMSK(0,REG_SC_BK16_3A_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer write address limit
986
987 SC_W2BYTE(0,REG_SC_BK16_3B_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD frame buffer read address limit
988 SC_W2BYTEMSK(0,REG_SC_BK16_3C_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer read address limit
989
990 ///SC_W2BYTE(0,REG_SC_BK16_4F_L, (MS_U16)(u32OD_LSB_Addr & 0xFFFF)); // OD LSB request base address
991 ///SC_W2BYTEMSK(0,REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_Addr >> 16) & 0x00FF), 0x00FF); // OD LSB request base address
992 ///SC_W2BYTEMSK(0,REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_limit & 0x00FF) << 8), 0xFF00); // OD LSB request limit address
993 ///SC_W2BYTE(0,REG_SC_BK16_51_L, (MS_U16)((u32OD_LSB_limit >> 8) & 0xFFFF)); // OD LSB request limit address
994
995 SC_W2BYTE(0,REG_SC_BK16_1A_L, 0x4020); // OD request rFIFO limit threshold, priority threshold
996 SC_W2BYTE(0,REG_SC_BK16_1C_L, 0x4020); // OD request wFIFO limit threshold, priority threshold
997 SC_W2BYTEMSK(0,REG_SC_BK16_3A_L, 0x00, BIT(14)); // OD strength gradually bypass
998 SC_W2BYTEMSK(0,REG_SC_BK16_3A_L, 0x2F00, 0x3F00); // OD strength gradually slop
999 SC_W2BYTEMSK(0,REG_SC_BK16_12_L, 0x0C, 0xFF); // OD active threshold
1000 }
1001
MHal_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1002 void MHal_PNL_OverDriver_Enable(void *pInstance,MS_BOOL bEnable)
1003 {
1004 // OD mode
1005 // OD used user weight to output blending directly
1006 // OD Enable
1007 if (bEnable)
1008 {
1009 SC_W2BYTEMSK(0,REG_SC_BK16_10_L, 0x2D, 0x2F);
1010 }
1011 else
1012 {
1013 SC_W2BYTEMSK(0,REG_SC_BK16_10_L, 0x2C, 0x2F);
1014 }
1015 }
1016
MHal_PNL_OverDriver_TBL(void * pInstance,MS_U8 u8ODTbl[1056])1017 void MHal_PNL_OverDriver_TBL(void *pInstance,MS_U8 u8ODTbl[1056])
1018 {
1019 // SRAM 1: 17x17 = 289
1020 // SRAM 2: 17x16 = 272
1021 // SRAM 3: 17x16 = 272
1022 // SRAM 4: 16x16 = 256
1023 MS_U16 i;
1024 MS_U8 u8target;
1025 MS_BOOL bEnable;
1026
1027 bEnable = SC_R2BYTEMSK(0,REG_SC_BK16_10_L, BIT(0));
1028 SC_W2BYTEMSK(0,REG_SC_BK16_10_L, 0x00, BIT(0)); // OD enable
1029 SC_W2BYTEMSK(0,REG_SC_BK16_01_L, 0x0E, 0x0E); // OD table SRAM enable, RGB channel
1030
1031 u8target= u8ODTbl[9];
1032 for (i=0; i<272; i++)
1033 {
1034 SC_W2BYTEMSK(0,REG_SC_BK16_03_L, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
1035 SC_W2BYTEMSK(0,REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1036 while(SC_R2BYTEMSK(0,REG_SC_BK16_02_L, BIT(15)));
1037 }
1038
1039 // temp patch for 33x33 for SRAM1
1040 for (i=272; i<289; i++)
1041 {
1042 SC_W2BYTEMSK(0,REG_SC_BK16_03_L, 0x00, 0x00FF);
1043 SC_W2BYTEMSK(0,REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1044 while(SC_R2BYTEMSK(0,REG_SC_BK16_02_L, BIT(15)));
1045 }
1046
1047 u8target= u8ODTbl[(272+19)];
1048 for (i=0; i<272; i++)
1049 {
1050 SC_W2BYTEMSK(0,REG_SC_BK16_06_L, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
1051 SC_W2BYTEMSK(0,REG_SC_BK16_05_L, (i|0x8000), 0x81FF);
1052 while(SC_R2BYTEMSK(0,REG_SC_BK16_05_L, BIT(15)));
1053 }
1054
1055 u8target= u8ODTbl[(272*2+29)];
1056 for (i=0; i<256; i++)
1057 {
1058 SC_W2BYTEMSK(0,REG_SC_BK16_09_L, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
1059 SC_W2BYTEMSK(0,REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
1060 while(SC_R2BYTEMSK(0,REG_SC_BK16_08_L, BIT(15)));
1061 }
1062
1063 // temp patch for 33x33 for SRAM3
1064 for (i=256; i<272; i++)
1065 {
1066 SC_W2BYTEMSK(0,REG_SC_BK16_09_L, 0x00, 0x00FF);
1067 SC_W2BYTEMSK(0,REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
1068 while(SC_R2BYTEMSK(0,REG_SC_BK16_08_L, BIT(15)));
1069 }
1070
1071 u8target= u8ODTbl[(272*2+256+39)];
1072 for (i=0; i<256; i++)
1073 {
1074 SC_W2BYTEMSK(0,REG_SC_BK16_0C_L, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
1075 SC_W2BYTEMSK(0,REG_SC_BK16_0B_L, (i|0x8000), 0x81FF);
1076 while(SC_R2BYTEMSK(0,REG_SC_BK16_0D_L, BIT(15)));
1077 }
1078
1079 SC_W2BYTEMSK(0,REG_SC_BK16_01_L, 0x00, 0x0E); // OD table SRAM enable, RGB channel
1080 SC_W2BYTEMSK(0,REG_SC_BK16_10_L, bEnable, BIT(0)); // OD enable
1081 }
1082
_MHal_PNL_MOD_Swing_Refactor_AfterCAL(void * pInstance,MS_U16 u16Swing_Level)1083 MS_U16 _MHal_PNL_MOD_Swing_Refactor_AfterCAL(void *pInstance, MS_U16 u16Swing_Level)
1084 {
1085 MS_U8 u8ibcal = 0x00;
1086 MS_U16 u16AfterCal_value = 0;
1087 MS_U16 u16Cus_value = 0;
1088
1089 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1090 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1091 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1092 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1093
1094 // =========
1095 // GCR_CAL_LEVEL[1:0] : REG_MOD_BK00_7D_L =>
1096 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1097 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1098 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1099 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1100 // =========
1101 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1102 {
1103 default:
1104 case 0:
1105 u8ibcal = 0x15;
1106 break;
1107 case 1:
1108 u8ibcal = 0x1F;
1109 break;
1110 case 2:
1111 u8ibcal = 0x1A;
1112 break;
1113 case 3:
1114 u8ibcal = 0x10;
1115 break;
1116 }
1117 u16Cus_value = (u16Swing_Level) * (pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4)/(u8ibcal + 4);
1118 u16AfterCal_value = (u16Cus_value-40)/10+2;
1119
1120 HAL_MOD_CAL_DBG(printf("\r\n--Swing value after refactor = %d\n", u16AfterCal_value));
1121
1122 return u16AfterCal_value;
1123 }
1124
MHal_PNL_MOD_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)1125 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance,MS_U16 u16Swing_Level)
1126 {
1127 MS_BOOL bStatus = FALSE;
1128 MS_U16 u16ValidSwing = 0;
1129 MS_U16 u16ValidSwing_ext = 0;
1130
1131 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1132 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1133 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1134 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1135
1136 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)||
1137 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS))
1138 {
1139 if(u16Swing_Level>600)
1140 u16Swing_Level=600;
1141 if(u16Swing_Level<40)
1142 u16Swing_Level=40;
1143
1144 u16ValidSwing = _MHal_PNL_MOD_Swing_Refactor_AfterCAL(pInstance, u16Swing_Level);
1145 }
1146 else
1147 {
1148 u16ValidSwing = u16Swing_Level;
1149 }
1150
1151 u16ValidSwing = u16ValidSwing & 0x3F;
1152 u16ValidSwing_ext = (u16ValidSwing & 0x40)>>6;
1153
1154 MOD_W2BYTEMSK(REG_MOD_BK00_29_L,
1155 ( (u16ValidSwing << 4 )|(u16ValidSwing << 10 ) ) , 0xFFF0);
1156
1157 MOD_W2BYTE(REG_MOD_BK00_2A_L,
1158 ((u16ValidSwing )|(u16ValidSwing << 6 ) |(u16ValidSwing << 12 ) ));
1159
1160 MOD_W2BYTE(REG_MOD_BK00_2B_L,
1161 ( (u16ValidSwing >> 4 )|(u16ValidSwing << 2 ) |(u16ValidSwing << 8 ) | (u16ValidSwing << 14 )));
1162
1163 MOD_W2BYTE(REG_MOD_BK00_2C_L,
1164 ( (u16ValidSwing >> 2 )|(u16ValidSwing << 4 ) |(u16ValidSwing << 10 ) ) );
1165
1166 MOD_W2BYTE(REG_MOD_BK00_2D_L,
1167 ( (u16ValidSwing )|(u16ValidSwing << 6 ) |(u16ValidSwing << 12 ) ));
1168
1169 MOD_W2BYTE(REG_MOD_BK00_2E_L,
1170 ( (u16ValidSwing >> 4 )|(u16ValidSwing << 2 )) );
1171
1172 /// for extended bit, extended bit for reg_gcr_icon_ch0~ch13
1173 MOD_W2BYTE(REG_MOD_BK00_2F_L,
1174 (u16ValidSwing_ext )|(u16ValidSwing_ext << 1 )|(u16ValidSwing_ext << 2 )|(u16ValidSwing_ext << 3 )|
1175 (u16ValidSwing_ext << 4)|(u16ValidSwing_ext << 5 )|(u16ValidSwing_ext << 6 )|(u16ValidSwing_ext << 7 )|
1176 (u16ValidSwing_ext << 8)|(u16ValidSwing_ext << 9 )|(u16ValidSwing_ext <<10 )|(u16ValidSwing_ext <<11 )|
1177 (u16ValidSwing_ext <<12)|(u16ValidSwing_ext <<13 )|(u16ValidSwing_ext <<14 )|(u16ValidSwing_ext <<15 )
1178 );
1179
1180 bStatus = TRUE;
1181
1182 return bStatus;
1183 }
1184
1185
1186 ////////////////////////////////////////////////////////////////////////
1187 // Turn Pre-Emphasis Current function
1188 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_PE_Current(void * pInstance,MS_U16 u16Current_Level)1189 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance,MS_U16 u16Current_Level)
1190 {
1191 MS_BOOL bStatus = FALSE;
1192 MS_U16 u16ValidCurrent = u16Current_Level & 0x07;
1193
1194 MOD_W2BYTEMSK(REG_MOD_BK00_23_L,
1195 ( (u16ValidCurrent ) |(u16ValidCurrent << 3 )|(u16ValidCurrent << 6 )
1196 |(u16ValidCurrent << 9 ) |(u16ValidCurrent << 12 )) , 0x7FFF);
1197
1198 MOD_W2BYTEMSK(REG_MOD_BK00_24_L,
1199 ( (u16ValidCurrent ) |(u16ValidCurrent << 3 )|(u16ValidCurrent << 6 )
1200 |(u16ValidCurrent << 9 ) |(u16ValidCurrent << 12 )) , 0x7FFF);
1201
1202 MOD_W2BYTEMSK(REG_MOD_BK00_25_L,
1203 ( (u16ValidCurrent ) |(u16ValidCurrent << 3 )|(u16ValidCurrent << 6 )
1204 |(u16ValidCurrent << 9 ) |(u16ValidCurrent << 12 )) , 0x7FFF);
1205
1206 MOD_W2BYTEMSK(REG_MOD_BK00_26_L,
1207 ( (u16ValidCurrent ) |(u16ValidCurrent << 3 )|(u16ValidCurrent << 6 )
1208 |(u16ValidCurrent << 9 ) |(u16ValidCurrent << 12 )) , 0x7FFF);
1209
1210 MOD_W2BYTEMSK(REG_MOD_BK00_29_L, u16ValidCurrent ,0x0007);
1211
1212 bStatus = TRUE;
1213
1214 return bStatus;
1215 }
1216
1217
1218 ////////////////////////////////////////////////////////////////////////
1219 // 1.Turn TTL low-power mode function
1220 // 2.Turn internal termination function
1221 // 3.Turn DRIVER BIAS OP function
1222 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_TTL_Resistor_OP(void * pInstance,MS_BOOL bEnble)1223 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance,MS_BOOL bEnble)
1224 {
1225 MS_BOOL bStatus = FALSE;
1226 if(bEnble)
1227 {
1228 MOD_W2BYTEMSK(REG_MOD_BK00_36_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode
1229 MOD_W2BYTEMSK(REG_MOD_BK00_37_L, 0x001E, 0x001E);
1230
1231 MOD_W2BYTEMSK(REG_MOD_BK00_75_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open)
1232 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F);
1233
1234 MOD_W2BYTEMSK(REG_MOD_BK00_79_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP
1235 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F);
1236 }
1237 else
1238 {
1239 MOD_W2BYTEMSK(REG_MOD_BK00_36_L, 0x0000, 0xFFFF); //Disable TTL low-power mode
1240 MOD_W2BYTEMSK(REG_MOD_BK00_37_L, 0x0000, 0x001E);
1241
1242 MOD_W2BYTEMSK(REG_MOD_BK00_75_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close)
1243 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F);
1244
1245 MOD_W2BYTEMSK(REG_MOD_BK00_79_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP
1246 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F);
1247 }
1248
1249 bStatus = TRUE;
1250 return bStatus;
1251 }
1252
MHal_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)1253 void MHal_PNL_PreInit(void *pInstance,PNL_OUTPUT_MODE eParam)
1254 {
1255 _eDrvPnlInitOptions = eParam;
1256 }
1257
MHal_PNL_Get_Output_MODE(void * pInstance)1258 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance)
1259 {
1260 PNL_OUTPUT_MODE eParam = _eDrvPnlInitOptions;
1261
1262 return eParam;
1263 }
1264
MHal_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)1265 void MHal_PNL_SetOutputType(void *pInstance,PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
1266 {
1267 MS_U16 u16ValidSwing2 = 0;
1268 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1269 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1270
1271 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1272 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1273 if( eLPLL_Type == E_PNL_TYPE_TTL)
1274 {
1275 // select pair output to be TTL
1276 MOD_W2BYTE(REG_MOD_BK00_6D_L, 0x0000);
1277 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x0000);
1278 MOD_W2BYTEMSK(REG_MOD_BK00_6F_L, 0x0000, 0xEFFF);//0x6F
1279
1280 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair
1281
1282 // other TTL setting
1283 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x0000); // TTL output enable
1284
1285 MOD_W2BYTE(REG_MOD_BK00_46_L, 0x0000);
1286 MOD_W2BYTE(REG_MOD_BK00_47_L, 0x0000);
1287 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000);
1288
1289 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew
1290
1291 // GPO gating
1292 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating
1293 }
1294 else
1295 {
1296 switch(eOutputMode)
1297 {
1298 case E_PNL_OUTPUT_NO_OUTPUT:
1299 // if MOD_45[5:0] = 0x3F && XC_MOD_EXT_DATA_EN_L = 0x0,
1300 // then if XC_MOD_OUTPUT_CONF_L = 0x0 ---> output TTL as tri-state
1301 MOD_W2BYTE(REG_MOD_BK00_6D_L, 0x0000);
1302 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x0000);
1303 MOD_W2BYTEMSK(REG_MOD_BK00_6F_L, 0x0000, 0x000F);
1304
1305 //----------------------------------
1306 // Purpose: Set the output to be the GPO, and let it's level to Low
1307 // 1. External Enable, Pair 0~5
1308 // 2. GPIO Enable, pair 0~5
1309 // 3. GPIO Output data : All low, pair 0~5
1310 // 4. GPIO OEZ: output piar 0~5
1311 //----------------------------------
1312
1313 //1.External Enable, Pair 0~5
1314 MOD_W2BYTEMSK(REG_MOD_BK00_46_L, 0x0FFF, 0x0FFF);
1315 //2.GPIO Enable, pair 0~5
1316 MOD_W2BYTEMSK(REG_MOD_BK00_4D_L, 0x0FFF, 0x0FFF);
1317 //3.GPIO Output data : All low, pair 0~5
1318 MOD_W2BYTEMSK(REG_MOD_BK00_4F_L, 0x0000, 0x0FFF);
1319 //4.GPIO OEZ: output piar 0~5
1320 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, 0x0FFF);
1321
1322 //1.External Enable, Pair 6~15
1323 MOD_W2BYTEMSK(REG_MOD_BK00_46_L, 0xF000, 0xF000);
1324 MOD_W2BYTE(REG_MOD_BK00_47_L, 0xFFFF);
1325 //2.GPIO Enable, pair 6~15
1326 MOD_W2BYTEMSK(REG_MOD_BK00_4D_L, 0xF000, 0xF000);
1327 MOD_W2BYTE(REG_MOD_BK00_4E_L, 0xFFFF);
1328 //3.GPIO Output data : All low, pair 6~15
1329 MOD_W2BYTEMSK(REG_MOD_BK00_4F_L, 0x0000, 0xF000);
1330 MOD_W2BYTE(REG_MOD_BK00_50_L, 0x0000);
1331 //4.GPIO OEZ: output piar 6~15
1332 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, 0xF000);
1333 MOD_W2BYTE(REG_MOD_BK00_52_L, 0x0000);
1334
1335 //1234.External Enable, Pair 16~17
1336 MOD_W2BYTE(REG_MOD_BK00_7E_L, 0xFF00);
1337
1338 //1.External Enable, Pair 18~20, 2.GPIO Enable, pair 18~20
1339 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F);
1340 //3.GPIO Output data : All low, pair 18~20
1341 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00);
1342 //4.GPIO OEZ: output piar 18~20
1343 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00);
1344 break;
1345
1346 case E_PNL_OUTPUT_CLK_ONLY:
1347 MOD_W2BYTEMSK(REG_MOD_BK00_6D_L, 0, 0xF000);
1348 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0x4004);
1349 MOD_W2BYTEMSK(REG_MOD_BK00_6F_L, 0, 0x000F);
1350 break;
1351
1352 case E_PNL_OUTPUT_DATA_ONLY:
1353 case E_PNL_OUTPUT_CLK_DATA:
1354 default:
1355
1356 MOD_W2BYTEMSK(REG_MOD_BK00_4D_L, 0x0000, 0xF000);
1357 MOD_W2BYTE(REG_MOD_BK00_4E_L, 0x0000);
1358 //1. set GCR_PVDD_2P5=1��b0; MOD PVDD power: 0: 3.3V
1359 MOD_W2BYTEMSK(REG_MOD_BK00_37_L, 0x00, BIT(6));
1360 //2. set PD_IB_MOD=1��b0;
1361 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x00, BIT(0));
1362 // save ch6 init value
1363 u16ValidSwing2 = (MOD_R2BYTEMSK(REG_MOD_BK00_2B_L, 0x3F00)>>8);
1364 //3. set Desired Pairs: GCR_ICON[5:0]=6��h3f (current all open);
1365 MHal_PNL_MOD_Control_Out_Swing(pInstance,0x3F);
1366 //4. set Desired Pairs: GCR_PE_ADJ[2:0]=3��h7 (pre-emphasis current all open )
1367 MHal_PNL_MOD_Control_Out_PE_Current (pInstance,0x07);
1368 //5. Enable low-power modeinternal termination Open, Enable OP
1369 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance,1);
1370
1371 MsOS_DelayTask(1);
1372
1373 //6. Enable low-power modeinternal termination Open, Enable OP
1374 MHal_Output_LVDS_Pair_Setting(pInstance,
1375 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
1376 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
1377 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
1378 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
1379 //pPNLResourcePrivate->stdrvPNL._stPnlInitData
1380 MHal_Shift_LVDS_Pair(pInstance,_u8MOD_LVDS_Pair_Shift);
1381
1382 //7. set Desired Pairs: GCR_PE_ADJ[2:0]=3��h0 (pre-emphasis current all Close)
1383 MHal_PNL_MOD_Control_Out_PE_Current (pInstance,0x00);
1384 //8. set Desired Pairs: GCR_ICON[5:0] (current all init);
1385 MHal_PNL_MOD_Control_Out_Swing(pInstance,u16ValidSwing2);
1386 //9. Disable low-power modeinternal termination Close, Disable OP
1387 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance,0);
1388
1389 // other TTL setting
1390 MOD_W2BYTE(REG_MOD_BK00_45_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/ PANEL_miniLVDS/ PANEL_RSDS
1391
1392 MOD_W2BYTEMSK(REG_MOD_BK00_46_L, 0x0000, 0xF000);
1393 MOD_W2BYTE(REG_MOD_BK00_47_L, 0x0000);
1394 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F);
1395
1396 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew
1397
1398 // GPO gating
1399 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating
1400
1401 break;
1402 }
1403 }
1404 }
1405
Mhal_PNL_Flock_LPLLSet(void * pInstance,MS_U32 ldHz)1406 void Mhal_PNL_Flock_LPLLSet(void *pInstance,MS_U32 ldHz)
1407 {
1408 UNUSED(ldHz);
1409 }
1410
1411
MHal_PNL_MISC_Control(void * pInstance,MS_U32 u32PNL_MISC)1412 void MHal_PNL_MISC_Control(void *pInstance,MS_U32 u32PNL_MISC)
1413 {
1414 if(u32PNL_MISC & E_DRVPNL_MISC_MFC_ENABLE)
1415 {
1416 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair
1417 }
1418 }
1419
MHal_PNL_Init_XC_Clk(void * pInstance,PNL_InitData * pstPanelInitData)1420 void MHal_PNL_Init_XC_Clk(void *pInstance,PNL_InitData *pstPanelInitData)
1421 {
1422 // setup output dot clock
1423 W2BYTEMSK(REG_CKG_ODCLK, CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock
1424 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert
1425 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock
1426
1427 W2BYTEMSK(REG_CKG_BT656, CKG_BT656_CLK_LPLL, CKG_BT656_MASK); // select source tobe LPLL clock
1428 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert
1429 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock
1430 W2BYTE(REG_CLKGEN0_4F_L,0x0000); //[3:0]CLK_VBY1_FIFO clock setting
1431 W2BYTE(L_CLKGEN0(0x57),0x0000); //[15:12]ckg_bt656 [3:0]ckg_fifo
1432 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod
1433
1434 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod
1435
1436 //W2BYTE(L_CLKGEN1(0x31), 0x0000); //[11:8]ckg_odclk_frc
1437 }
1438
MHal_PNL_Init_MOD(void * pInstance,PNL_InitData * pstPanelInitData)1439 void MHal_PNL_Init_MOD(void *pInstance,PNL_InitData *pstPanelInitData)
1440 {
1441
1442 //-------------------------------------------------------------------------
1443 // Set MOD registers
1444 //-------------------------------------------------------------------------
1445
1446 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK);
1447 if(pstPanelInitData->eLPLL_Type == E_PNL_TYPE_TTL)
1448 {
1449 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, (pstPanelInitData->u16OSTRL)<<4, 0xF00);
1450 }
1451 // GPIO is controlled in drvPadConf.c
1452 // MDrv_Write2Byte(L_BK_MOD(0x46), 0x0000); //EXT GPO disable
1453 // MDrv_Write2Byte(L_BK_MOD(0x47), 0x0000); //EXT GPO disable
1454 MOD_W2BYTE(REG_MOD_BK00_49_L, pstPanelInitData->u16MOD_CTRL9); //{L_BK_MOD(0x49), 0x00}, // [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit, bit shift
1455 MOD_W2BYTE(REG_MOD_BK00_4A_L, pstPanelInitData->u16MOD_CTRLA);
1456 MOD_W2BYTE(REG_MOD_BK00_4B_L, pstPanelInitData->u8MOD_CTRLB); //[1:0]ti_bitmode 10:8bit 11:6bit 0x:10bit
1457
1458 if ( SUPPORT_SYNC_FOR_DUAL_MODE )
1459 {
1460 // Set 1 only when PNL is dual mode
1461 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12));
1462 }
1463
1464 //dual port lvds _start_//
1465 // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
1466 MOD_W2BYTE(REG_MOD_BK00_6F_L, 0x0000); // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
1467 MOD_W2BYTEMSK(REG_MOD_BK00_77_L, 0x1C, 0xFC); // original is MDrv_WriteByteMask(L_BK_MOD(0x77), 0x0F, BITMASK(7:2));
1468 //dual port lvds _end_//
1469
1470 //MOD_W2BYTEMSK(REG_MOD_BK00_78_L, (_u8PnlDiffSwingLevel << 1), 0xFE); //differential output swing level
1471 //if(!MHal_PNL_MOD_Control_Out_Swing(_u16PnlDefault_SwingLevel))
1472 // printf(">>Swing Level setting error!!\n");
1473 MOD_W2BYTE(REG_MOD_BK00_73_L, pstPanelInitData->u16LVDSTxSwapValue);
1474
1475
1476 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x0100,0x0100);
1477 // TODO: move from MDrv_Scaler_Init(), need to double check!
1478 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0));
1479
1480 if (R1BYTEMSK(REG_CHIP_REVISION, 0xFF) > 0)
1481 {
1482 // it needs internal LDO for chip after U02
1483 MOD_W2BYTEMSK(REG_MOD_BK00_7B_L, 0x03, 0xFF); // for internal LDO
1484 }
1485
1486 //--------------------------------------------------------------
1487 //Depend On Bitmode to set Dither
1488 //--------------------------------------------------------------
1489
1490
1491 // always enable noise dither and disable TAILCUT
1492 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, ((pstPanelInitData->u8PanelNoiseDith ? XC_PAFRC_DITH_NOISEDITH_EN : (1 - XC_PAFRC_DITH_NOISEDITH_EN)) <<3) , BIT(3));
1493 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, XC_PAFRC_DITH_TAILCUT_DISABLE, BIT(4));
1494
1495 switch(pstPanelInitData->u8MOD_CTRLB & 0x03)//[1:0]ti_bitmode b'10:8bit 11:6bit 0x:10bit
1496 {
1497 case HAL_TI_6BIT_MODE:
1498 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, BIT(0), BIT(0));
1499 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, BIT(2), BIT(2));
1500 break;
1501
1502 case HAL_TI_8BIT_MODE:
1503 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, BIT(0), BIT(0));
1504 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, 0x00, BIT(2));
1505 break;
1506
1507 case HAL_TI_10BIT_MODE:
1508 default:
1509 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, 0x00, BIT(0));
1510 SC_W2BYTEMSK(0,REG_SC_BK24_3F_L, 0x00, BIT(2));
1511 break;
1512 }
1513
1514
1515 //-----depend on bitmode to set Dither------------------------------
1516 MHal_PNL_SetOutputType(pInstance,_eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type); // TTL to Ursa
1517
1518 MHal_PNL_MISC_Control(pInstance,pstPanelInitData->u32PNL_MISC);
1519
1520 }
1521
MHal_PNL_DumpMODReg(void * pInstance,MS_U32 u32Addr,MS_U16 u16Value,MS_BOOL bHiByte,MS_U16 u16Mask)1522 void MHal_PNL_DumpMODReg(void *pInstance,MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask)
1523 {
1524 if (bHiByte)
1525 {
1526 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
1527 }
1528 else
1529 {
1530 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask);
1531 }
1532 }
MHal_MOD_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)1533 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
1534 {
1535 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1536 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1537 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1538 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1539 pPNLResourcePrivate->sthalPNL._usMOD_CALI_OFFSET= pstModCaliInitData->u8ModCaliTarget;
1540 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE = pstModCaliInitData->s8ModCaliOffset;
1541 }
1542
MHal_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)1543 void MHal_BD_LVDS_Output_Type(void *pInstance,MS_U16 Type)
1544 {
1545 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1546 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1547 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1548 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1549
1550 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
1551 {
1552 _u8MOD_LVDS_Pair_Shift = LVDS_DUAL_OUTPUT_SPECIAL;
1553 _u8MOD_LVDS_Pair_Type = 1;
1554 }
1555 else
1556 {
1557 _u8MOD_LVDS_Pair_Type = Type;
1558 }
1559
1560 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = _u8MOD_LVDS_Pair_Type;
1561 }
1562
msModCalDDAOUT(void * pInstance)1563 MS_BOOL msModCalDDAOUT(void *pInstance)
1564 {
1565 // W2BYTEMSK(BK_MOD(0x7D), ENABLE, 8:8);
1566 // MsOS_DelayTask(10); //10ms
1567 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_BK00_7D_L, BIT(8))) >> 8);
1568 }
1569
msModCurrentCalibration(void * pInstance)1570 MS_U8 msModCurrentCalibration(void *pInstance)
1571 {
1572 #if MOD_CAL_TIMER
1573 MS_U32 delay_start_time;
1574 delay_start_time=MsOS_GetSystemTime();
1575 #endif
1576
1577 #if (!ENABLE_Auto_ModCurrentCalibration)
1578 return 0x60;
1579 #else
1580 MS_U8 u8cur_ibcal=0;
1581 MS_U16 u16cur_ibcal[]={0,0,0,0,0,0,0,0,0,0,0,0,0,0};
1582 MS_U32 x=0;
1583 MS_U16 u16reg_3280,u16reg_3282,u16reg_328a;
1584 MS_U16 u16reg_32da,u16reg_32dc,u16reg_32de;
1585
1586
1587 u16reg_3280 = MOD_R2BYTEMSK(REG_MOD_BK00_40_L, LBMASK);
1588 u16reg_3282 = MOD_R2BYTEMSK(REG_MOD_BK00_41_L, LBMASK);
1589 u16reg_328a = MOD_R2BYTEMSK(REG_MOD_BK00_45_L, LBMASK);
1590
1591 u16reg_32da = MOD_R2BYTE(REG_MOD_BK00_6D_L);
1592 u16reg_32dc = MOD_R2BYTE(REG_MOD_BK00_6E_L);
1593 u16reg_32de = MOD_R2BYTE(REG_MOD_BK00_6F_L);
1594
1595 // =========
1596 // GCR_CAL_LEVEL[1:0] : REG_MOD_BK00_7D_L =>
1597 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1598 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1599 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1600 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1601 // =========
1602
1603 switch(_u8MOD_CALI_TARGET)
1604 {
1605 default:
1606 case 0:
1607 u8cur_ibcal = 0x19;
1608 break;
1609 case 1:
1610 u8cur_ibcal = 0x26;
1611 break;
1612 case 2:
1613 u8cur_ibcal = 0x14;
1614 break;
1615 case 3:
1616 u8cur_ibcal = 0x12;
1617 break;
1618 }
1619
1620 //MOD_W2BYTEMSK(REG_MOD_BK00_2B_L, ((MS_U16)u8cur_ibcal)<<8, 0x3F00); // calibration initialized value
1621
1622 //Set output config to be test clock output mode
1623 MOD_W2BYTE(REG_MOD_BK00_6D_L, 0xFFFF);
1624 MOD_W2BYTE(REG_MOD_BK00_6E_L, 0xFFFF);
1625 MOD_W2BYTE(REG_MOD_BK00_6F_L, 0xFFFF);
1626
1627 // White Pattern for Calibration
1628 MOD_W2BYTEMSK(REG_MOD_BK00_32_L, BIT(15), BIT(15)); // Enable test enable of digi seri
1629 MOD_W2BYTEMSK(REG_MOD_BK00_41_L, 0x00, 0xFF); // Set analog testpix output to low
1630 // (1) Set keep mode to auto write calibration result into register.
1631 MOD_W2BYTEMSK(REG_MOD_BK00_3C_L, BIT(15), BIT(15));
1632
1633 // (2) Set calibration step waiting time
1634 MOD_W2BYTE(REG_MOD_BK00_3B_L, 0x0080); // (about 5us)
1635 MOD_W2BYTEMSK(REG_MOD_BK00_3C_L, 0x0000, 0x00FF);
1636
1637 // (3) Set calibration toggle time
1638 MOD_W2BYTEMSK(REG_MOD_BK00_3C_L, 0x0500, 0x0F00);
1639 // Set Calibration target
1640 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, BIT(2), BIT(3)|BIT(2)); // Select calibration source pair, 01: channel 6
1641 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, _u8MOD_CALI_TARGET, BIT(1)|BIT(0)); // Select calibration target voltage, 00: 200mv, 01:350mv, 10: 250mv, 11: 150mv
1642 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, BIT(7), BIT(7)); // Enable calibration function
1643
1644 HAL_MOD_CAL_DBG(printf("\r\n [%s](1)Init value:u8cur_ibcal = %d\n", __FUNCTION__, u8cur_ibcal));
1645 MS_U8 u8CheckTimes = 0;
1646 while(1)
1647 {
1648 // (7) Enable Hardware calibration
1649 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, BIT(15), BIT(15));
1650
1651 // (8) Wait 2ms
1652 MsOS_DelayTask(2);
1653
1654 // (10) Disable Hardware calibration
1655 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, 0x00, BIT(15));
1656
1657 // (9)Check Finish and Fail flag bit
1658 //BK1032, 0x3D[14], Finish flag=1
1659 //BK1032, 0x3D[13], Fail flag=0
1660 if (MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000) == 0x4000)
1661 {
1662 printf("\033[0;31m [%s][%d] cal ok, break \033[0m\n", __FUNCTION__, __LINE__);
1663 //u16cur_ibcal
1664 u16cur_ibcal[0]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0001)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_29_L, 0x3F0)>>4); // ch0
1665 u16cur_ibcal[1]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0002)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_29_L, 0xFC00)>>10); // ch1
1666
1667 u16cur_ibcal[2]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0004)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2A_L, 0x3F)); // ch2
1668 u16cur_ibcal[3]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0008)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2A_L, 0xFC0)>>6); // ch3
1669 u16cur_ibcal[4]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0010)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2A_L, 0xF000)>>12) | (MOD_R2BYTEMSK(REG_MOD_BK00_2B_L, 0x03))<<4;
1670 u16cur_ibcal[5]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0020)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2B_L, 0xFC)>>2); // ch5
1671 u16cur_ibcal[6]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0040)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2B_L, 0x3F00)>>8); // ch6
1672 u16cur_ibcal[7]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0080)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2B_L, 0xC000)>>14) | (MOD_R2BYTEMSK(REG_MOD_BK00_2C_L, 0x0F)<<2);
1673 u16cur_ibcal[8]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0100)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2C_L, 0x3F0)>>4); // ch8
1674 u16cur_ibcal[9]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0200)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2C_L, 0xFC00)>>10); // ch9
1675
1676 u16cur_ibcal[10]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0400)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2D_L, 0x3F)); // ch10
1677 u16cur_ibcal[11]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x0800)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2D_L, 0xFC0)>>6); // ch11
1678 u16cur_ibcal[12]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x1000)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2D_L, 0xF000)>>12) | (MOD_R2BYTEMSK(REG_MOD_BK00_2E_L, 0x03)<<4);
1679 u16cur_ibcal[13]=(MOD_R2BYTEMSK(REG_MOD_BK00_2F_L,0x2000)<<6)| (MOD_R2BYTEMSK(REG_MOD_BK00_2E_L, 0xFC)>>2); // ch13
1680 break;
1681 }
1682 else
1683 {
1684 u8CheckTimes ++;
1685 //printf("\033[0;31m [%s][%d] cal ng, u8CheckTimes: %d \033[0m\n", __FUNCTION__, __LINE__, u8CheckTimes);
1686 }
1687
1688 if (u8CheckTimes > 3)
1689 {
1690 // (13) If 3 times all fail, set all pair to nominal value by disable keep mode
1691 //MOD_W2BYTEMSK(REG_MOD_BK00_3C_L, 0x00, BIT(15));
1692 printf("\033[0;31m [%s][%d] If 3 times all fail, set all pair to nominal value by disable keep mode \033[0m\n", __FUNCTION__, __LINE__);
1693 break;
1694 }
1695 }
1696
1697 MOD_W2BYTEMSK(REG_MOD_BK00_3C_L, 0x00, BIT(15));
1698
1699 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x00, BIT(7)); // Disable calibration function
1700 MOD_W2BYTEMSK(REG_MOD_BK00_32_L, 0x00, BIT(15)); // Disable test enable of digi seri
1701
1702 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, u16reg_3280, LBMASK);
1703 MOD_W2BYTEMSK(REG_MOD_BK00_41_L, u16reg_3282, LBMASK);
1704 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, u16reg_328a, LBMASK);
1705
1706 MOD_W2BYTE(REG_MOD_BK00_6D_L, u16reg_32da);
1707 MOD_W2BYTE(REG_MOD_BK00_6E_L, u16reg_32dc);
1708 MOD_W2BYTE(REG_MOD_BK00_6F_L, u16reg_32de);
1709
1710 if (u8CheckTimes <=3)
1711 {
1712 HAL_MOD_CAL_DBG(printf("\r\n----- Calibration ok \n"));
1713 for(x=0;x<14;x++)
1714 {
1715 //printf("\033[1;33m[%s:%d]BEF %d = %d\033[m\n",__FUNCTION__,__LINE__,x,u16cur_ibcal[x]);
1716 if((u16cur_ibcal[x]>=(u8cur_ibcal*1.6))||(u16cur_ibcal[x]<=(u8cur_ibcal*0.4)))
1717 {
1718 u16cur_ibcal[x]=u8cur_ibcal;
1719 }
1720 //printf("\033[1;33m[%s:%d]AFT %d = %d\033[m\n",__FUNCTION__,__LINE__,x,u16cur_ibcal[x]);
1721 }
1722 }
1723 else
1724 {
1725 HAL_MOD_CAL_DBG(printf("\r\n----- Calibration fail: 0x%lx \n", MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000)));
1726 //printf("\033[1;33m[%s:%d]BEF %d = %d\033[m\n",__FUNCTION__,__LINE__,x,u16cur_ibcal[x]);
1727 for(x=0;x<14;x++)
1728 {
1729 u16cur_ibcal[x]=u8cur_ibcal;
1730 }
1731 //printf("\033[1;33m[%s:%d]AFT %d = %d\033[m\n",__FUNCTION__,__LINE__,x,u16cur_ibcal[x]);
1732 }
1733
1734 // Store the final value
1735 HAL_MOD_CAL_DBG(printf("\r\n (3)Store value = %d\n", u8cur_ibcal));
1736
1737 _u8MOD_CALI_VALUE = (u8cur_ibcal & 0x3F);
1738
1739 // copy the valur of ch6 to all channel( 0~20)
1740 MOD_W2BYTEMSK(REG_MOD_BK00_29_L,((MS_U16)(u16cur_ibcal[0]&0x3F))<<4, 0x3F0); // ch0
1741 MOD_W2BYTEMSK(REG_MOD_BK00_29_L,((MS_U16)(u16cur_ibcal[1]&0x3F))<<10, 0xFC00); // ch1
1742
1743 MOD_W2BYTEMSK(REG_MOD_BK00_2A_L,((MS_U16)(u16cur_ibcal[2]&0x3F)), 0x3F); // ch2
1744 MOD_W2BYTEMSK(REG_MOD_BK00_2A_L,((MS_U16)(u16cur_ibcal[3]&0x3F))<<6, 0xFC0); // ch3
1745 MOD_W2BYTEMSK(REG_MOD_BK00_2A_L,((MS_U16)(u16cur_ibcal[4]&0x3F))<<12, 0xF000); // ch4
1746 MOD_W2BYTEMSK(REG_MOD_BK00_2B_L,((MS_U16)(u16cur_ibcal[4]&0x3F))>>4, 0x03);
1747 MOD_W2BYTEMSK(REG_MOD_BK00_2B_L,((MS_U16)(u16cur_ibcal[5]&0x3F))<<2, 0xFC); // ch5
1748 MOD_W2BYTEMSK(REG_MOD_BK00_2B_L,((MS_U16)(u16cur_ibcal[6]&0x3F))<<8, 0x3F00); // ch6
1749 MOD_W2BYTEMSK(REG_MOD_BK00_2B_L,((MS_U16)(u16cur_ibcal[7]&0x3F))<<14, 0xC000); // ch7
1750 MOD_W2BYTEMSK(REG_MOD_BK00_2C_L,((MS_U16)(u16cur_ibcal[7]&0x3F))>>2, 0x0F);
1751 MOD_W2BYTEMSK(REG_MOD_BK00_2C_L,((MS_U16)(u16cur_ibcal[8]&0x3F))<<4, 0x3F0); // ch8
1752 MOD_W2BYTEMSK(REG_MOD_BK00_2C_L,((MS_U16)(u16cur_ibcal[9]&0x3F))<<10, 0xFC00); // ch9
1753
1754 MOD_W2BYTEMSK(REG_MOD_BK00_2D_L,((MS_U16)(u16cur_ibcal[10]&0x3F)), 0x3F); // ch10
1755 MOD_W2BYTEMSK(REG_MOD_BK00_2D_L,((MS_U16)(u16cur_ibcal[11]&0x3F))<<6, 0xFC0); // ch11
1756 MOD_W2BYTEMSK(REG_MOD_BK00_2D_L,((MS_U16)(u16cur_ibcal[12]&0x3F))<<12, 0xF000); // ch12
1757 MOD_W2BYTEMSK(REG_MOD_BK00_2E_L,((MS_U16)(u16cur_ibcal[12]&0x3F))>>4, 0x03);
1758 MOD_W2BYTEMSK(REG_MOD_BK00_2E_L,((MS_U16)(u16cur_ibcal[13]&0x3F))<<2, 0xFC); // ch13
1759 MOD_W2BYTEMSK(REG_MOD_BK00_2F_L,0x0000, 0x1FFF); // MSB
1760
1761 #if MOD_CAL_TIMER
1762 printf("[%s] takes %ld ms\n", __FUNCTION__, (MsOS_GetSystemTime()-delay_start_time));
1763 #endif
1764 return (u8cur_ibcal&0x3F);//MOD_R2BYTEMSK(REG_MOD_BK00_2B_L, 0x3F00);
1765 #endif
1766 }
1767
MHal_PNL_MOD_Calibration(void * pInstance)1768 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance)
1769 {
1770 MS_U8 u8Cab;
1771 MS_U8 u8BackUSBPwrStatus;
1772
1773
1774 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
1775
1776 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
1777
1778 u8Cab = msModCurrentCalibration(pInstance);
1779
1780 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
1781
1782
1783 return E_PNL_OK;
1784
1785 }
1786
MHal_PNL_PowerDownLPLL(void * pInstance,MS_BOOL bEnable)1787 static void MHal_PNL_PowerDownLPLL(void *pInstance,MS_BOOL bEnable)
1788 {
1789 if(bEnable)
1790 {
1791 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5));
1792 }
1793 else
1794 {
1795 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5));
1796 }
1797 }
1798
MHal_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)1799 PNL_Result MHal_PNL_En(void *pInstance,MS_BOOL bPanelOn, MS_BOOL bCalEn)
1800 {
1801 MS_U8 u8Cab;
1802 MS_U8 u8BackUSBPwrStatus;
1803 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1804 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1805 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1806 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1807
1808 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "[%s][%d]\n", __FUNCTION__, __LINE__);
1809
1810 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u32PNL_MISC = %x\n", (unsigned int)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC);
1811 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "bPanelOn = %x\n", bPanelOn);
1812 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "eLPLL_Type = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type);
1813 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "_u8MOD_LVDS_Pair_Type = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
1814 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
1815 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
1816 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
1817
1818 MS_U16 u16PortA = MOD_R2BYTE(REG_MOD_BK00_6D_L);
1819 MS_U16 u16PortB = MOD_R2BYTE(REG_MOD_BK00_6E_L);
1820
1821 if(u16PortA!=0)
1822 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_R2BYTE(REG_MOD_BK00_6D_L);
1823 if(u16PortB!=0)
1824 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_R2BYTE(REG_MOD_BK00_6E_L);
1825
1826 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "==========================\n\n");
1827 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
1828 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
1829 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
1830
1831 if(bPanelOn)
1832 {
1833 // The order is PanelVCC -> delay pnlGetOnTiming1() -> VOP -> MOD
1834 // VOP
1835 SC_W2BYTEMSK(0,REG_SC_BK10_46_L, 0x4000, HBMASK);
1836
1837 // mod power on
1838 MHal_MOD_PowerOn(pInstance
1839 , ENABLE
1840 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
1841 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
1842 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
1843 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
1844 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
1845
1846 // turn on LPLL
1847 MHal_PNL_PowerDownLPLL(pInstance,FALSE);
1848
1849 #if ENABLE_MODE_PATCH
1850 MOD_W2BYTE(REG_MOD_BK00_33_L, 0x0039);
1851 MsOS_DelayTask(5);
1852 MOD_W2BYTEMSK(REG_MOD_BK00_33_L, BIT(8), BIT(8));
1853 MOD_W2BYTEMSK(REG_MOD_BK00_33_L, BIT(9), BIT(9));
1854 #endif
1855
1856 if(bCalEn)
1857 {
1858
1859 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
1860
1861 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
1862
1863 u8Cab = msModCurrentCalibration(pInstance);
1864
1865 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
1866
1867 }
1868 if(!MHal_PNL_MOD_Control_Out_Swing(pInstance,_u16PnlDefault_SwingLevel))
1869 printf(">>Swing Level setting error!!\n");
1870 }
1871 else
1872 {
1873 // The order is LPLL -> MOD -> VOP -> delay for MOD power off -> turn off VCC
1874
1875 // LPLL
1876 // MHal_PNL_PowerDownLPLL(TRUE); //Remove to keep op vsync if panel off
1877
1878 MHal_MOD_PowerOn(pInstance
1879 , DISABLE
1880 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
1881 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
1882 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
1883 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
1884 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
1885 // VOP
1886 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS ||
1887 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_I ||
1888 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_P)//(bIsLVDS)
1889 SC_W2BYTEMSK(0,REG_SC_BK10_46_L, 0xFF, LBMASK);
1890 else
1891 SC_W2BYTEMSK(0,REG_SC_BK10_46_L, 0x00, 0xFF);
1892 }
1893
1894 return E_PNL_OK;
1895 }
1896
MHal_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)1897 void MHal_PNL_SetOutputPattern(void *pInstance,MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
1898 {
1899 if (bEnable)
1900 {
1901 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF);
1902 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF);
1903 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF);
1904 MsOS_DelayTask(10);
1905 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15));
1906 }
1907 else
1908 {
1909 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15));
1910 }
1911
1912 }
1913
MHal_PNL_Switch_LPLL_SubBank(void * pInstance,MS_U16 u16Bank)1914 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance,MS_U16 u16Bank)
1915 {
1916 UNUSED(u16Bank);
1917 }
1918
MHal_PNL_Switch_TCON_SubBank(void * pInstance,MS_U16 u16Bank)1919 void MHal_PNL_Switch_TCON_SubBank(void *pInstance,MS_U16 u16Bank)
1920 {
1921 W2BYTEMSK(L_BK_TCON(0x00), u16Bank&0xff, 0xFF);
1922 }
1923
MHal_PNL_Read_TCON_SubBank(void * pInstance)1924 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance)
1925 {
1926 return (MS_U16)R2BYTEMSK(L_BK_TCON(0x00),0xFF);
1927 }
1928
MHal_PNL_IsYUVOutput(void * pInstance)1929 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance)
1930 {
1931 return FALSE;
1932 }
1933
MHal_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1934 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1935 {
1936 }
MHal_PNL_Set_Device_Bank_Offset(void * pInstance)1937 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance)
1938 {
1939 UNUSED(pInstance);
1940 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM);
1941 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg bank offset
1942 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg bank offset
1943 }
MHal_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)1944 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
1945 {
1946 return TRUE;
1947 }
MHal_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)1948 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
1949 {
1950 }
MHal_PNL_Init(void * pInstance)1951 void MHal_PNL_Init(void *pInstance)
1952 {
1953 // Do nothing
1954 UNUSED(pInstance);
1955 }
1956
MHal_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)1957 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
1958 {
1959 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1960 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1961
1962 if (bEnable == TRUE)
1963 {
1964 //interlace output vtotal modify
1965 SC_W2BYTEMSK(0, REG_SC_BK0F_2A_L, BIT(5)|BIT(8), BIT(5)|BIT(8));
1966 // two different interlace information through channel A reserved bit
1967 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7));
1968 // two different interlace information through channel B reserved bit
1969 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11));
1970 }
1971 else
1972 {
1973 SC_W2BYTEMSK(0, REG_SC_BK0F_2A_L, 0x00, BIT(5)|BIT(8));
1974 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0x00, BIT(4) | BIT(7));
1975 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x00, BIT(10)|BIT(11));
1976 }
1977
1978 return TRUE;
1979 }
1980
MHal_PNL_GetOutputInterlaceTiming(void * pInstance)1981 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance)
1982 {
1983 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1984 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1985
1986 MS_BOOL bIsInterlaceOutput = FALSE;
1987 //interlace output vtotal modify
1988 if (SC_R2BYTEMSK(0, REG_SC_BK0F_2A_L, BIT(5)|BIT(8)) == (BIT(5)|BIT(8)))
1989 {
1990 if ((MOD_R2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7)) == (BIT(4) | BIT(7)))
1991 || (MOD_R2BYTEMSK(REG_MOD_BK00_42_L, BIT(10) | BIT(11)) == (BIT(10)|BIT(11))))
1992 {
1993 bIsInterlaceOutput = TRUE;
1994 }
1995 }
1996 else
1997 {
1998 bIsInterlaceOutput = FALSE;
1999 }
2000 return bIsInterlaceOutput;
2001 }
2002
MHal_PNL_GetPanelVStart(void)2003 MS_U16 MHal_PNL_GetPanelVStart(void)
2004 {
2005 return 0;
2006 }
2007
MHal_Pnl_Get_SupportMaxDclk(void * pInstance)2008 MS_U16 MHal_Pnl_Get_SupportMaxDclk(void *pInstance)
2009 {
2010 return 0;
2011 }
2012 #endif
2013
2014