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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_PNL_H_ 103 #define _HAL_PNL_H_ 104 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 #ifdef _HAL_PNL_C_ 110 #define HAL_PNL_INTERFACE 111 #else 112 #define HAL_PNL_INTERFACE extern 113 #endif 114 115 // Current platform is DAC out or not 116 #define IS_DAC_OUT FALSE 117 118 // XC register serpead define 119 #define XC_REGISTER_SPREAD 1 120 #define SUPPORT_FRC 0 121 122 123 //------------------------------------------------------------------------------------------------- 124 // Driver Capability 125 //------------------------------------------------------------------------------------------------- 126 #define GAMMA_10BIT BIT(0) ///< gamma value range up to 10 BIt 127 #define GAMMA_12BIT BIT(1) ///< gamma value range up to 12 BIT 128 129 #define GAMMA_8BIT_MAPPING BIT(0) ///< mapping GAMMA value to 256 sampline entries 130 #define GAMMA_10BIT_MAPPING BIT(1) ///< mapping GAMMA value to 1024 sampling entries 131 132 typedef struct 133 { 134 MS_U8 eSupportGammaType; ///< refer to HAL_PNL_GAMMA_TYPE 135 MS_U8 eSupportGammaMapMode; ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE 136 } PNL_HalInfo; 137 138 #define SUPPORT_OVERDRIVE 0 139 #define GAMMA_TYPE (GAMMA_10BIT | GAMMA_12BIT) 140 #define GAMMA_MAPPING (GAMMA_8BIT_MAPPING | GAMMA_10BIT_MAPPING) 141 #define SUPPORT_SYNC_FOR_DUAL_MODE TRUE //New feature after T7 142 #define ENABLE_Auto_ModCurrentCalibration 1 143 #define ENABLE_MODE_PATCH 0 144 #define PNL_SUPPORT_DEVICE_NUM 1 145 146 // MIU Word (Bytes) 147 #define BYTE_PER_WORD (16) 148 149 #define SUPPORT_TCON TRUE 150 //------------------------------------------------------------------------------------------------- 151 // Macro and Define 152 //------------------------------------------------------------------------------------------------- 153 154 155 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 156 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 157 158 // NONPM 159 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF 160 #if XC_REGISTER_SPREAD 161 #define REG_SCALER_BASE 0x130000 162 #else 163 #define REG_SCALER_BASE 0x102F00 164 #endif 165 #define REG_HDGEN_BASE 0x103000 166 #define REG_LPLL_BASE 0x103100 167 #define REG_MOD_BASE 0x103200 168 #define REG_UTMI1_BASE 0x103A00 169 170 #define REG_CHIP_REVISION 0x1ECF 171 172 #define REG_CLKGEN0_BASE 0x100B00 173 #define REG_CLKGEN1_BASE 0x103300 174 175 /* TCON */ 176 #define L_BK_TCON(x) BK_REG_L(REG_HDGEN_BASE, x) 177 #define H_BK_TCON(x) BK_REG_H(REG_HDGEN_BASE, x) 178 179 /* LPLL */ 180 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 181 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 182 183 /* UTMI1 */ 184 #define L_BK_UTMI1(x) BK_REG_L(REG_UTMI1_BASE, x) 185 #define H_BK_UTMI1(x) BK_REG_H(REG_UTMI1_BASE, x) 186 #define REG_CLKGEN0_4F_L (REG_CHIPTOP_BASE + 0x9E) 187 188 #define REG_CLKGEN0_52_L (REG_CHIPTOP_BASE + 0xA4) 189 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) 190 #define REG_CLKGEN0_57_L (REG_CHIPTOP_BASE + 0xAE) 191 #define REG_CLKGEN0_58_L (REG_CHIPTOP_BASE + 0xB0) 192 #define REG_CLKGEN0_5B_L (REG_CHIPTOP_BASE + 0xB6) 193 #define REG_CLKGEN0_5E_L (REG_CHIPTOP_BASE + 0xBC) 194 195 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 196 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 197 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 198 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 199 200 #define XC_PAFRC_DITH_NOISEDITH_EN (0x00) 201 #define XC_PAFRC_DITH_TAILCUT_DISABLE (0x00) 202 203 #define LVDS_DUAL_OUTPUT 0 204 #define LVDS_DUAL_OUTPUT_SPECIAL 1// only for use with T8 board 205 #define LVDS_SINGLE_OUTPUT_A 2 206 #define LVDS_SINGLE_OUTPUT_B 3 207 #define LVDS_OUTPUT_User 4 208 209 // SCALER CLK select 210 #define REG_CKG_ODCLK REG_CLKGEN0_53_L 211 #define CKG_ODCLK_GATED BIT(0) 212 #define CKG_ODCLK_INVERT BIT(1) 213 #define CKG_ODCLK_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2)) 214 #define CKG_ODCLK_CLK_SC_PLL (0 << 2) 215 #define CKG_ODCLK_CLK_LPLL_DIV2 (5 << 2) 216 #define CKG_ODCLK_27M (6 << 2) 217 #define CKG_ODCLK_CLK_LPLL (7 << 2) 218 219 #define REG_CKG_BT656 REG_CLKGEN0_53_L 220 #define CKG_BT656_GATED BIT(8) 221 #define CKG_BT656_INVERT BIT(9) 222 #define CKG_BT656_MASK (BIT(13) | BIT(12) | BIT(11) | BIT(10)) 223 #define CKG_BT656_CLK_SC_PLL (0 << 10) 224 #define CKG_BT656_CLK_LPLL_DIV_2 (5 << 10) 225 #define CKG_BT656_27M (6 << 10) 226 #define CKG_BT656_CLK_LPLL (7 << 10) 227 228 #define REG_CKG_TX_MOD REG_CLKGEN0_58_L 229 #define CKG_TX_MOD_GATED BIT(0) 230 #define CKG_TX_MOD_INVERT BIT(1) 231 #define CKG_TX_MOD_MASK (BIT(3) | BIT(2)) 232 #define CKG_TX_1X_4XDIGITAL (0 << 2) 233 234 #define PANEL_LPLL_INPUT_DIV_1st 0x00 235 #define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 236 #define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8 237 #define PANEL_LPLL_LOOP_DIV_2nd 0x01 // 238 #define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 239 #define PANEL_LPLL_OUTPUT_DIV_2nd 0x00 240 #define LPLL_LOOPGAIN 16 // use at MHal_PNL_Get_LPLL_LoopGain() 241 242 #define LVDS_MPLL_CLOCK_MHZ 432 // For crystal 24Mhz 243 #define LVDS_SPAN_FACTOR 131072 244 245 #define VOP_DE_HSTART_MASK (0x1FFF) //BK_10_04 246 #define VOP_DE_HEND_MASK (0x1FFF) //BK_10_05 247 #define VOP_DE_VSTART_MASK (0x0FFF) //BK_10_06 248 #define VOP_DE_VEND_MASK (0x0FFF) //BK_10_07 249 250 #define VOP_VTT_MASK (0x0FFF) //BK_10_0D 251 #define VOP_HTT_MASK (0x1FFF) //BK_10_0C 252 253 #define VOP_VSYNC_END_MASK (0x0FFF) //BK_10_03 254 #define VOP_DISPLAY_HSTART_MASK (0x1FFF) //BK_10_08 255 #define VOP_DISPLAY_HEND_MASK (0x1FFF) //BK_10_09 256 #define VOP_DISPLAY_VSTART_MASK (0x0FFF) //BK_10_0A 257 #define VOP_DISPLAY_VEND_MASK (0x0FFF) //BK_10_0B 258 259 260 //------------------------------------------------------------------------------------------------- 261 // Type and Structure 262 //------------------------------------------------------------------------------------------------- 263 typedef enum 264 { 265 E_HALPNL_DEVICE0_XC_BANK_OFFSET = 0, 266 E_HALPNL_DEVICE1_XC_BANK_OFFSET = 0 267 }PNL_HAL_DEVICE_XC_BANK_OFFSET; 268 269 typedef enum 270 { 271 E_DRVPNL_ALLIN_MODE = 1, 272 E_DRVPNL_2X_MODE = 2, 273 E_DRVPNL_SEPARATE_MODE = 3, 274 E_DRVPNL_TYPE_NUM 275 }DRVPNL_OUT_SWING_TYPE; 276 277 typedef enum 278 { 279 HAL_TI_10BIT_MODE = 0, 280 HAL_TI_8BIT_MODE = 2, 281 HAL_TI_6BIT_MODE = 3, 282 } PNL_HAL_TIMODES; 283 284 //------------------------------------------------------------------------------------------------- 285 // Function and Variable 286 //------------------------------------------------------------------------------------------------- 287 HAL_PNL_INTERFACE MS_U32 gu32PnlRiuBaseAddr; 288 HAL_PNL_INTERFACE MS_U32 gu32PMRiuBaseAddr; 289 290 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 291 void MHal_PNL_TCON_Init(void *pInstance); 292 293 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 294 295 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type); 296 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 297 void MHal_Output_Channel_Order(void *pInstance, MS_U8 Type, MS_U16 u16OutputOrder0_3, MS_U16 u16OutputOrder4_7, MS_U16 u16OutputOrder8_11, MS_U16 u16OutputOrder12_13); 298 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance); 299 300 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 301 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance); 302 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping); 303 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue); 304 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue); 305 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); 306 #define Hal_PNL_Get12BitGammaPerChannel(args...) 307 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz); 308 //void _MDrv_PNL_Set_12BIT_Gamma( MS_U8 u8Channel, MS_U8 * u8Tab ); 309 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U32 ldHz); 310 311 #define MHal_PNL_FRC_lpll_src_sel(args...) 312 313 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U32 ldHz); 314 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance); 315 316 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 317 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 318 void MHal_PNL_OverDriver_Init(void *pInstance, MS_U32 u32OD_MSB_Addr, MS_U32 u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit); 319 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 320 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]); 321 322 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 323 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance); 324 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 325 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 326 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level); 327 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level); 328 329 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData); 330 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData); 331 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask); 332 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 333 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 334 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance); 335 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); 336 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 337 338 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank); 339 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U32 ldHz); 340 341 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank); 342 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance); 343 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance); 344 345 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 346 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 347 348 /// Set pair swap for user mode 349 #define MHal_FRC_MOD_PairSwap_UserMode(args...) 350 351 #define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC 352 353 #define MHal_PNL_CalExtLPLLSETbyDClk(args...) 354 355 #define MHal_PNL_VBY1_Handshake(args...) TRUE 356 #define MHal_PNL_VBY1_OC_Handshake(args...) TRUE 357 358 359 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable); 360 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance); 361 #define MHal_PNL_SetOSDCOutputType(args...) 362 363 #define MHal_PNL_Set_T3D_Setting(args...) 364 365 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance); 366 void MHal_PNL_Init(void *pInstance); 367 #define MHal_PNL_ChannelFIFOPointerADjust(args...) 368 MS_U16 MHal_Pnl_Get_SupportMaxDclk(void *pInstance); 369 MS_U16 MHal_PNL_GetPanelVStart(void); 370 #ifdef __cplusplus 371 } 372 #endif 373 374 #endif // _HAL_PNL_H_ 375 376