1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 //==============================================================================
95 // [mhal_sc.c]
96 // Date: 20081203
97 // Descriptions: Add a new layer for HW setting
98 //==============================================================================
99 #define MHAL_SC_C
100
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <asm/div64.h>
103 #else
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106 #include "UFO.h"
107
108 // Common Definition
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 #include "mhal_xc_chip_config.h"
113 #include "utopia.h"
114 #include "utopia_dapi.h"
115 #include "xc_hwreg_utility2.h"
116 #include "xc_Analog_Reg.h"
117 #include "drvXC_IOPort.h"
118 #include "apiXC.h"
119 #include "drv_sc_display.h"
120 #include "drv_sc_isr.h"
121 #include "apiXC_Adc.h"
122 #include "apiXC_PCMonitor.h"
123 #include "apiXC_ModeParse.h"
124 #include "apiXC_Auto.h"
125 #include "drvXC_HDMI_if.h"
126 #include "mvideo_context.h"
127 #include "drv_sc_ip.h"
128 #include "mhal_dynamicscaling.h"
129 #include "mdrv_sc_dynamicscaling.h"
130 #include "drvXC_HDMI_Internal.h"
131 #include "drvMVOP.h"
132
133 #if (LD_ENABLE==1)
134 #include "mdrv_ld.h"
135 #include "mdrv_ldalgo.h"
136 #endif
137 #include "mdrv_sc_3d.h"
138 #include "drv_sc_menuload.h"
139 #include "drvXC_ADC_Internal.h"
140 #include "mhal_sc.h"
141 #if FRC_INSIDE
142 #include "mdrv_frc.h"
143 #include "mhal_frc.h"
144 #endif
145 #include "XC_private.h"
146 #include "mhal_menuload.h"
147 #include "halCHIP.h"
148 #include "drvSYS.h"
149 #include "drv_sc_scaling.h"
150 #include "drvSEAL.h"
151
152 #ifndef DONT_USE_CMA
153 #if (XC_SUPPORT_CMA ==TRUE)
154 #ifdef MSOS_TYPE_LINUX_KERNEL
155 #include "drvCMAPool_v2.h"
156 #else
157 #include "drvCMAPool.h"
158 #endif
159 #include "msos/linux/mdrv_cma_pool_st.h"
160 #include "drvMIU.h"
161 #endif
162 #endif
163 #if ((defined (ANDROID) || defined(MSOS_TYPE_LINUX_KERNEL)) && defined(UFO_XC_DS_PQ))
164 #include "drvPQ_Define.h"
165 #endif
166 //#include <assert.h>
167 #ifdef ANDROID
168 #include <cutils/log.h>
169 #ifndef LOGE
170 #define printf(format, args...) ALOGE(format, ##args);
171 #else
172 #define printf(format, args...) LOGE(format, ##args);
173 #endif
174 #endif
175
176 #define DBG_EN 0
177 #if DBG_EN
178 #define SC_DBG(x) x
179 #define FPLL_DBG(x) x
180 #else
181 #define SC_DBG(x)
182 #define FPLL_DBG(x)
183 #endif
184 #define new_chakra
185
186 #define MIU_SEL_USE_XC_INTERNAL TRUE
187
188 //==============================================================================
189 //==============================================================================
190 MS_VIRT _XC_RIU_BASE;
191 MS_VIRT _PM_RIU_BASE;
192
193 MS_VIRT _DVI_ATOP_RIU_BASE;
194 MS_VIRT _DVI_DTOP_RIU_BASE;
195 MS_VIRT _HDCP_RIU_BASE;
196 MS_VIRT _DVI_EQ_RIU_BASE;
197 MS_VIRT _ADC_DTOPB_RIU_BASE;
198
199 MS_VIRT _DDC_RIU_BASE;
200 MS_VIRT _PM_SLEEP_RIU_BASE;
201
202 MS_U32 u32DTVPatchTimer;
203 MS_BOOL bPreFDMaskStatse;
204 MS_U16 u16FDMaskCount;
205
206 #ifndef DONT_USE_CMA
207 #if (XC_SUPPORT_CMA ==TRUE)
208 MS_U32 u32CMAPatchTimer_Main ;
209 #endif
210 #endif
211
212 #define TGEN_SC0_DLY 11
213 #define TGEN_SC0_USER_MODE_DLY 3
214 #define VIP_SC0_V_DLY 2
215 #define VIP_SC0_H_DLY 150
216 #define VIP_SC0_USER_MODE_V_DLY (SC_R2BYTEMSK(0, REG_SC_BK68_51_L, 0x1FFF))
217 #define VIP_SC0_USER_MODE_H_DLY ((SC_R2BYTEMSK(0, REG_SC_BK68_52_L, 0x3FFF))/2)
218 #define SC1_PRE_RUN_DLY ((SC_R2BYTEMSK(0, REG_SC_BK10_0C_L, 0x3FFF)+1)/4)
219 #define VIP_SC1_V_DLY 2
220 #define VIP_SC1_H_DLY 61
221
222 #ifdef UFO_XC_AUTO_DOWNLOAD
223 #define DEBUG_HDR 0
224 #define AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR 512
225 #define AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR 4944
226
227 // HDR client of auto download has these following formats, include format0 and format1.
228 //
229 // Format0:
230 //127 125 116 115 112 60 57 0
231 // | [x[2]] | [addr(10)] | 0 | [sel0(3)] | [data1] | sel1(3) | [data0] |
232 // sel0 = 1 x(52) sel1 = 1 wd0(19),wd1(19),wd2(19)
233 // sel0 = 2 x(4),wd0(16),wd1(16),wd2(16) sel1 = 2 x(9),wd0(16),wd1(16),wd2(16)
234 // sel0 = 3 x(40),wd0(12) sel1 = 3 x(45),wd0(12)
235 // sel0 = 4 idx(4),wd0(16),wd1(16),wd2(16) sel1 = 4 x(5),idx(4),wd0(16),wd1(16),wd2(16)
236 // sel: 0: disable
237 // 1: De-gamma
238 // 2: Gamma
239 // 3: TMO
240 // 4: 3D-lut
241
242 // Format1:
243 //127 125 116 115 112 60 57 0
244 // | [x[2]] | [addr(10)] | 1 | [ctrl0(3)] | [data1] | sel1(3) | [data0] |
245 // x(52) sel1 = 0
246 // idx(4),wd0(16),wd1(16),wd2(16) sel1 = 4 x(10),degam(19),gam(16),tmo(16)
247 // ctrl: bit: 114 113 112
248 // |degam|gam|tmo|
249 // sel: 0: disable
250 // 4: 3D-lut
251 //
252 // HW designer recommand using format1.
253 // These following definitions write datas of tmo/gamma/de-gamma/3d-lut separately by format1,
254 // please refer to definition of WRITE_TMO_DATA_FORMAT_1, WRITE_GAMMA_DATA_FORMAT_1, WRITE_DEGAMMA_DATA_FORMAT_1 and WRITE_3DLUT_DATA_FORMAT_1.
255 #define WRITE_TMO_DATA_FORMAT_1(baseaddr, index, value) \
256 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
257 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x09);\
258 *(baseaddr + 14) = ((*(baseaddr + 14) & 0xF0) | (((value) >> 8) & 0x0F));\
259 *(baseaddr + 15) = ((value) & 0xFF);
260
261 #define WRITE_GAMMA_DATA_FORMAT_1(baseaddr, index, value) \
262 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
263 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x0A);\
264 *(baseaddr + 14) = ((*(baseaddr + 14) & 0x0F) | (((value) << 4) & 0xF0));\
265 *(baseaddr + 13) = (((value) >> 4) & 0xFF);\
266 *(baseaddr + 12) = ((*(baseaddr + 12) & 0xF0) | (((value) >> 12) & 0x0F));
267
268 #define WRITE_DEGAMMA_DATA_FORMAT_1(baseaddr, index, value) \
269 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
270 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x0C);\
271 *(baseaddr + 12) = ((*(baseaddr + 12) & 0x0F) | (((value) << 4) & 0xF0));\
272 *(baseaddr + 11) = (((value) >> 4) & 0xFF);\
273 *(baseaddr + 10) = ((*(baseaddr + 10) & 0x80) | (((value) >> 12) & 0x7F));
274
275 #define WRITE_3DLUT_DATA_FORMAT_1(baseaddr, index, subindex, rval, gval, bval) \
276 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
277 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x08);\
278 *(baseaddr + 8) = ((*(baseaddr + 8) & 0xF1) | 0x08);\
279 *(baseaddr + 8) = ((*(baseaddr + 8) & 0x0F) | (((bval) << 4) & 0xF0));\
280 *(baseaddr + 7) = (((bval) >> 4) & 0xFF);\
281 *(baseaddr + 6) = ((*(baseaddr + 6) & 0xF0) | (((bval) >> 12) & 0x0F));\
282 *(baseaddr + 6) = ((*(baseaddr + 6) & 0x0F) | (((gval) << 4) & 0xF0));\
283 *(baseaddr + 5) = (((gval) >> 4) & 0xFF);\
284 *(baseaddr + 4) = ((*(baseaddr + 4) & 0xF0) | (((gval) >> 12) & 0x0F));\
285 *(baseaddr + 4) = ((*(baseaddr + 4) & 0x0F) | (((rval) << 4) & 0xF0));\
286 *(baseaddr + 3) = (((rval) >> 4) & 0xFF);\
287 *(baseaddr + 2) = ((*(baseaddr + 2) & 0xF0) | (((rval) >> 12) & 0x0F));\
288 *(baseaddr + 2) = ((*(baseaddr + 2) & 0x0F) | (((subindex) << 4) & 0xF0));
289
290 // The following definition clear bits of format1's ctrl & sel.
291 #define CLEAR_HDR_DATA_FORMAT_1(baseaddr) \
292 *(baseaddr + 1) = ((*(baseaddr + 1)) & 0xF8);\
293 *(baseaddr + 8) = (*(baseaddr + 8) & 0xF1);
294
295 static MS_U32 _au32_3dlut_entry_num[8] = {736, 656, 656, 576, 656, 576, 576, 512};
296 #endif
297
298 // Put this function here because hwreg_utility2 only for hal.
Hal_SC_init_riu_base(MS_VIRT u32riu_base,MS_VIRT u32PMriu_base)299 void Hal_SC_init_riu_base(MS_VIRT u32riu_base, MS_VIRT u32PMriu_base)
300 {
301 _XC_RIU_BASE = u32PMriu_base;
302 _PM_RIU_BASE = u32PMriu_base;
303
304
305 _DVI_ATOP_RIU_BASE = u32PMriu_base;
306 _DVI_DTOP_RIU_BASE = u32PMriu_base;
307 _HDCP_RIU_BASE = u32PMriu_base;
308 _DVI_EQ_RIU_BASE = u32PMriu_base;
309 _ADC_DTOPB_RIU_BASE = u32PMriu_base;
310
311 _DDC_RIU_BASE =u32PMriu_base;
312 _PM_SLEEP_RIU_BASE =u32PMriu_base;
313
314 }
315
316 //=========================================================//
317 // Function : Hal_SC_setfield
318 // Description:
319 //=========================================================//
Hal_SC_setfield(void * pInstance,MS_U16 reg_1D,MS_U16 reg_21,MS_U16 reg_23,SCALER_WIN eWindow)320 void Hal_SC_setfield(void *pInstance, MS_U16 reg_1D, MS_U16 reg_21, MS_U16 reg_23, SCALER_WIN eWindow )
321 {
322 //printf("reg_1D=%x, reg_21=%x, reg_23=%x\n", reg_1D, reg_21, reg_23);
323 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
324 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
325
326 if( eWindow == MAIN_WINDOW )
327 {
328 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_1D_L, (reg_1D<<8), 0xEF00);
329 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, reg_21, 0x3FFF);
330 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_23_L, (reg_23<<8), HBMASK);
331 }
332 else
333 {
334 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_1D_L, (reg_1D<<8), 0xEF00);
335 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_21_L, reg_21, 0x3FFF);
336 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_23_L, (reg_23<<8), HBMASK);
337 }
338 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_1D_L, HBMASK));
339 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_21_L, 0x3FFF));
340 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_23_L, HBMASK));
341
342 // printf("%x ",SC_R4BYTE(REG_SC_BK01_21_L));
343 // printf("%x ",SC_R4BYTE(REG_SC_BK01_23_L));
344 }
345
346 //=========================================================//
347 // Function : Hal_SC_de_only_en
348 // Description: DE Only. HSYNC and VSYNC are ignored.
349 //#0: Disable.
350 //#1: Enable.
351 //=========================================================//
Hal_SC_de_only_en(void * pInstance,MS_BOOL benable,SCALER_WIN eWindow)352 void Hal_SC_de_only_en(void *pInstance, MS_BOOL benable, SCALER_WIN eWindow)
353 {
354 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
355 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
356 if(eWindow == MAIN_WINDOW)
357 {
358 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, (benable ? BIT(6):0), BIT(6));
359 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patch for HDMI switch, Auto search HST jistter mask filter force off
360 }
361 else
362 {
363 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, (benable ? BIT(6):0), BIT(6));
364 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patch for HDMI switch, Auto search HST jistter mask filter force off
365 }
366 }
367
368 //=========================================================//
369 // Function : Hal_SC_de_direct_en
370 // Description: Digital Input Horizontal Sample Range
371 //#0: Use DE as sample range, only V position can be adjusted.
372 //#1: Use SPRHST and SPRHDC as sample range, both H and V position can be adjusted.
373 //=========================================================//
Hal_SC_de_direct_en(void * pInstance,MS_BOOL benable,SCALER_WIN eWindow)374 void Hal_SC_de_direct_en(void *pInstance, MS_BOOL benable, SCALER_WIN eWindow)
375 {
376 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
377 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
378 if(eWindow == MAIN_WINDOW)
379 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, (benable ? BIT(7):0), BIT(7));
380 else
381 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, (benable ? BIT(7):0), BIT(7));
382
383 }
384
Hal_SC_set_ficlk(void * pInstance,MS_BOOL bPreDown,SCALER_WIN eWindow)385 void Hal_SC_set_ficlk(void *pInstance, MS_BOOL bPreDown, SCALER_WIN eWindow)
386 {
387 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
388 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
389 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
390 {
391 // manhattan is not needed it
392 }
393 else //E_XC_DEVICE1 == psXCInstPri->u32DeviceID
394 {
395 if (bPreDown)
396 {
397 W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk
398 }
399 else
400 {
401 W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk
402 }
403 }
404 }
405
Hal_SC_set_shiftline(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)406 void Hal_SC_set_shiftline(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow )
407 {
408 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
409 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
410 if( eWindow == MAIN_WINDOW )
411 {
412 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_2F_L, (u8Val & 0x07)<<8, (BIT(10)|BIT(9)|BIT(8)));
413 }
414 else
415 {
416 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_2F_L, (u8Val & 0x03)<<13, (BIT(14)|BIT(13)));
417 }
418 }
419
Hal_SC_set_422_cbcr_swap(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)420 void Hal_SC_set_422_cbcr_swap(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
421 {
422 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
423 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
424 if(eWindow == MAIN_WINDOW)
425 {
426 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_0A_L, bEnable ? BIT(6) : 0, BIT(6));
427 }
428 else
429 {
430 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_0A_L, bEnable ? BIT(6) : 0, BIT(6));
431 }
432 }
433
Hal_SC_set_pre_align_pixel(void * pInstance,MS_BOOL bEnable,MS_U16 pixels,SCALER_WIN eWindow)434 void Hal_SC_set_pre_align_pixel(void *pInstance, MS_BOOL bEnable, MS_U16 pixels, SCALER_WIN eWindow)
435 {
436 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
437 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
438 if (bEnable)
439 {
440 if ( eWindow == MAIN_WINDOW )
441 {
442 // Enable pre align pixel for mirror mode.
443 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, BIT(15), BIT(15));
444
445 // Number of pixels need to be inserted. (U3 has 15 pixels)
446 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, pixels << 8 , 0x1F00);
447 }
448 else
449 {
450 // Enable pre align pixel for mirror mode.
451 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, BIT(15), BIT(15));
452
453 // Number of pixels need to be inserted. (U3 has 15 pixels)
454 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, pixels << 8 , 0x1F00);
455 }
456
457 }
458 else
459 {
460 if ( eWindow == MAIN_WINDOW )
461 {
462 // Disable pre align pixel for mirror mode.
463 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, 0x00 , BIT(15));
464 }
465 else
466 {
467 // Disable pre align pixel for mirror mode.
468 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, 0x00 , BIT(15));
469 }
470 }
471 }
472
Hal_SC_get_pre_align_pixel(void * pInstance,SCALER_WIN eWindow)473 MS_BOOL Hal_SC_get_pre_align_pixel(void *pInstance, SCALER_WIN eWindow)
474 {
475 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
476 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
477 if ( eWindow == MAIN_WINDOW )
478 {
479 // Check pre align pixel.
480 return ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, BIT(15))) ? TRUE:FALSE;
481 }
482 else
483 {
484 // Check pre align pixel.
485 return ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, BIT(15))) ? TRUE:FALSE;
486 }
487 }
488
Hal_XC_Set_FreeFRCMD(void * pInstance,MS_BOOL bEnable)489 void Hal_XC_Set_FreeFRCMD(void *pInstance, MS_BOOL bEnable)
490 {
491 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
492 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
493 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, bEnable? BIT(5) : 0, BIT(5));
494 }
495
496 // Obsolete in M10/J2/A5
Hal_SC_set_linearmem_mode(MS_BOOL bEnable,SCALER_WIN eWindow)497 void Hal_SC_set_linearmem_mode(MS_BOOL bEnable, SCALER_WIN eWindow)
498 {
499 }
500
501 // This function will return 8/10/12/14/16 field mode or 8 frame mode.
502 // Otherwise it return IMAGE_STORE_2_FRAMES
Hal_SC_GetFrameStoreMode(void * pInstance,SCALER_WIN eWindow)503 XC_FRAME_STORE_NUMBER Hal_SC_GetFrameStoreMode(void *pInstance, SCALER_WIN eWindow)
504 {
505 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
506 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
507 MS_U16 u16FrameCount = 0x00;
508 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
509 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
510 if (eWindow == MAIN_WINDOW)
511 {
512 u16FrameCount = 0x1F & SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L);
513 }
514 else
515 {
516 u16FrameCount = 0x1F & SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L);
517 }
518
519 switch( u16FrameCount) // Get field type.
520 {
521 default:
522 if (gSrcInfo[MAIN_WINDOW].bInterlace)
523 {
524 return IMAGE_STORE_4_FIELDS;
525 }
526 else
527 {
528 return IMAGE_STORE_2_FRAMES;
529 }
530 case 3:
531 return IMAGE_STORE_3_FRAMES;
532 case 4:
533 if (gSrcInfo[MAIN_WINDOW].bInterlace)
534 {
535 return IMAGE_STORE_4_FIELDS;
536 }
537 else
538 {
539 return IMAGE_STORE_4_FRAMES;
540 }
541 case 6:
542 if (gSrcInfo[MAIN_WINDOW].bInterlace)
543 {
544 return IMAGE_STORE_6_FIELDS;
545 }
546 else
547 {
548 return IMAGE_STORE_6_FRAMES;
549 }
550 case 8:
551 if (gSrcInfo[MAIN_WINDOW].bInterlace)
552 {
553 return IMAGE_STORE_8_FIELDS;
554 }
555 else
556 {
557 return IMAGE_STORE_8_FRAMES;
558 }
559 case 10:
560 return IMAGE_STORE_10_FIELDS;
561 case 12:
562 if (gSrcInfo[MAIN_WINDOW].bInterlace)
563 {
564 return IMAGE_STORE_12_FIELDS;
565 }
566 else
567 {
568 return IMAGE_STORE_12_FRAMES;
569 }
570 case 14:
571 return IMAGE_STORE_14_FIELDS;
572 case 16:
573 return IMAGE_STORE_16_FIELDS;
574
575 }
576
577 return IMAGE_STORE_UNDEFINE;
578 }
579
Hal_SC_set_wr_bank_mapping(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)580 void Hal_SC_set_wr_bank_mapping(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
581 {
582 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
583 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
584 SC_DBG(printf("Set WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
585
586 if( eWindow == MAIN_WINDOW )
587 {
588 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
589 }
590 else
591 {
592 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
593 }
594 }
595
Hal_SC_set_frcm_wr_bank_mapping(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)596 void Hal_SC_set_frcm_wr_bank_mapping(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
597 {
598 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
599 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
600 SC_DBG(printf("Set WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
601
602 if( eWindow == MAIN_WINDOW )
603 {
604 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_07_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
605 }
606 else
607 {
608 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_47_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
609 }
610 }
611
Hal_SC_set_wr_bank_mapping_num(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)612 void Hal_SC_set_wr_bank_mapping_num(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
613 {
614 Hal_SC_set_wr_bank_mapping(pInstance, u8Val, eWindow);
615 }
616
Hal_SC_Get_WR_Bank_Mapping(void * pInstance,SCALER_WIN eWindow)617 MS_U8 Hal_SC_Get_WR_Bank_Mapping(void *pInstance, SCALER_WIN eWindow)
618 {
619 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
620 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
621 MS_U8 u8val = 0;
622
623 if( eWindow == MAIN_WINDOW )
624 {
625 u8val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(15)|BIT(14)|BIT(13)) >> 13;
626 }
627 else
628 {
629 u8val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(15)|BIT(14)|BIT(13)) >> 13;
630 }
631 SC_DBG(printf("Get WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
632 return u8val;
633 }
634
Hal_SC_Get_WR_Bank_Mapping_Num(void * pInstance,SCALER_WIN eWindow)635 MS_U8 Hal_SC_Get_WR_Bank_Mapping_Num(void *pInstance, SCALER_WIN eWindow)
636 {
637 return Hal_SC_Get_WR_Bank_Mapping(pInstance, eWindow);
638 }
639
Hal_SC_set_csc(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)640 void Hal_SC_set_csc(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow )
641 {
642 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
643 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
644 if( eWindow == MAIN_WINDOW )
645 {
646 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, (bEnable ? BIT(3):0), BIT(3));
647 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_01_L, (bEnable ? BIT(2):0), BIT(2));
648 }
649 else
650 {
651 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_40_L, (bEnable ? BIT(3):0), BIT(3));
652 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_01_L, (bEnable ? BIT(2):0), BIT(2));
653 }
654 }
655
Hal_SC_get_ip2_csc(void * pInstance,SCALER_WIN eWindow)656 MS_BOOL Hal_SC_get_ip2_csc(void *pInstance, SCALER_WIN eWindow)
657 {
658 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
659 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
660 MS_BOOL bYUVInput;
661 if(eWindow == MAIN_WINDOW)
662 {
663 // If it has CSC, it shows it must be RGB input.
664 // Because in scaler, it must be YUV. So if input is RGB, then we need to do CSC
665 bYUVInput = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, BIT(3) ))? FALSE:TRUE;
666 }
667 else
668 {
669 bYUVInput = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, BIT(3) ))? FALSE:TRUE;
670 }
671 return bYUVInput;
672 }
673
Hal_SC_set_delayline(void * pInstance,MS_U8 u8DelayLines,SCALER_WIN eWindow)674 void Hal_SC_set_delayline(void *pInstance, MS_U8 u8DelayLines, SCALER_WIN eWindow )
675 {
676 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
677 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
678 //skip bit7, which is other usage
679 MS_U16 u16DelayLines = ((MS_U16)u8DelayLines) & 0xFF;
680 if( eWindow == MAIN_WINDOW )
681 {
682 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_1C_L, (u16DelayLines<<4), (BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)));
683 }
684 else
685 {
686 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_1C_L, (u16DelayLines<<4), (BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)));
687 }
688 }
689
Hal_SC_set_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)690 void Hal_SC_set_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
691 {
692 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
693 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
694 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
695 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
696
697 MS_PHY u32MinLimitAddress = 0;
698 MS_PHY u32MaxLimitAddress = 0;
699
700 #ifndef DONT_USE_CMA
701 #if (XC_SUPPORT_CMA ==TRUE)
702 #if ((HW_DESIGN_4K2K_VER == 4)||(HW_DESIGN_4K2K_VER == 6))
703 #if (defined (ANDROID))
704 UNUSED(u32WritelimitAddrBase);
705 UNUSED(eWindow);
706 return;
707 #endif
708 #endif
709 #endif
710 #endif
711
712 #if (HW_DESIGN_4K2K_VER == 4)
713 // in Monaco, the 4K data path need to setup the IPM write on the FRCM base, and the max/min limit region also need to change
714 if(gSrcInfo[eWindow].stCapWin.width > 3800)
715 {
716 u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
717 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
718 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
719 else
720 u32MaxLimitAddress = u32MinLimitAddress;
721 }
722 //monaco mm DS VB size always be 4k2k , mvop timing is 4k2k , 2p mode
723 else if ((pXCResourcePrivate->sthal_SC.bDynamicScalingEnable || pXCResourcePrivate->stdrvXC_Dynamicscaling._bDSForceIndexEnable[eWindow] ) &&
724 (gSrcInfo[eWindow].Status2.u16VirtualBox_Width >= 0xF00) && (gSrcInfo[eWindow].Status2.u16VirtualBox_Height>= 0x870))
725 {
726 u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
727 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
728 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
729 else
730 u32MaxLimitAddress = u32MinLimitAddress;
731 }
732 else
733 #endif
734 {
735 u32MinLimitAddress = MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
736 if((MHal_XC_GetDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDNRBufSize(pInstance, eWindow))!=0)
737 u32MaxLimitAddress = (MHal_XC_GetDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
738 else
739 u32MaxLimitAddress = u32MinLimitAddress;
740 }
741 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, MHal_XC_GetDNRBufAddress=%tx, MHal_XC_GetDNRBufSize=%tx\n", eWindow, (ptrdiff_t)(MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ),(ptrdiff_t) (MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD);
742 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, u32MinLimitAddress=%tx, u32MaxLimitAddress=%tx\n", eWindow, (ptrdiff_t)u32MinLimitAddress, (ptrdiff_t)u32MaxLimitAddress);
743
744 if(eWindow == MAIN_WINDOW)
745 {
746 /// need to disable the r/w request, when change the write limit base
747 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
748 if (IsHMirrorMode(eWindow) && IsEnableDualMode(eWindow))
749 {
750 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address
751 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, u32MinLimitAddress); //F2 memory min address
752 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, u32MaxLimitAddress); //F2 memory max address
753 }
754 else
755 {
756 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(0):0),BIT(0)); //F2 memory address
757 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_40_L, u32MinLimitAddress); //F2 memory min address
758 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_42_L, u32MaxLimitAddress); //F2 memory max address
759 }
760 /// need to enable the r/w request
761 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0x00, BIT(0)|BIT(1));
762 }
763 else
764 {
765 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
766 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(1):0),BIT(1)); //F1 memory address limit enable
767 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_44_L, u32MinLimitAddress); //F1 memory min address
768 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_46_L, u32MaxLimitAddress); //F1 memory max address
769 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0x00, BIT(0)|BIT(1));
770 }
771 }
772
Hal_SC_set_frcm_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)773 void Hal_SC_set_frcm_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
774 {
775 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
776 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
777 MS_PHY u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
778 MS_PHY u32MaxLimitAddress = 0;
779
780 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
781 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
782 else
783 u32MaxLimitAddress = u32MinLimitAddress;
784
785 if(eWindow == MAIN_WINDOW)
786 {
787 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_50_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address limit enable
788 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_64_L, u32MinLimitAddress); //F2 memory min address
789 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_66_L, u32MaxLimitAddress); //F2 memory max address
790 }
791 else
792 {
793 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_50_L, ((u32WritelimitAddrBase&BIT(31))?BIT(5):0),BIT(5)); //F1 memory address limit enable
794 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_68_L, u32MinLimitAddress); //F1 memory min address
795 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_6A_L, u32MaxLimitAddress); //F1 memory max address
796 }
797
798 }
799
Hal_SC_set_dual_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)800 void Hal_SC_set_dual_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
801 {
802 #ifdef UFO_XC_SUPPORT_DUAL_MIU
803 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
804 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
805 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
806 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
807
808 MS_PHY u32MinLimitAddress = 0;
809 MS_PHY u32MaxLimitAddress = 0;
810
811 u32MinLimitAddress = MHal_XC_GetDualDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD;
812 if((MHal_XC_GetDualDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDualDNRBufSize(pInstance, eWindow))!=0)
813 u32MaxLimitAddress = (MHal_XC_GetDualDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDualDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
814 else
815 u32MaxLimitAddress = u32MinLimitAddress;
816
817 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, MHal_XC_GetDNRBufAddress=%llx, MHal_XC_GetDNRBufSize=%llx\n", eWindow, (MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ), (MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD);
818 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, u32MinLimitAddress=%llx, u32MaxLimitAddress=%llx\n", eWindow, u32MinLimitAddress, u32MaxLimitAddress);
819
820 if(eWindow == MAIN_WINDOW)
821 {
822 /// need to disable the r/w request, when change the write limit base
823 /// For SCMI0/1 use the same IPM r/w request.
824 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
825 if (IsHMirrorMode(eWindow) && IsEnableDualMode(eWindow))
826 {
827 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(0):0),BIT(0)); //F2 memory address
828 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_40_L, u32MinLimitAddress); //F2 memory min address
829 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_42_L, u32MaxLimitAddress); //F2 memory max address
830
831 }
832 else
833 {
834 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address
835 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, u32MinLimitAddress); //F2 memory min address
836 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, u32MaxLimitAddress); //F2 memory max address
837 }
838 /// need to enable the r/w request
839 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0x00, BIT(0)|BIT(1));
840 }
841 #endif
842 }
843
Hal_SC_set_opm_write_limit(void * pInstance,MS_BOOL bEnable,MS_BOOL bFlag,MS_PHY u32OPWlimitAddr,SCALER_WIN eWindow)844 void Hal_SC_set_opm_write_limit(void *pInstance, MS_BOOL bEnable, MS_BOOL bFlag, MS_PHY u32OPWlimitAddr, SCALER_WIN eWindow)
845 {
846 #if 0
847
848 MS_U16 u16temp = 0x00;
849 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
850 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
851
852 // Only support address of Main_Window
853 if (eWindow != MAIN_WINDOW )
854 return;
855
856 // Bit 0 ~ 24
857 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5E_L, u32OPWlimitAddr & 0xFFFF);
858 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5F_L, (u32OPWlimitAddr >> 16) & 0x1FF);
859
860 // OPW limit enable
861 if (bEnable)
862 u16temp = BIT(9);
863
864 // OPW limit flag 0: maximum 1:minimum
865 if (bFlag)
866 u16temp |= BIT(10);
867
868 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_5F_L,u16temp ,BIT(9) | BIT(10) );
869 #endif
870 }
871
Hal_SC_is_extra_req_en(void * pInstance,MS_U16 * pu16MainHStart,MS_U16 * pu16MainHEnd,MS_U16 * pu16SubHStart,MS_U16 * pu16SubHEnd)872 MS_BOOL Hal_SC_is_extra_req_en(void *pInstance,
873 MS_U16 *pu16MainHStart, MS_U16 *pu16MainHEnd,
874 MS_U16 *pu16SubHStart, MS_U16 *pu16SubHEnd)
875 {
876 MS_BOOL bEn = FALSE;
877 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
878 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
879
880 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
881 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
882
883 MS_U16 u16MainHStart, u16SubHStart;
884 MS_U16 u16MainHEnd, u16SubHEnd;
885 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
886 u16MainHStart = pu16MainHStart == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L) : *pu16MainHStart;
887 u16MainHEnd = pu16MainHEnd == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L) : *pu16MainHEnd;
888 u16SubHStart = pu16SubHStart == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L) : *pu16SubHStart;
889 u16SubHEnd = pu16SubHEnd == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L) : *pu16SubHEnd;
890
891 if( SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(1))
892 &&(((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
893 ||(psXCInstPri->u32DeviceID == 1))
894 ) // Only Legacy mode use old rule for extra enable
895 {
896 if(u16MainHStart > u16SubHStart || u16MainHEnd < u16SubHEnd)
897 {
898 bEn = FALSE;
899 }
900 else
901 {
902 bEn = TRUE;
903 }
904 }
905 else
906 {
907 bEn = FALSE;
908 }
909 #if DBG_EN
910 SC_DBG(printf("Sub=%d, MainHs=%d, SubHs=%d, MainHe=%d, SubHe=%d :: Extra=%d\n",
911 SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(1)),
912 u16MainHStart, u16SubHStart, u16MainHEnd, u16SubHEnd, bEn));
913 #endif
914 return bEn;
915
916 }
917
918 #if 0 //Dual not support switch miu select dynamicly.
919 //#ifdef UFO_XC_SUPPORT_DUAL_MIU
920 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
921 // Miu opm1 opm2 need to be switched just under Dual Mirror case, so it should be Called in runtime.
922 // This API just for swap OPM when miu select control by miu arb.
923 static void _Hal_SC_adjust_dual_miu_setting(void *pInstance, MS_PHY u32FBAddress, MS_PHY u32DualFBAddress, MS_BOOL bMirrorWithDual, MS_U16 *pu16OPMLeftMiuSel, MS_U16 *pu16OPMRightMiuSel)
924 {
925 MS_U8 u8MIUSel = 0;
926 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
927 if (u8MIUSel == 0)
928 {
929 //IPM0 OPM0 access miu0
930 *pu16OPMLeftMiuSel = 0x0;
931 }
932 else if(u8MIUSel == 1)
933 {
934 // OPM0 access miu 1
935 *pu16OPMLeftMiuSel = 0x1;
936 }
937 else if(u8MIUSel == 2)
938 {
939 // OPM0 access miu 1
940 *pu16OPMLeftMiuSel = 0x2;
941 }
942
943 _phy_to_miu_offset(u8MIUSel, u32DualFBAddress, u32DualFBAddress);
944 if (u8MIUSel == 0)
945 {
946 //IPM0 OPM0 access miu0
947 *pu16OPMRightMiuSel = 0x0;
948 }
949 else if(u8MIUSel == 1)
950 {
951 // OPM0 access miu 1
952 *pu16OPMRightMiuSel = 0x1;
953 }
954 else if(u8MIUSel == 2)
955 {
956 // OPM0 access miu 1
957 *pu16OPMRightMiuSel = 0x2;
958 }
959
960 if (bMirrorWithDual)
961 {
962 MS_U16 u16Tmp = *pu16OPMLeftMiuSel;
963 *pu16OPMLeftMiuSel = *pu16OPMRightMiuSel;
964 *pu16OPMRightMiuSel = u16Tmp;
965 }
966
967 }
968
969 #else
970 //the patch to reset the miu selection ,becuase HW always swaps the miu selection on dual or without dual.
971 static void _Hal_SC_adjust_swap_miu_setting(void *pInstance,MS_PHY u32FBAddress)
972 {
973 MS_U8 u8MIUSel = 0;
974 MS_U8 u8MIUSel_temp= 0;
975 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
976 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
977 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
978 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
979 u8MIUSel_temp = SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, BIT(4)) >> 3;
980 u8MIUSel_temp = u8MIUSel_temp | (SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, BIT(4)) >> 4);
981 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
982 if(u8MIUSel_temp != u8MIUSel)
983 {
984 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, (u8MIUSel & BIT(0)) << 4 , 0x0010);
985 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, ((u8MIUSel & BIT(1)) >> 1) << 4 , 0x0010);
986 }
987 else
988 {
989 printf("The miu has been set correctly function %s line %d parars \n",__FUNCTION__,__LINE__);
990 }
991 }
992 static void _Hal_SC_adjust_swap_miu_setting_burst(void *pInstance,MS_PHY u32FBAddress)
993 {
994 MS_U8 u8MIUSel = 0;
995 MS_U8 u8MIUSel_temp= 0;
996 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
997 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
998 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
999 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1000 u8MIUSel_temp = SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, BIT(4)) >> 3;
1001 u8MIUSel_temp = u8MIUSel_temp | (SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, BIT(4)) >> 4);
1002 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
1003 if(u8MIUSel_temp != u8MIUSel)
1004 {
1005 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_05_L, (u8MIUSel & BIT(0)) << 4 ,BIT(4));
1006 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK51_05_L, ((u8MIUSel & BIT(1)) >> 1) << 4 ,BIT(4));
1007 }
1008 else
1009 {
1010 printf("The miu has been set correctly function %s line %d parars \n",__FUNCTION__,__LINE__);
1011 }
1012 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1013 }
1014 #endif
1015 #endif
1016
Hal_SC_3D_CopyDispWinToSTGEN(void * pInstance,SCALER_WIN eWindow)1017 void Hal_SC_3D_CopyDispWinToSTGEN(void *pInstance, SCALER_WIN eWindow)
1018 {
1019 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1020 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1021 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1022 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1023
1024 MS_U16 u16Start = 0, u16End = 0;
1025 // 3D case, copy bk10 disp to bk68
1026 // copy main disp Y
1027 if(eWindow == MAIN_WINDOW)
1028 {
1029 u16Start = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L);
1030 u16End = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L);
1031 // FRC 3D,SC transfer to TB,FRC transfer to LA ,tb out 3D main display window height is 1/2 of LA
1032 if(MHal_FRC_IsEnableFRC3D(pInstance, MAIN_WINDOW) && (pXCResourcePrivate->stdrvXC_3D._bLAToTB) && IS_OUTPUT_4K2K_60HZ_PANEL())
1033 {
1034 if(!IsVMirrorMode(eWindow))
1035 {
1036 u16End = (u16Start -pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart)/2 + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + (u16End-u16Start +1)/2 -1;
1037 u16Start = (u16Start -pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart)/2 + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart;
1038 }
1039 else
1040 {
1041 u16Start = (u16Start -pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart)/2 + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + (u16End-u16Start +1)/2 -1;
1042 u16End = u16Start + (u16End-u16Start +1)/2 -1;
1043 }
1044 }
1045 u16Start = u16Start + VSTART_OFFSET;
1046 u16End = u16End + VSTART_OFFSET;
1047
1048 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0D_L, u16Start, 0x1FFF);
1049 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, u16End, 0x1FFF);
1050
1051 // copy main disp X
1052 u16Start = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L);
1053 u16End = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L);
1054
1055 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_05_L, u16Start, 0x3FFF);
1056 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_06_L, u16End, 0x3FFF);
1057 }
1058 else
1059 {
1060 // copy sub disp Y
1061 u16Start = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L);
1062 u16End = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L);
1063
1064 u16Start = u16Start + VSTART_OFFSET;
1065 u16End = u16End + VSTART_OFFSET;
1066
1067 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_12_L, u16Start, 0x1FFF);
1068 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_13_L, u16End, 0x1FFF);
1069
1070 // copy sub disp X
1071 u16Start = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L);
1072 u16End = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L);
1073
1074 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_10_L, u16Start, 0x3FFF);
1075 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_11_L, u16End, 0x3FFF);
1076 }
1077 }
1078
_Hal_SC_fill_main_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg)1079 static void _Hal_SC_fill_main_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg)
1080 {
1081 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1082 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1083 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1084 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1085
1086 if(Hal_SC_is_extra_req_en(pInstance, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd, NULL, NULL))
1087 {
1088 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
1089 }
1090 else
1091 {
1092 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(15));
1093 }
1094
1095 //H pre-scaling
1096 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_04_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>00), 0xFFFF);
1097 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_05_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>16), 0xFFFF);
1098 //V pre-scaling
1099 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_08_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>00), 0xFFFF);
1100 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_09_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>16), 0xFFFF);
1101 //H post-scaling
1102 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>00), 0xFFFF);
1103 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>16), 0xFFFF);
1104 //V post-scaling
1105 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>00), 0xFFFF);
1106 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>16), 0xFFFF);
1107
1108 //SCMI: vertical limitation
1109 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_18_L, (MS_U16)(pDBreg->u16VWritelimit), 0xFFFF);
1110 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1111 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1112
1113 //SCMI: IPM address 0
1114 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_08_L, (MS_U16)(pDBreg->u32DNRBase0>>00), 0xFFFF);
1115 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_09_L, (MS_U16)(pDBreg->u32DNRBase0>>16), 0xFFFF);
1116 //SCMI: DNR address 1
1117 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1118 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1119 //SCMI: DNR address 2
1120 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0C_L, (MS_U16)(pDBreg->u32DNRBase2>>00), 0xFFFF);
1121 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0D_L, (MS_U16)(pDBreg->u32DNRBase2>>16), 0xFFFF);
1122
1123 //SCMI: DNR offset
1124 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0E_L, (MS_U16)(pDBreg->u16DNROffset>>00), 0xFFFF);
1125 //SCMI: DNR fetch
1126 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0F_L, (MS_U16)(pDBreg->u16DNRFetch>>00), 0xFFFF);
1127
1128 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1129
1130 //SCMI: OPM address 0
1131 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00), 0xFFFF);
1132 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_11_L, (MS_U16)(pDBreg->u32OPMBase0>>16), 0xFFFF);
1133 //SCMI: OPM address 1
1134 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_12_L, (MS_U16)(pDBreg->u32OPMBase1>>00), 0xFFFF);
1135 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_13_L, (MS_U16)(pDBreg->u32OPMBase1>>16), 0xFFFF);
1136 //SCMI: OPM address 2
1137 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_14_L, (MS_U16)(pDBreg->u32OPMBase2>>00), 0xFFFF);
1138 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_15_L, (MS_U16)(pDBreg->u32OPMBase2>>16), 0xFFFF);
1139 //SCMI: OPM offset
1140 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_16_L, (MS_U16)(pDBreg->u16OPMOffset>>00), 0xFFFF);
1141 //SCMI: OPM fetch
1142 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_17_L, (MS_U16)(pDBreg->u16OPMFetch>>00), 0xFFFF);
1143
1144 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1145 if (psXCInstPri->u32DeviceID == 0) // Dual miu just support sc0 main window for main window.
1146 {
1147 if (IsEnableDualMode(MAIN_WINDOW))
1148 {
1149 #if 0 // Dual do not support switch MIU setting Dynamic.
1150 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1151 MS_U16 u16OPMLeftMiuSel = 0;
1152 MS_U16 u16OPMRightMiuSel = 0;
1153 if(IsHMirrorMode(MAIN_WINDOW))
1154 {
1155 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1156 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], TRUE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1157 }
1158 else
1159 {
1160 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1161 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1162 }
1163
1164 // miu request0 IPM/OPM LSB
1165 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1166 // miu request0 IPM/OPM MSB
1167 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1168 // miu request1 IPM/OPM
1169 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1170 #else
1171 _Hal_SC_adjust_swap_miu_setting_burst(pInstance,pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW]);
1172 #endif
1173 #endif
1174 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_08_L, (MS_U16)(pDBreg->u32DualDNRBase0 >> 0), 0xFFFF); //F2_1 IPM base addr
1175 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_09_L, (MS_U16)(pDBreg->u32DualDNRBase0 >> 16), 0xFFFF);
1176 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_0E_L, (MS_U16)(pDBreg->u16DualDNROffset), 0x1FFF); //F2_1 IPM offset
1177 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_0F_L, (MS_U16)(pDBreg->u16DualDNRFetch), 0x1FFF); //F2_1 IPM fetch number
1178 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_10_L, (MS_U16)(pDBreg->u32DualOPMBase0 >> 0), 0xFFFF); //F2_1 OPM base addr
1179 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_11_L, (MS_U16)(pDBreg->u32DualOPMBase0 >> 16), 0xFFFF);
1180 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_16_L, (MS_U16)(pDBreg->u16DualOPMOffset), 0x1FFF); //F2_1 OPM offset
1181 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_17_L, (MS_U16)(pDBreg->u16DualOPMFetch), 0x1FFF); //F2_1 OPM fetch number
1182 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_28_L, (MS_U16)(pDBreg->u16DualDNRFetch + pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16DNRFetch), 0x1FFF); //F2 IPM total fetch
1183 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_29_L, (MS_U16)(BIT(15)|(pDBreg->u16DualOPMFetch + pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16OPMFetch)), 0x1FFF | BIT(15)); //F2 OPM total fetch
1184
1185 }
1186 else
1187 {
1188 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_29_L, 0, BIT(15));
1189 #if 0 // Dual do not support switch MIU setting Dynamic.
1190 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1191 MS_U16 u16OPMLeftMiuSel = 0;
1192 MS_U16 u16OPMRightMiuSel = 0;
1193 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1194 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1195 // miu request0 IPM/OPM LSB
1196 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1197 // miu request0 IPM/OPM MSB
1198 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1199 // miu request1 IPM/OPM
1200 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1201 #endif
1202 #endif
1203 }
1204 }
1205 #endif
1206
1207 //PIP
1208 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00), 0xFFFF); // Write V length
1209 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1D_L, (MS_U16)(pDBreg->u16LBOffset&0xFF), 0x00FF);
1210 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1C_L, (MS_U16)(pDBreg->u16DispOffset&0xFF), 0x00FF);
1211 // if LB Offset > externded pixels of bottom A session,
1212 // there would be garbage on the left side of sub video
1213 if (pDBreg->u16LBOffset > SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, 0x00FF))
1214 {
1215 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_14_L, (pDBreg->u16LBOffset&0xFF), 0x00FF);
1216 }
1217
1218 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1219 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1220 pDBreg->u16H_CapSize |= 0x8000;
1221 else
1222 pDBreg->u16H_CapSize |= 0x0000;
1223
1224 //capture window
1225 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_04_L, (MS_U16)(pDBreg->u16V_CapStart>>00), 0xFFFF);
1226 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_05_L, (MS_U16)(pDBreg->u16H_CapStart>>00), 0xFFFF);
1227 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_06_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0xFFFF);
1228 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_07_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0xFFFF);
1229 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1230 if (psXCInstPri->u32DeviceID == 1)
1231 {
1232 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
1233 //Display window
1234 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, u16HDEStart/2, VOP_DISPLAY_HSTART_MASK);//temp solution(+90)
1235 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart), VOP_DISPLAY_HEND_MASK);
1236 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_04_L, u16HDEStart/2, VOP_DISPLAY_HSTART_MASK);//temp solution(+90)
1237 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart), VOP_DISPLAY_HEND_MASK);
1238
1239 // E_FRC_PIPE_DELAY_MODE ePipeDlyMode = E_FRC_PIPE_DELAY_MODE_AUTO;
1240 MS_U32 u32Sc1OneLineDly = (SC_R2BYTE(0, REG_SC_BK10_0C_L) + 1)/2;
1241 MS_U32 u32Sc1TGEN_Dly = 0;
1242 if (SC_R2BYTEMSK(0, REG_SC_BK68_50_L, BIT(3)) == 0)
1243 {
1244 MS_U32 u32STGEN_Dly = VIP_SC0_V_DLY*u32Sc1OneLineDly+VIP_SC0_H_DLY;
1245 MS_U32 u32Sc0TGEN_Dly = u32STGEN_Dly + TGEN_SC0_DLY;
1246 MS_U32 u32Sc1VIP_Dly = VIP_SC1_V_DLY*u32Sc1OneLineDly + VIP_SC1_H_DLY;
1247 if (u32Sc0TGEN_Dly > u32Sc1VIP_Dly + SC1_PRE_RUN_DLY)
1248 {
1249 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY;
1250 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1251 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1252 }
1253 else
1254 {
1255 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly + u32Sc1OneLineDly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY;
1256 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart-1), VOP_DISPLAY_VSTART_MASK);
1257 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd-1), VOP_DISPLAY_VEND_MASK);
1258 }
1259 }
1260 else
1261 {
1262 MS_U32 u32STGEN_Dly = VIP_SC0_USER_MODE_V_DLY*u32Sc1OneLineDly+VIP_SC0_USER_MODE_H_DLY;
1263 MS_U32 u32Sc0TGEN_Dly = u32STGEN_Dly + TGEN_SC0_USER_MODE_DLY;
1264 MS_U32 u32HComp = (pDBreg->u16H_DisStart - u16HDEStart)/2;
1265 MS_U32 u32Sc1VIP_Dly = VIP_SC1_V_DLY*u32Sc1OneLineDly + VIP_SC1_H_DLY;
1266 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY + u32HComp;
1267 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1268 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1269 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_06_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart, 0x1FFF); // DE V start
1270 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_07_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1, 0x1FFF); // DE V end
1271 }
1272 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK68_61_L, (MS_U16)(u32Sc1TGEN_Dly%u32Sc1OneLineDly)*2, 0xFFFF);
1273 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK68_62_L, (MS_U16)(u32Sc1TGEN_Dly/u32Sc1OneLineDly), 0xFFFF);
1274
1275 if(!Hal_SC_3D_IsDualViewMode(pInstance,MAIN_WINDOW))
1276 {
1277 //Display window
1278 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_07_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1279 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_08_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1280 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_09_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1281 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_0A_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1282 }
1283
1284 }
1285 else
1286 {
1287 MS_U16 u16Start = 0, u16End = 0;
1288 MS_U16 u16DispX = (pDBreg->u16H_DisStart +1) &~1; // Hstart need to be even
1289 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled) &&
1290 MHal_FRC_IsFHDToFSC(pInstance,MAIN_WINDOW))
1291 {
1292 u16DispX = (pDBreg->u16H_DisStart/2 +1) &~1; // Hstart need to be even
1293
1294 u16Start = pDBreg->u16V_DisStart/2;
1295 u16End = (pDBreg->u16V_DisStart/2 + (pDBreg->u16V_DisEnd - pDBreg->u16V_DisStart + 1)/2 - 1);
1296
1297 u16Start += VSTART_OFFSET;
1298 u16End += VSTART_OFFSET;
1299
1300 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0D_L, u16Start, 0x1FFF);
1301 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0E_L, u16End, 0x1FFF);
1302
1303 u16Start = u16DispX;
1304 u16End = (u16DispX + (pDBreg->u16H_DisEnd - pDBreg->u16H_DisStart + 1)/2 - 1);
1305
1306 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_05_L, u16Start, 0x3FFF);
1307 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_06_L, u16End, 0x3FFF);
1308 }
1309 else
1310 {
1311 u16Start = pDBreg->u16V_DisStart;
1312 u16End = (pDBreg->u16V_DisStart + (pDBreg->u16V_DisEnd - pDBreg->u16V_DisStart + 1) - 1);
1313
1314 u16Start += VSTART_OFFSET;
1315 u16End += VSTART_OFFSET;
1316
1317 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0D_L, u16Start, 0x1FFF);
1318 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0E_L, u16End, 0x1FFF);
1319
1320 u16Start = u16DispX;
1321 u16End = u16DispX + ((pDBreg->u16H_DisEnd - pDBreg->u16H_DisStart + 1) - 1);
1322
1323 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_05_L, u16Start, 0x3FFF);
1324 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_06_L, u16End, 0x3FFF);
1325 }
1326
1327 //Display window
1328 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1329 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1330 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart), VOP_DISPLAY_VSTART_MASK);
1331 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd), VOP_DISPLAY_VEND_MASK);
1332 }
1333 #else
1334 //Display window
1335 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)&&(psXCInstPri->u32DeviceID != 1))
1336 {
1337 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart), VOP_DISPLAY_HSTART_MASK);
1338 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart +pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width-1), VOP_DISPLAY_HEND_MASK);
1339 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart), VOP_DISPLAY_VSTART_MASK);
1340 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1), VOP_DISPLAY_VEND_MASK);
1341 }
1342 else
1343 {
1344 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1345 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1346 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart>>00), VOP_DISPLAY_VSTART_MASK);
1347 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd>>00), VOP_DISPLAY_VEND_MASK);
1348 }
1349 #endif
1350 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1351
1352 #if SUPPORT_2_FRAME_MIRROR
1353
1354 if( (gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber == IMAGE_STORE_2_FRAMES) && (!gSrcInfo[MAIN_WINDOW].bInterlace) && (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == 0))
1355 {
1356 // 2_frmae_mirror cannot work when UC on
1357
1358 //SCMI: DNR address 1
1359 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1360 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1361
1362 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_30_L, 0x4000,0xFFFF);// enable two frame mirror
1363
1364 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, 0x0001) == 0 )//compress mode
1365 {
1366 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, 0x20,0x00F0); // opm_ce_lcnt_inv
1367 }
1368 }
1369 else
1370 {
1371 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == BIT(15))
1372 {
1373 printf("@@ [%s,%5d] 2_frmae_mirror cannot work when UC on \n",__func__,__LINE__);
1374 }
1375
1376 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_30_L, 0x0000,0xFFFF);// disable two frame mirror
1377 }
1378 #endif
1379
1380 MS_U16 u16reg = 0;
1381 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1382 ||(psXCInstPri->u32DeviceID == 1))
1383 {
1384 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L);
1385 }
1386 else
1387 {
1388 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK33_32_L);
1389 }
1390
1391
1392 if(pDBreg->bOpmLcntInv_En)
1393 {
1394 u16reg |= BIT(5);
1395 }
1396 else
1397 {
1398 u16reg &= ~ BIT(5);
1399 }
1400
1401
1402 //monaco/muji 3D mode need control sub for some output format, or else the edge of object in the image may shake
1403 #if (HW_DESIGN_4K2K_VER == 4)
1404 E_XC_3D_OUTPUT_MODE e3DOutputFormat = MDrv_XC_Get_3D_Output_Mode(pInstance);
1405 if((e3DOutputFormat == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
1406 || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM) || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
1407 || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
1408 || (e3DOutputFormat == E_XC_3D_OUTPUT_FRAME_PACKING))
1409 {
1410 //Hal_SC_set_opm_lcnt_inv(pInstance, bopm_lcnt_inv, SUB_WINDOW);
1411 if(pDBreg->bOpmLcntInv_En)
1412 {
1413 u16reg |= BIT(4);
1414 }
1415 else
1416 {
1417 u16reg &= ~ BIT(4);
1418 }
1419 }
1420 #endif
1421
1422 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1423 ||(psXCInstPri->u32DeviceID == 1))
1424 {
1425 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, u16reg, 0xFFFF);
1426 }
1427 else
1428 {
1429 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK33_32_L, u16reg, 0xFFFF);
1430 }
1431 }
1432
_Hal_SC_fill_sub_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg)1433 static void _Hal_SC_fill_sub_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg)
1434 {
1435 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1436 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1437 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1438 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1439
1440 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd))
1441 {
1442 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
1443 }
1444 else
1445 {
1446 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(15));
1447 }
1448
1449 //H pre-scaling
1450 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_04_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>00), 0xFFFF);
1451 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_05_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>16), 0xFFFF);
1452 //V pre-scaling
1453 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_08_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>00), 0xFFFF);
1454 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_09_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>16), 0xFFFF);
1455
1456 //H post-scaling
1457 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_27_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>00), 0xFFFF);
1458 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_28_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>16), 0xFFFF);
1459 //V post-scaling
1460 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_29_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>00), 0xFFFF);
1461 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_2A_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>16), 0xFFFF);
1462
1463 //SCMI: vertical limitation
1464 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_58_L, (MS_U16)(pDBreg->u16VWritelimit), 0xFFFF);
1465 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5A_L, (MS_U16)(pDBreg->u32WritelimitBase>>00), 0xFFFF);
1466 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5B_L, (MS_U16)(pDBreg->u32WritelimitBase>>16), 0xFFFF);
1467 //SCMI: IPM address 0
1468 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_48_L, (MS_U16)(pDBreg->u32DNRBase0>>00), 0xFFFF);
1469 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_49_L, (MS_U16)(pDBreg->u32DNRBase0>>16), 0xFFFF);
1470 //SCMI: DNR address 1
1471 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1472 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1473 //SCMI: DNR address 2
1474 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4C_L, (MS_U16)(pDBreg->u32DNRBase2>>00), 0xFFFF);
1475 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4D_L, (MS_U16)(pDBreg->u32DNRBase2>>16), 0xFFFF);
1476 //SCMI: DNR offset
1477 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4E_L, (MS_U16)(pDBreg->u16DNROffset>>00), 0xFFFF);
1478 //SCMI: DNR fetch
1479 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4F_L, (MS_U16)(pDBreg->u16DNRFetch>>00), 0xFFFF);
1480 //SCMI: OPM address 0
1481 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_50_L, (MS_U16)(pDBreg->u32OPMBase0>>00), 0xFFFF);
1482 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_51_L, (MS_U16)(pDBreg->u32OPMBase0>>16), 0xFFFF);
1483 //SCMI: OPM address 1
1484 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_52_L, (MS_U16)(pDBreg->u32OPMBase1>>00), 0xFFFF);
1485 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_53_L, (MS_U16)(pDBreg->u32OPMBase1>>16), 0xFFFF);
1486 //SCMI: OPM address 2
1487 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_54_L, (MS_U16)(pDBreg->u32OPMBase2>>00), 0xFFFF);
1488 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_55_L, (MS_U16)(pDBreg->u32OPMBase2>>16), 0xFFFF);
1489 //SCMI: OPM offset
1490 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_56_L, (MS_U16)(pDBreg->u16OPMOffset>>00), 0xFFFF);
1491 //SCMI: OPM fetch
1492 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_57_L, (MS_U16)(pDBreg->u16OPMFetch>>00), 0xFFFF);
1493 //PIP
1494 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_16_L, (MS_U16)(pDBreg->u16VLen>>00), 0xFFFF); // Write V length
1495 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1D_L, (MS_U16)((pDBreg->u16LBOffset&0xFF)<<8), 0xFF00);
1496 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1C_L, (MS_U16)((pDBreg->u16DispOffset&0xFF)<<8), 0xFF00);
1497
1498 /// before enable ML bit mask feature, the capture size for 2P setting BK03_07[15] need to be considered
1499 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, BIT(15)))
1500 pDBreg->u16H_CapSize |= 0x8000;
1501 else
1502 pDBreg->u16H_CapSize |= 0x0000;
1503
1504 // capture window
1505 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_04_L, (MS_U16)(pDBreg->u16V_CapStart>>00), 0xFFFF);
1506 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_05_L, (MS_U16)(pDBreg->u16H_CapStart>>00), 0xFFFF);
1507 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_06_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0xFFFF);
1508 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_07_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0xFFFF);
1509
1510 //Display window
1511 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, (MS_U16)(pDBreg->u16H_DisStart>>00), 0xFFFF);
1512 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), 0xFFFF);
1513 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, (MS_U16)(pDBreg->u16V_DisStart>>00), 0xFFFF);
1514 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, (MS_U16)(pDBreg->u16V_DisEnd>>00), 0xFFFF);
1515
1516 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5C_L, 0x0, 0x1FFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1517
1518 MS_U16 u16reg = 0;
1519 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1520 ||(psXCInstPri->u32DeviceID == 1))
1521 {
1522 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L);
1523 }
1524 else
1525 {
1526 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK33_32_L);
1527 }
1528
1529 if(pDBreg->bOpmLcntInv_En)
1530 {
1531 u16reg |= BIT(4);
1532 }
1533 else
1534 {
1535 u16reg &= ~ BIT(4);
1536 }
1537
1538 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1539 ||(psXCInstPri->u32DeviceID == 1))
1540 {
1541 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, u16reg, 0xFFFF);
1542 }
1543 else
1544 {
1545 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK33_32_L, u16reg, 0xFFFF);
1546 }
1547 }
1548
Hal_SC_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1549 void Hal_SC_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow )
1550 {
1551 _MLOAD_ENTRY(pInstance);
1552
1553 if( eWindow == MAIN_WINDOW )
1554 {
1555 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
1556 E_FRC_MLOAD_TRIG_MODE eTrigMode = E_FRC_MLOAD_TRIG_MODE_FROM_OP1;
1557 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1558 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1559 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1560 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1561
1562 // if no mute
1563 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled == FALSE)
1564 {
1565 if(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_5F_L) & BIT(15))
1566 {
1567 eTrigMode = E_FRC_MLOAD_TRIG_MODE_FROM_OP2;
1568 }
1569 else
1570 {
1571 eTrigMode = E_FRC_MLOAD_TRIG_MODE_FROM_OP1;
1572 }
1573
1574 MHal_FRC_Set_Mload_Trig_Mode(pInstance, E_FRC_MLOAD_TRIG_MODE_FROM_OP1);
1575
1576 _Hal_SC_fill_main_sw_db_burst(pInstance, pDBreg);
1577 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1578
1579 //--> restore
1580 MHal_FRC_Set_Mload_Trig_Mode(pInstance, eTrigMode);
1581 }
1582 else
1583 {
1584 _Hal_SC_fill_main_sw_db_burst(pInstance, pDBreg);
1585 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1586 }
1587 #else
1588 _Hal_SC_fill_main_sw_db_burst(pInstance, pDBreg);
1589 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1590 #endif
1591 }
1592 else
1593 {
1594 _Hal_SC_fill_sub_sw_db_burst(pInstance, pDBreg);
1595 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1596 }
1597
1598 _MLOAD_RETURN(pInstance);
1599 }
1600
Hal_SC_dual_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pMainDBreg,P_SC_SWDB_INFO pSubDBreg)1601 void Hal_SC_dual_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pMainDBreg, P_SC_SWDB_INFO pSubDBreg)
1602 {
1603 _MLOAD_ENTRY(pInstance);
1604
1605 _Hal_SC_fill_main_sw_db_burst(pInstance, pMainDBreg);
1606 _Hal_SC_fill_sub_sw_db_burst(pInstance, pSubDBreg);
1607 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1608
1609 _MLOAD_RETURN(pInstance);
1610 }
1611
Hal_SC_sw_db(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1612 void Hal_SC_sw_db(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow )
1613 {
1614 MS_U32 u32LcentInvReg = 0;
1615 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1616 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1617 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1618 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1619
1620 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] bDynamicScalingEnable%d \n",__func__,__LINE__,pXCResourcePrivate->sthal_SC.bDynamicScalingEnable);
1621
1622 if( eWindow == MAIN_WINDOW )
1623 {
1624 if(Hal_SC_is_extra_req_en(pInstance, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd, NULL, NULL))
1625 {
1626 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, BIT(15), BIT(15));
1627 }
1628 else
1629 {
1630 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, 0, BIT(15));
1631 }
1632
1633 // H pre-scaling
1634 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_04_L, pDBreg->u32H_PreScalingRatio);
1635 // V pre-scaling
1636 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_08_L, pDBreg->u32V_PreScalingRatio);
1637 // H post-scaling
1638 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L, pDBreg->u32H_PostScalingRatio);
1639 // V post-scaling
1640 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L, pDBreg->u32V_PostScalingRatio);
1641
1642 //SCMI
1643 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, pDBreg->u16VWritelimit); // Set vertical limitation
1644 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pDBreg->u32DNRBase1);
1645
1646 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, pDBreg->u32DNRBase0); // input address0
1647 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L, pDBreg->u32DNRBase1); // input address1
1648 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0C_L, pDBreg->u32DNRBase2); // input address2
1649
1650 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, pDBreg->u16DNROffset);// input Offset
1651 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, pDBreg->u16DNRFetch); // input fetch
1652 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1653
1654
1655 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L, pDBreg->u32OPMBase0); // output address0
1656 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L, pDBreg->u32OPMBase1); // output address1
1657 // SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_14_L, pDBreg->u32OPMBase2); // output address2
1658 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, pDBreg->u16OPMOffset); // output offset
1659 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, pDBreg->u16OPMFetch); // output fetch
1660
1661 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1662 if (psXCInstPri->u32DeviceID == 0) // Dual miu just support sc0 main window for main window.
1663 {
1664 if(IsEnableDualMode(eWindow))
1665 {
1666 #if 0 // Dual miu do not support switch miu select dynamicly.
1667 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1668 MS_U16 u16OPMLeftMiuSel = 0;
1669 MS_U16 u16OPMRightMiuSel = 0;
1670 if(IsHMirrorMode(eWindow))
1671 {
1672 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1673 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], TRUE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1674 }
1675 else
1676 {
1677 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1678 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1679 }
1680 // miu request0 IPM/OPM LSB
1681 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1682 // miu request0 IPM/OPM MSB
1683 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1684 // miu request1 IPM/OPM
1685 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1686 #else
1687 _Hal_SC_adjust_swap_miu_setting(pInstance,pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW]);
1688 #endif
1689 #endif
1690 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_08_L, pDBreg->u32DualDNRBase0 >> 0, 0xFFFF); //F2_1 IPM base addr
1691 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_09_L, pDBreg->u32DualDNRBase0 >> 16, 0x03FF);
1692 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_0E_L, pDBreg->u16DualDNROffset, 0x1FFF); //F2_1 IPM offset
1693 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_0F_L, pDBreg->u16DualDNRFetch, 0x1FFF); //F2_1 IPM fetch number
1694 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_10_L, pDBreg->u32DualOPMBase0 >> 0, 0xFFFF); //F2_1 OPM base addr
1695 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_11_L, pDBreg->u32DualOPMBase0 >> 16, 0x03FF);
1696 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_16_L, pDBreg->u16DualOPMOffset, 0x1FFF); //F2_1 OPM offset
1697 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_17_L, pDBreg->u16DualOPMFetch, 0x1FFF); //F2_1 OPM fetch number
1698 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_28_L, pDBreg->u16DualDNRFetch + pDBreg->u16DNRFetch, 0x1FFF); //F2 IPM total fetch
1699 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, pDBreg->u16DualOPMFetch + pDBreg->u16OPMFetch, 0x1FFF); //F2 OPM total fetch
1700 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, BIT(15), BIT(15)); //Enable SCMI MIU Dual mode
1701 }
1702 else
1703 {
1704 SC_W2BYTEMSK(0, REG_SC_BK11_29_L, 0, BIT(15));
1705 #if 0 // Dual miu do not support switch miu dynamicly.
1706 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1707 MS_U16 u16OPMLeftMiuSel = 0;
1708 MS_U16 u16OPMRightMiuSel = 0;
1709 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1710 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1711 // miu request0 IPM/OPM LSB
1712 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1713 // miu request0 IPM/OPM MSB
1714 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1715 // miu request1 IPM/OPM
1716 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1717 #else
1718 _Hal_SC_adjust_swap_miu_setting(pInstance,pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW]);
1719 #endif
1720 #endif
1721 }
1722 }
1723 #endif
1724
1725 //PIP
1726 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_15_L, pDBreg->u16VLen); // Write V length
1727 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1D_L, (pDBreg->u16LBOffset&0xFF), 0xFF);
1728 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1C_L, (pDBreg->u16DispOffset&0xFF), 0xFF);
1729 // if LB Offset > externded pixels of bottom A session,
1730 // there would be garbage on the left side of sub video
1731 if (pDBreg->u16LBOffset > SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, 0xFF))
1732 {
1733 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, (pDBreg->u16LBOffset&0xFF), 0xFF);
1734 }
1735
1736 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1737 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1738 pDBreg->u16H_CapSize |= 0x8000;
1739 else
1740 pDBreg->u16H_CapSize |= 0x0000;
1741
1742 // capture window
1743 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_04_L, pDBreg->u16V_CapStart); // Capture V start
1744 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_05_L, pDBreg->u16H_CapStart); // Capture H start
1745 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, pDBreg->u16V_CapSize); // Capture V size
1746 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, pDBreg->u16H_CapSize); // Capture H size
1747
1748 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1749 //Display window
1750 if (psXCInstPri->u32DeviceID == 1)
1751 {
1752 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
1753 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, u16HDEStart/2);//temp solution(+90)
1754 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart));
1755 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, u16HDEStart/2);//temp solution(+90)
1756 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (u16HDEStart/2+ pDBreg->u16H_DisEnd -pDBreg->u16H_DisStart));
1757
1758 // E_FRC_PIPE_DELAY_MODE ePipeDlyMode = E_FRC_PIPE_DELAY_MODE_AUTO;
1759 MS_U32 u32Sc1OneLineDly = (SC_R2BYTE(0, REG_SC_BK10_0C_L) + 1)/2;
1760 MS_U32 u32Sc1TGEN_Dly = 0;
1761 if ((SC_R2BYTEMSK(0, REG_SC_BK68_50_L, BIT(3)) == 0)
1762 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1763 && (!Hal_SC_3D_IsDualViewMode(pInstance, MAIN_WINDOW))
1764 #endif
1765 )
1766 {
1767 MS_U32 u32STGEN_Dly = VIP_SC0_V_DLY*u32Sc1OneLineDly+VIP_SC0_H_DLY;
1768 MS_U32 u32Sc0TGEN_Dly = u32STGEN_Dly + TGEN_SC0_DLY;
1769 MS_U32 u32Sc1VIP_Dly = VIP_SC1_V_DLY*u32Sc1OneLineDly + VIP_SC1_H_DLY;
1770 if (u32Sc0TGEN_Dly > u32Sc1VIP_Dly + SC1_PRE_RUN_DLY)
1771 {
1772 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY;
1773 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart);
1774 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd);
1775 }
1776 else
1777 {
1778 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly + u32Sc1OneLineDly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY;
1779 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart - 1);
1780 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd - 1);
1781 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart-1, 0x1FFF); // DE V start
1782 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-2, 0x1FFF); // DE V end
1783 }
1784 SC_W2BYTEMSK(0, REG_SC_BK68_61_L, (u32Sc1TGEN_Dly%u32Sc1OneLineDly)*2, 0xFFFF);// 2p mode
1785 SC_W2BYTEMSK(0, REG_SC_BK68_62_L, u32Sc1TGEN_Dly/u32Sc1OneLineDly, 0xFFFF);
1786 }
1787 else
1788 {
1789 MS_U32 u32STGEN_Dly = VIP_SC0_USER_MODE_V_DLY*u32Sc1OneLineDly+VIP_SC0_USER_MODE_H_DLY;
1790 MS_U32 u32Sc0TGEN_Dly = u32STGEN_Dly + TGEN_SC0_USER_MODE_DLY;
1791 MS_U32 u32Sc1VIP_Dly = VIP_SC1_V_DLY*u32Sc1OneLineDly + VIP_SC1_H_DLY;
1792 MS_U32 u32HComp = (pDBreg->u16H_DisStart - u16HDEStart)/2;
1793 u32Sc1TGEN_Dly = u32Sc0TGEN_Dly - u32Sc1VIP_Dly - SC1_PRE_RUN_DLY + u32HComp;
1794 SC_W2BYTEMSK(0, REG_SC_BK68_61_L, (u32Sc1TGEN_Dly%u32Sc1OneLineDly)*2, 0xFFFF);
1795 SC_W2BYTEMSK(0, REG_SC_BK68_62_L, u32Sc1TGEN_Dly/u32Sc1OneLineDly, 0xFFFF);
1796 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart);
1797 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd);
1798 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart, 0x1FFF); // DE V start
1799 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1, 0x1FFF); // DE V end
1800 }
1801 }
1802 else
1803 {
1804 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pDBreg->u16H_DisStart);
1805 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pDBreg->u16H_DisEnd);
1806 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart);
1807 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd);
1808
1809 //For SkipWaitVsync case, write riu directly.
1810 MDrv_FRC_UpdateMDE(pInstance, gSrcInfo[MAIN_WINDOW].stDispWin);
1811 }
1812
1813 if ((psXCInstPri->u32DeviceID == 1) && (!Hal_SC_3D_IsDualViewMode(pInstance, MAIN_WINDOW)))//follow HW_DESIGN_4K2K_VER = 6 rule
1814 {
1815 //Display window
1816 SC_W2BYTE(0, REG_SC_BK0F_07_L, pDBreg->u16H_DisStart); // Display H start
1817 SC_W2BYTE(0, REG_SC_BK0F_08_L, pDBreg->u16H_DisEnd); // Display H end
1818 SC_W2BYTE(0, REG_SC_BK0F_09_L, pDBreg->u16V_DisStart); // Display V start
1819 SC_W2BYTE(0, REG_SC_BK0F_0A_L, pDBreg->u16V_DisEnd); // Display V end
1820 }
1821 #else
1822 //Display window
1823 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pDBreg->u16H_DisStart); // Display H start
1824 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pDBreg->u16H_DisEnd); // Display H end
1825 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart); // Display V start
1826 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd); // Display V end
1827 #endif
1828
1829 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1830
1831 // 2_frame_mirror setting
1832 #if SUPPORT_2_FRAME_MIRROR
1833 // 2_frmae_mirror cannot work when UC on
1834 if( (gSrcInfo[eWindow].Status2.eFrameStoreNumber == IMAGE_STORE_2_FRAMES) && (!gSrcInfo[eWindow].bInterlace) && (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == 0))
1835 {
1836 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pDBreg->u32DNRBase1); // IPM base1
1837 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0x4000, BIT(14)); // enable two frame mirror
1838
1839 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, 0x0001) == 0 )//compress mode
1840 {
1841 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, 0X20 ,0x00F0 ); // opm_ce_lcnt_inv
1842 }
1843 }
1844 else
1845 {
1846 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == BIT(15))
1847 {
1848 printf("@@ [%s,%5d] 2_frmae_mirror cannot work when UC on \n",__func__,__LINE__);
1849 }
1850
1851 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0x00 , BIT(14)); // disable two frame mirror
1852 }
1853 #endif
1854 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1855 ||(psXCInstPri->u32DeviceID == 1))
1856 {
1857 u32LcentInvReg = REG_SC_BK08_32_L;
1858 }
1859 else
1860 {
1861 u32LcentInvReg = REG_SC_BK33_32_L;
1862 }
1863
1864 if(pDBreg->bOpmLcntInv_En)
1865 {
1866 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(5), BIT(5));
1867 }
1868 else
1869 {
1870 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(5));
1871 }
1872
1873 //monaco/muji 3D mode need control sub for some output format, or else the edge of object in the image may shake
1874 #if (HW_DESIGN_4K2K_VER == 4)
1875 E_XC_3D_OUTPUT_MODE e3DOutputFormat = MDrv_XC_Get_3D_Output_Mode(pInstance);
1876 if((e3DOutputFormat == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
1877 || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM) || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
1878 || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
1879 || (e3DOutputFormat == E_XC_3D_OUTPUT_FRAME_PACKING))
1880 {
1881 //Hal_SC_set_opm_lcnt_inv(pInstance, bopm_lcnt_inv, SUB_WINDOW);
1882 if(pDBreg->bOpmLcntInv_En)
1883 {
1884 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(4), BIT(4));
1885 }
1886 else
1887 {
1888 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(4));
1889 }
1890 }
1891 #endif
1892 }
1893 else
1894 {
1895 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd))
1896 {
1897 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, BIT(15), BIT(15));
1898 }
1899 else
1900 {
1901 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, 0, BIT(15));
1902 }
1903
1904 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_04_L, pDBreg->u32H_PreScalingRatio); // H pre-scaling
1905 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_08_L, pDBreg->u32V_PreScalingRatio); // V pre-scaling
1906
1907 //HVSP
1908 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_27_L, pDBreg->u32H_PostScalingRatio); // H post-scaling
1909 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_29_L, pDBreg->u32V_PostScalingRatio); // V post-scaling
1910
1911 //SCMI
1912 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_58_L, pDBreg->u16VWritelimit); // Set vertical limitation
1913 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5A_L, pDBreg->u32WritelimitBase);
1914 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L, pDBreg->u32DNRBase0); // input address0
1915 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4A_L, pDBreg->u32DNRBase1); // input address1
1916 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4C_L, pDBreg->u32DNRBase2); // input address2
1917 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, pDBreg->u16DNROffset);// input Offset
1918 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, pDBreg->u16DNRFetch); // input fetch
1919 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L, pDBreg->u32OPMBase0); // output address0
1920 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L, pDBreg->u32OPMBase1); // output address1
1921 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_54_L, pDBreg->u32OPMBase2); // output address2
1922 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, pDBreg->u16OPMOffset); // output offset
1923 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, pDBreg->u16OPMFetch); // output fetch
1924 //PIP
1925 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_16_L, pDBreg->u16VLen); // Write V length
1926 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1D_L, (pDBreg->u16LBOffset&0xFF)<<8, 0xFF00);
1927 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1C_L, (pDBreg->u16DispOffset&0xFF)<<8, 0xFF00);
1928
1929 // capture window
1930 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_04_L, pDBreg->u16V_CapStart); // Capture V start
1931 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_05_L, pDBreg->u16H_CapStart); // Capture H start
1932 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, pDBreg->u16V_CapSize); // Capture V size
1933 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, pDBreg->u16H_CapSize); // Capture H size
1934
1935 //Display window
1936 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pDBreg->u16H_DisStart); // Display H start
1937 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, pDBreg->u16H_DisEnd); // Display H end
1938 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pDBreg->u16V_DisStart); // Display V start
1939 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, pDBreg->u16V_DisEnd); // Display V end
1940
1941 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_5C_L, 0x0, 0x1FFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1942
1943 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1944 ||(psXCInstPri->u32DeviceID == 1))
1945 {
1946 u32LcentInvReg = REG_SC_BK08_32_L;
1947 }
1948 else
1949 {
1950 u32LcentInvReg = REG_SC_BK33_32_L;
1951 }
1952
1953 if(pDBreg->bOpmLcntInv_En)
1954 {
1955 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(4), BIT(4));
1956 }
1957 else
1958 {
1959 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(4));
1960 }
1961 }
1962 }
1963 #if ((defined (ANDROID) || defined(MSOS_TYPE_LINUX_KERNEL)) && defined(UFO_XC_DS_PQ))
1964 extern stDS_PQ_REG DS_REG[DS_PQ_MAX_NUM];
1965 extern MS_U16 DS_REG_CNT;
1966 #endif
Hal_SC_SWDS_AddCmd(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1967 void Hal_SC_SWDS_AddCmd(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow)
1968 {
1969 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1970 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1971 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1972 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1973
1974 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] eWindow:%d bDynamicScalingEnable%d \n",__func__,__LINE__,eWindow,pXCResourcePrivate->sthal_SC.bDynamicScalingEnable);
1975 #if ((defined (ANDROID) || defined(MSOS_TYPE_LINUX_KERNEL)) && defined(UFO_XC_DS_PQ))
1976 MS_U16 cnt_x = 0;
1977 MS_U16 u16TempRegVal = 0;
1978 #endif
1979 if(eWindow == MAIN_WINDOW)
1980 {
1981 if(pXCResourcePrivate->sthal_SC.bDynamicScalingEnable)
1982 {
1983 pXCResourcePrivate->sthal_SC.u8DynamicScalingNextIndex[MAIN_WINDOW] = pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[MAIN_WINDOW];
1984
1985 //Command Priority:
1986 //1.GOP
1987 //2.MVOP
1988 //3.XC
1989 //---------------------------------------------------------------------IP Command Start---------------------------------------------------------------------------------------//
1990
1991 MS_U32 ActiveSWClearEn = 0;
1992 MS_U32 u32SW_Reset_Enable = 0;
1993 //ActiveSWClearEn enable in first DS IP command ;
1994 u32SW_Reset_Enable = 0x0400; // bit10: reg_ds_ipm_active_sel: 0:HW 1:SW
1995 ActiveSWClearEn = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK1F_17_L, 0xFFFF);
1996 ActiveSWClearEn |= u32SW_Reset_Enable;
1997
1998 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK1F_17_L,(MS_U16)(ActiveSWClearEn),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1999
2000 //XC_PRINTF("[%s,%5d] bR_FBL:%d bFBL:%d \n",__func__,__LINE__,gSrcInfo[MAIN_WINDOW].bR_FBL,gSrcInfo[MAIN_WINDOW].bFBL);
2001 //XC_PRINTF("[%s,%5d] Crop(x,y,w,h)=(%d,%d,%d,%d) \n",__func__,__LINE__,gSrcInfo[eWindow].stCropWin.x,gSrcInfo[eWindow].stCropWin.y,gSrcInfo[eWindow].stCropWin.width,gSrcInfo[eWindow].stCropWin.height);
2002
2003 if(IsSrcTypeStorage(gSrcInfo[MAIN_WINDOW].enInputSourceType))
2004 {
2005 if((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL))//set MVOP crop info
2006 {
2007 // GET MVOP crop info first
2008 MVOP_Handle stHdl = { E_MVOP_MODULE_MAIN };
2009 MVOP_XCGetCrop stCropInfo;
2010 stCropInfo.u16XStart = gSrcInfo[eWindow].stCropWin.x;
2011 stCropInfo.u16YStart = gSrcInfo[eWindow].stCropWin.y;
2012 stCropInfo.u16XSize = gSrcInfo[eWindow].stCropWin.width;
2013 stCropInfo.u16YSize = gSrcInfo[eWindow].stCropWin.height;
2014
2015 MDrv_MVOP_GetCommand(&stHdl, E_MVOP_CMD_GET_CROP_FOR_XC, &stCropInfo, sizeof(MVOP_XCGetCrop));
2016
2017 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_START,stCropInfo.u16XStart,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0840XXXX
2018 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_START,0x2000|stCropInfo.u16YStart,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0841XXXX
2019 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_SIZE,stCropInfo.u16XSize,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0842XXXX
2020 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_SIZE,stCropInfo.u16YSize,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0843XXXX
2021 pDBreg->u16LBOffset = 0; // mvop do crop, align in 2pixel, so xc don't need crop
2022 }
2023 else
2024 {
2025 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_START,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0840XXXX
2026 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_START,0x2000,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0841XXXX
2027 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_SIZE,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0842XXXX
2028 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_SIZE,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0843XXXX
2029 }
2030 }
2031
2032 //H pre-scaling
2033 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_04_L,(MS_U16)(pDBreg->u32H_PreScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8104XXXX
2034 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_05_L,(MS_U16)(pDBreg->u32H_PreScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8105XXXX
2035 //V pre-scaling
2036 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_08_L,(MS_U16)(pDBreg->u32V_PreScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8108XXXX
2037 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_09_L,(MS_U16)(pDBreg->u32V_PreScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8109XXXX
2038
2039 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_18_L,(MS_U16)(pDBreg->u16VWritelimit>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8918XXXX
2040
2041 if(IsVMirrorMode(MAIN_WINDOW))
2042 {
2043 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_08_L,(MS_U16)(pDBreg->u32DNRBase0>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
2044 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_09_L,(MS_U16)(pDBreg->u32DNRBase0>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
2045 }
2046 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_0F_L,(MS_U16)(pDBreg->u16DNRFetch>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 890FXXXX
2047
2048 //H_mirror_offset
2049 if(IsHMirrorMode(MAIN_WINDOW)||IsVMirrorMode(MAIN_WINDOW))
2050 {
2051 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] VB_width:%d framNum:%d u8BitPerPixel:%d \n",__func__,__LINE__,gSrcInfo[MAIN_WINDOW].Status2.u16VirtualBox_Width,MDrv_XC_TransFrameNumToFactor(pInstance,gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber, gSrcInfo[MAIN_WINDOW].bLinearMode, _FIELD_PACKING_MODE_SUPPORTED),gSrcInfo[MAIN_WINDOW].u8BitPerPixel);
2052
2053 MS_U32 H_mirror_offset;
2054 H_mirror_offset = (gSrcInfo[eWindow].Status2.u16VirtualBox_Width * gSrcInfo[eWindow].u8BitPerPixel * 2 / 8 * MDrv_XC_TransFrameNumToFactor(pInstance,gSrcInfo[eWindow].Status2.eFrameStoreNumber, gSrcInfo[eWindow].bLinearMode, _FIELD_PACKING_MODE_SUPPORTED)) / BYTE_PER_WORD;
2055
2056 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_1C_L,H_mirror_offset,DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 891CXXXX
2057 }
2058 else
2059 {
2060 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_1C_L,0x0000,DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 891CXXXX
2061 }
2062
2063 //Cap info
2064 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
2065 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
2066 pDBreg->u16H_CapSize |= 0x8000;
2067 else
2068 pDBreg->u16H_CapSize |= 0x0000;
2069
2070 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK01_06_L,(MS_U16)(pDBreg->u16V_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8086XXXX
2071 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK01_07_L,(MS_U16)(pDBreg->u16H_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8087XXXX
2072
2073 //toggle reg_ds_ipm_active_set in last DS IP command
2074 MS_U32 u32SW_Reset_IPM = 0;
2075 u32SW_Reset_IPM = 0x0100 ;//bit8 : reg_ds_ipm_active_set
2076 ActiveSWClearEn |= u32SW_Reset_IPM;
2077 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK1F_17_L,(MS_U16)(ActiveSWClearEn),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
2078 //---------------------------------------------------------------------IP Command End---------------------------------------------------------------------------------------//
2079
2080 //---------------------------------------------------------------------OP Command Start---------------------------------------------------------------------------------------//
2081 if(!((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL))) //FB case
2082 {
2083 //H post-scaling
2084 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_07_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9187XXXX
2085 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_08_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9188XXXX
2086 //V post-scaling
2087 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_09_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9189XXXX
2088 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_0A_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 918AXXXX
2089
2090 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8910XXXX
2091 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_11_L,(MS_U16)(pDBreg->u32OPMBase0>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8911XXXX
2092 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_17_L,(MS_U16)(pDBreg->u16OPMFetch>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM fetch //0xFFFF0009 8917XXXX
2093 //Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len
2094 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
2095 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
2096 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len //0xFFFF0009 9015XXXX
2097
2098 //STGEN setting
2099 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_23_L,(MS_U16)(0x0001),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2100
2101 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled)&&(psXCInstPri->u32DeviceID != 1))
2102 {
2103 if(MHal_FRC_IsFHDToFSC(pInstance,MAIN_WINDOW))
2104 {
2105 //H_MDE start and end
2106 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_05_L,(MS_U16)((pDBreg->u16H_DisStart/2 +1) & ~1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2107 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_06_L,(MS_U16)( ((pDBreg->u16H_DisStart/2 +1) & ~1) + gSrcInfo[eWindow].stDispWin.width/2 - 1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2108 //V_FDE start and end
2109 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0D_L,(MS_U16)( (pDBreg->u16V_DisStart/2)+ VSTART_OFFSET),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2110 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0E_L,(MS_U16)((pDBreg->u16V_DisEnd/2) + VSTART_OFFSET),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2111 //H_FDE start and end
2112 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_03_L,(MS_U16)((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart/2+1) & ~1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2113 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_04_L,(MS_U16)(((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart/2+1) & ~1) + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width/2 -1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2114 //V_FDE start and end
2115 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0B_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart/2),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2116 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0C_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart/2 + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height/2 -1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2117 }
2118 else
2119 {
2120 //H_MDE start and end
2121 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_05_L,(MS_U16)(pDBreg->u16H_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2122 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_06_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2123 //V_FDE start and end
2124 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0D_L,(MS_U16)(pDBreg->u16V_DisStart + VSTART_OFFSET),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2125 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0E_L,(MS_U16)(pDBreg->u16V_DisEnd + VSTART_OFFSET ),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2126 //H_FDE start and end
2127 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_03_L,(MS_U16)((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart) & ~1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2128 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_04_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width -1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2129 //V_FDE start and end
2130 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0B_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2131 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_0C_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height -1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2132 }
2133 }
2134
2135 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK68_23_L,(MS_U16)(0x0000),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2136
2137
2138 //Disp info
2139 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled && pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)&&(psXCInstPri->u32DeviceID != 1))
2140 {
2141 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
2142 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart +pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width-1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
2143 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
2144 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height-1),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
2145 }
2146 else
2147 {
2148 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pDBreg->u16H_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
2149 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
2150 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pDBreg->u16V_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
2151 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pDBreg->u16V_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
2152 }
2153
2154 //FSC setting
2155 if(MHal_FRC_IsFHDToFSC(pInstance,MAIN_WINDOW))
2156 {
2157 //H scaling ratio
2158 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x10, 0x0308, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2159 //V scaling ratio
2160 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x14, 0x0308, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2161 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x3A, 0x1080, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2162 //Initial fac
2163 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x04, 0x000C, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2164 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x08, 0x000C, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2165 //V_12L
2166 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x26, 0x1000, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2167 //scaling filter
2168 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x16, 0x4444, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2169 //input V size
2170 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x0A, 0x0438, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2171 //input H size/2
2172 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x34, 0x03C0, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2173
2174 if(MHal_FRC_IsSupportFRC_byEfuse(pInstance))
2175 {
2176 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1457,0x02, 0x0100, 0x0100,DS_OP,&PSTXC_DS_CMDCNT);
2177 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x144C,0xA0, 0x0001, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2178 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1472,0x40, 0x0001, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2179 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1471,0x60, 0x0100, 0x0100,DS_OP,&PSTXC_DS_CMDCNT);
2180 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1470,0x50, 0x0010, 0x0010,DS_OP,&PSTXC_DS_CMDCNT);
2181 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1426,0x20, 0x0001, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2182 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1472,0x80, 0x0001, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2183 }
2184 }
2185 else
2186 {
2187 //H scaling ratio
2188 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x10, 0x0110, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2189 //V scaling ratio
2190 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x14, 0x0110, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2191 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x3A, 0x1080, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2192 //Initial fac
2193 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x04, 0x0000, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2194 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x08, 0x0000, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2195 //V_12L
2196 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x26, 0x0000, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2197 //scaling filter
2198 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x16, 0x0000, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2199 //input V size
2200 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x0A, 0x0870, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2201 //input H size/2
2202 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1423,0x34, 0x0780, 0xFFFF,DS_OP,&PSTXC_DS_CMDCNT);
2203
2204 if(MHal_FRC_IsSupportFRC_byEfuse(pInstance))
2205 {
2206 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1457,0x02, 0x0000, 0x0100,DS_OP,&PSTXC_DS_CMDCNT);
2207 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x144C,0xA0, 0x0000, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2208 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1472,0x40, 0x0000, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2209 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1471,0x60, 0x0000, 0x0100,DS_OP,&PSTXC_DS_CMDCNT);
2210 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1470,0x50, 0x0000, 0x0010,DS_OP,&PSTXC_DS_CMDCNT);
2211 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1426,0x20, 0x0000, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2212 Hal_SC_WriteSWDSCommand_NonXC(pInstance,MAIN_WINDOW,0x1472,0x80, 0x0000, 0x0001,DS_OP,&PSTXC_DS_CMDCNT);
2213 }
2214 }
2215 }
2216 else //RFBL or FBL case
2217 {
2218 //H post-scaling
2219 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_07_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9187XXXX
2220 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_08_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9188XXXX
2221 //V post-scaling
2222 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_09_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9189XXXX
2223 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_0A_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 918AXXXX
2224
2225 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8910XXXX
2226 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_11_L,(MS_U16)(pDBreg->u32OPMBase0>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8911XXXX
2227 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_17_L,(MS_U16)(pDBreg->u16OPMFetch>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // OPM fetch //0xFFFF0009 8917XXXX
2228 //Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len
2229 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
2230 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
2231 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); // V Len //0xFFFF0009 9015XXXX
2232 //Disp info
2233 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pDBreg->u16H_DisStart),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
2234 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
2235 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pDBreg->u16V_DisStart),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
2236 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pDBreg->u16V_DisEnd),DS_IP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
2237 }
2238 //---------------------------------------------------------------------OP Command End---------------------------------------------------------------------------------------//
2239 #if ((defined (ANDROID) || defined(MSOS_TYPE_LINUX_KERNEL)) && defined(UFO_XC_DS_PQ))
2240 if(DS_REG_CNT > DS_PQ_MAX_NUM)
2241 {
2242 MS_ASSERT(0);
2243 }
2244 if(eWindow != MAIN_WINDOW)
2245 {
2246 MS_ASSERT(0);
2247 }
2248 for(cnt_x = 0 ;cnt_x < DS_REG_CNT; cnt_x++)
2249 {
2250 //printf("\033[1;32m[%s:%d]u16Addr=0x%x,u16Value=0x%x,u16Mask=0x%x\033[m\n",__FUNCTION__,__LINE__,
2251 //DS_REG[cnt_x].u16Addr | 0x130000,
2252 //DS_REG[cnt_x].u16Value,
2253 //DS_REG[cnt_x].u16Mask);
2254 u16TempRegVal = SC_R2BYTE(psXCInstPri->u32DeviceID, DS_REG[cnt_x].u16Addr);
2255 u16TempRegVal = (u16TempRegVal & ~DS_REG[cnt_x].u16Mask) | DS_REG[cnt_x].u16Value;
2256 //printf("\033[1;31m[%s:%d][0x%x]Org=0x%x,Mod=0x%x\033[m\n",__FUNCTION__,__LINE__,DS_REG[cnt_x].u16Addr,SC_R2BYTE(psXCInstPri->u32DeviceID, DS_REG[cnt_x].u16Addr),u16TempRegVal);
2257 Hal_SC_WriteSWDSCommand(pInstance,eWindow,DS_REG[cnt_x].u16Addr,u16TempRegVal,DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
2258 }
2259 DS_REG_CNT = 0;
2260 #endif
2261 MS_U8 u8MaxCmdCnt = pXCResourcePrivate->sthal_SC.u8DynamicScalingIndexDepth * (Hal_XC_MLoad_Get_64Bits_MIU_Bus_Sel(pInstance) + 1);
2262
2263 //XC_PRINTF("[%s,%5d] u16CMDCNT_IPM:%d u8MaxCnt:%d \n",__func__,__LINE__,PSTXC_DS_CMDCNT.u16CMDCNT_IPM,u8MaxCmdCnt);
2264 //XC_PRINTF("[%s,%5d] u16CMDCNT_OPM:%d u8MaxCnt:%d \n",__func__,__LINE__,PSTXC_DS_CMDCNT.u16CMDCNT_OPM,u8MaxCmdCnt);
2265 if(PSTXC_DS_CMDCNT.u16CMDCNT_IPM < u8MaxCmdCnt)
2266 {
2267 Hal_SC_Add_NullCommand(pInstance,MAIN_WINDOW,DS_IP,&PSTXC_DS_CMDCNT);
2268 }
2269 if(!((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL)))
2270 {
2271 if(PSTXC_DS_CMDCNT.u16CMDCNT_OPM < u8MaxCmdCnt)
2272 {
2273 Hal_SC_Add_NullCommand(pInstance,MAIN_WINDOW,DS_OP,&PSTXC_DS_CMDCNT);
2274 }
2275 }
2276 }
2277 }
2278 }
2279
Hal_SC_SWDS_Fire(void * pInstance,SCALER_WIN eWindow)2280 void Hal_SC_SWDS_Fire(void *pInstance, SCALER_WIN eWindow)
2281 {
2282 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2283 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2284 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2285 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2286
2287 pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow]++;
2288 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] CurIdx:%d \n",__func__,__LINE__,(int)pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow]);
2289
2290 pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[eWindow] = pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow] % DS_BUFFER_NUM_EX;
2291 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] CurIdx_Ring:%d \n",__func__,__LINE__,(int)pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[eWindow])
2292 }
2293
Hal_SC_VIP_Peaking_Setting(void * pInstance,SCALER_WIN eWindow)2294 E_APIXC_ReturnValue Hal_SC_VIP_Peaking_Setting(void *pInstance, SCALER_WIN eWindow)
2295 {
2296 UNUSED(eWindow);
2297 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
2298 }
2299
Hal_SC_support_source_to_ve(void * pInstance,MS_U16 * pOutputCapability)2300 E_APIXC_ReturnValue Hal_SC_support_source_to_ve(void *pInstance, MS_U16* pOutputCapability)
2301 {
2302 *pOutputCapability = E_XC_IP | E_XC_OP2 | E_XC_OVERLAP;
2303 return E_APIXC_RET_OK;
2304 }
2305
Hal_SC_set_output_capture_enable(void * pInstance,MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)2306 E_APIXC_ReturnValue Hal_SC_set_output_capture_enable(void *pInstance, MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)
2307 {
2308 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2309 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2310 MS_BOOL bCaptureEna;
2311 MS_U16 u16CaptureSrc;
2312 // Current only support IP and OP2
2313 bCaptureEna = bEnable;
2314 switch(eSourceToVE)
2315 {
2316 case E_XC_VOP2:
2317 case E_XC_OVERLAP: // compatible to previous IC, overlap is before osd blending
2318 u16CaptureSrc = 0;
2319 break;
2320 case E_XC_OP2:
2321 u16CaptureSrc = 1;
2322 break;
2323 case E_XC_BRI:
2324 u16CaptureSrc = 3;
2325 break;
2326 default:
2327 u16CaptureSrc = 0;
2328 bCaptureEna = FALSE;
2329 break;
2330 }
2331
2332 if(bCaptureEna)
2333 {
2334 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(11), BIT(11)); // Disable
2335 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, u16CaptureSrc<<4, BMASK(7:4)); // Disable
2336 }
2337 else
2338 {
2339 //DIP and VE Opcapture both need enable this bit, so dont disable it.
2340 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0, BIT(11)); // Disable
2341 }
2342 return E_APIXC_RET_OK; // Support Scaler OP -> VE
2343 }
2344
2345 /******************************************************************************/
2346 ///Set output DE window size
2347 ///@param pstWindow \b IN
2348 ///- pointer to window information
2349 /******************************************************************************/
Hal_SC_set_de_window(void * pInstance,XC_PANEL_INFO * pPanel_Info)2350 void Hal_SC_set_de_window(void *pInstance, XC_PANEL_INFO *pPanel_Info)
2351 {
2352 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2353 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2354 #ifdef new_chakra
2355 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pPanel_Info->u16HStart); // DE H start
2356 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, pPanel_Info->u16HStart + pPanel_Info->u16Width - 1); // DE H end
2357 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pPanel_Info->u16VStart); // DE V start
2358 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pPanel_Info->u16VStart + pPanel_Info->u16Height - 1); // DE V end
2359 #else
2360 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pPanel_Info->u16HStart); // DE H start
2361 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, pPanel_Info->u16HStart + pPanel_Info->u16Width - 1); // DE H end
2362 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pSrcInfo->u8DE_V_Start); // DE V start
2363 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pSrcInfo->u16DE_V_End); // DE V end
2364 #endif
2365 }
2366
Hal_SC_get_disp_de_window(void * pInstance,MS_WINDOW_TYPE * pWin)2367 void Hal_SC_get_disp_de_window(void *pInstance, MS_WINDOW_TYPE *pWin)
2368 {
2369 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2370 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2371 pWin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L);
2372 pWin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L);
2373 pWin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L) - pWin->x + 1;
2374 pWin->height= SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L) - pWin->y + 1;
2375 }
2376
Hal_SC_Get_DNRBase0(void * pInstance,SCALER_WIN eWindow)2377 MS_PHY Hal_SC_Get_DNRBase0(void *pInstance, SCALER_WIN eWindow)
2378 {
2379 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2380 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2381 if(eWindow == MAIN_WINDOW)
2382 {
2383 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L); // input address0
2384 }
2385 else
2386 {
2387 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L); // input address0
2388 }
2389 }
2390
Hal_SC_Get_DNRBase1(void * pInstance,SCALER_WIN eWindow)2391 MS_PHY Hal_SC_Get_DNRBase1(void *pInstance, SCALER_WIN eWindow)
2392 {
2393 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2394 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2395 if(eWindow == MAIN_WINDOW)
2396 {
2397 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L); // input address1
2398 }
2399 else
2400 {
2401 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4A_L); // input address1
2402 }
2403 }
2404
Hal_SC_Get_OPMBase0(void * pInstance,SCALER_WIN eWindow)2405 MS_PHY Hal_SC_Get_OPMBase0(void *pInstance, SCALER_WIN eWindow)
2406 {
2407 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2408 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2409 if(eWindow == MAIN_WINDOW)
2410 {
2411 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L); // output address0
2412 }
2413 else
2414 {
2415 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L); // output address0
2416 }
2417 }
2418
Hal_SC_Get_OPMBase1(void * pInstance,SCALER_WIN eWindow)2419 MS_PHY Hal_SC_Get_OPMBase1(void *pInstance, SCALER_WIN eWindow)
2420 {
2421 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2422 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2423 if(eWindow == MAIN_WINDOW)
2424 {
2425 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L); // output address1
2426 }
2427 else
2428 {
2429 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L); // output address1
2430 }
2431 }
2432
Hal_SC_Get_FRCMBaseAddr(void * pInstance,MS_U8 u8id,SCALER_WIN eWindow)2433 MS_PHY Hal_SC_Get_FRCMBaseAddr(void *pInstance, MS_U8 u8id,SCALER_WIN eWindow)
2434 {
2435 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2436 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2437 if(eWindow == MAIN_WINDOW)
2438 {
2439 if(u8id == 0)
2440 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_08_L); // frcm_w base address0
2441 else if(u8id == 1)
2442 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L); // frcm_w base address1
2443 else //if(u8id == 2)
2444 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_0C_L); // frcm_w base address2
2445 }
2446 else
2447 {
2448 if(u8id == 0)
2449 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_48_L); // frcm_w base address0
2450 else if(u8id == 1)
2451 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_4A_L); // frcm_w base address1
2452 else //if(u8id == 2)
2453 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_4C_L); // frcm_w base address2
2454 }
2455 }
2456
Hal_SC_Get_LBOffset(void * pInstance,SCALER_WIN eWindow)2457 MS_U8 Hal_SC_Get_LBOffset(void *pInstance, SCALER_WIN eWindow)
2458 {
2459 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2460 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2461 if(eWindow == MAIN_WINDOW)
2462 {
2463 return SC_R2BYTEMSK(0, REG_SC_BK20_1D_L, 0x00FF);
2464 }
2465 else
2466 {
2467 return (SC_R2BYTEMSK(0, REG_SC_BK20_1D_L, 0xFF00) >> 8);
2468 }
2469 }
2470
Hal_SC_Set_LBOffset(void * pInstance,MS_U8 u8LBOffset,SCALER_WIN eWindow)2471 void Hal_SC_Set_LBOffset(void *pInstance, MS_U8 u8LBOffset, SCALER_WIN eWindow)
2472 {
2473 if(eWindow == MAIN_WINDOW)
2474 {
2475 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u8LBOffset, 0x00FF);
2476 }
2477 else
2478 {
2479 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u8LBOffset << 8, 0xFF00);
2480 }
2481 }
2482
Hal_SC_set_DNRBase0(void * pInstance,MS_PHY u32DNRBase0,SCALER_WIN eWindow)2483 void Hal_SC_set_DNRBase0(void *pInstance, MS_PHY u32DNRBase0, SCALER_WIN eWindow)
2484 {
2485 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2486 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2487 if(eWindow == MAIN_WINDOW)
2488 {
2489 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2490 }
2491 else
2492 {
2493 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2494 }
2495 }
2496
Hal_SC_set_DNRBase1(void * pInstance,MS_PHY u32DNRBase1,SCALER_WIN eWindow)2497 void Hal_SC_set_DNRBase1(void *pInstance, MS_PHY u32DNRBase1, SCALER_WIN eWindow)
2498 {
2499 UNUSED(u32DNRBase1);
2500 UNUSED(eWindow);
2501 }
2502
Hal_SC_set_DNRBase2(void * pInstance,MS_PHY u32DNRBase2,SCALER_WIN eWindow)2503 void Hal_SC_set_DNRBase2(void *pInstance, MS_PHY u32DNRBase2, SCALER_WIN eWindow)
2504 {
2505 UNUSED(u32DNRBase2);
2506 UNUSED(eWindow);
2507 }
2508
Hal_SC_set_OPMBase0(void * pInstance,MS_PHY u32OPMBase0,SCALER_WIN eWindow)2509 void Hal_SC_set_OPMBase0(void *pInstance, MS_PHY u32OPMBase0, SCALER_WIN eWindow)
2510 {
2511 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2512 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2513 if(eWindow == MAIN_WINDOW)
2514 {
2515 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2516 }
2517 else
2518 {
2519 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2520 }
2521 }
2522
Hal_SC_set_OPMBase1(void * pInstance,MS_PHY u32OPMBase1,SCALER_WIN eWindow)2523 void Hal_SC_set_OPMBase1(void *pInstance, MS_PHY u32OPMBase1, SCALER_WIN eWindow)
2524 {
2525 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2526 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2527 if(eWindow == MAIN_WINDOW)
2528 {
2529 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2530 }
2531 else
2532 {
2533 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2534 }
2535 }
2536
Hal_SC_set_OPMBase2(void * pInstance,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2537 void Hal_SC_set_OPMBase2(void *pInstance, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2538 {
2539 UNUSED(u32OPMBase2);
2540 UNUSED(eWindow);
2541 }
2542
Hal_SC_set_FRCM_WBase0(void * pInstance,MS_PHY u32FRCM_WBase0,SCALER_WIN eWindow)2543 void Hal_SC_set_FRCM_WBase0(void *pInstance, MS_PHY u32FRCM_WBase0, SCALER_WIN eWindow)
2544 {
2545 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2546 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2547 if(eWindow == MAIN_WINDOW)
2548 {
2549 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_08_L, u32FRCM_WBase0 / BYTE_PER_WORD); // input address0
2550 }
2551 else
2552 {
2553 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_48_L, u32FRCM_WBase0 / BYTE_PER_WORD); // input address0
2554 }
2555 }
2556
Hal_SC_set_FRCM_WBase1(void * pInstance,MS_PHY u32FRCM_WBase1,SCALER_WIN eWindow)2557 void Hal_SC_set_FRCM_WBase1(void *pInstance, MS_PHY u32FRCM_WBase1, SCALER_WIN eWindow)
2558 {
2559 UNUSED(u32FRCM_WBase1);
2560 UNUSED(eWindow);
2561 }
2562
Hal_SC_set_FRCM_WBase2(void * pInstance,MS_PHY u32FRCM_WBase2,SCALER_WIN eWindow)2563 void Hal_SC_set_FRCM_WBase2(void *pInstance, MS_PHY u32FRCM_WBase2, SCALER_WIN eWindow)
2564 {
2565 UNUSED(u32FRCM_WBase2);
2566 UNUSED(eWindow);
2567 }
2568
Hal_SC_set_FRCM_RBase0(void * pInstance,MS_PHY u32FRCM_RBase0,SCALER_WIN eWindow)2569 void Hal_SC_set_FRCM_RBase0(void *pInstance, MS_PHY u32FRCM_RBase0, SCALER_WIN eWindow)
2570 {
2571 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2572 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2573 if(eWindow == MAIN_WINDOW)
2574 {
2575 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_10_L, u32FRCM_RBase0 / BYTE_PER_WORD); // input address0
2576 }
2577 else
2578 {
2579 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_50_L, u32FRCM_RBase0 / BYTE_PER_WORD); // input address0
2580 }
2581 }
2582
Hal_SC_set_FRCM_RBase1(void * pInstance,MS_PHY u32FRCM_RBase1,SCALER_WIN eWindow)2583 void Hal_SC_set_FRCM_RBase1(void *pInstance, MS_PHY u32FRCM_RBase1, SCALER_WIN eWindow)
2584 {
2585 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2586 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2587 if(eWindow == MAIN_WINDOW)
2588 {
2589 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_12_L, u32FRCM_RBase1 / BYTE_PER_WORD); // input address1
2590 }
2591 else
2592 {
2593 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_52_L, u32FRCM_RBase1 / BYTE_PER_WORD); // input address1
2594 }
2595 }
2596
Hal_SC_set_FRCM_RBase2(void * pInstance,MS_PHY u32FRCM_RBase2,SCALER_WIN eWindow)2597 void Hal_SC_set_FRCM_RBase2(void *pInstance, MS_PHY u32FRCM_RBase2, SCALER_WIN eWindow)
2598 {
2599 UNUSED(u32FRCM_RBase2);
2600 UNUSED(eWindow);
2601 }
2602
Hal_SC_set_Dual_DNRBase0(void * pInstance,MS_PHY u32DNRBase0,SCALER_WIN eWindow)2603 void Hal_SC_set_Dual_DNRBase0(void *pInstance, MS_PHY u32DNRBase0, SCALER_WIN eWindow)
2604 {
2605 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2606 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2607 // Dual just support scaler0, main only
2608 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2609 {
2610 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2611 return;
2612 }
2613 if(eWindow == MAIN_WINDOW)
2614 {
2615 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_08_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2616 }
2617 else
2618 {
2619 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_48_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2620 }
2621 }
2622
Hal_SC_set_Dual_DNRBase1(void * pInstance,MS_PHY u32DNRBase1,SCALER_WIN eWindow)2623 void Hal_SC_set_Dual_DNRBase1(void *pInstance, MS_PHY u32DNRBase1, SCALER_WIN eWindow)
2624 {
2625 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2626 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2627 // Dual just support scaler0, main only
2628 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2629 {
2630 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2631 return;
2632 }
2633 if(eWindow == MAIN_WINDOW)
2634 {
2635 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_1A_L, u32DNRBase1 / BYTE_PER_WORD); // input address0
2636 }
2637 else
2638 {
2639 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_5A_L, u32DNRBase1 / BYTE_PER_WORD); // input address0
2640 }
2641
2642 }
2643
Hal_SC_set_Dual_DNRBase2(void * pInstance,MS_PHY u32DNRBase2,SCALER_WIN eWindow)2644 void Hal_SC_set_Dual_DNRBase2(void *pInstance, MS_PHY u32DNRBase2, SCALER_WIN eWindow)
2645 {
2646 UNUSED(u32DNRBase2);
2647 UNUSED(eWindow);
2648 }
2649
Hal_SC_set_Dual_OPMBase0(void * pInstance,MS_PHY u32OPMBase0,SCALER_WIN eWindow)2650 void Hal_SC_set_Dual_OPMBase0(void *pInstance, MS_PHY u32OPMBase0, SCALER_WIN eWindow)
2651 {
2652 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2653 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2654 // Dual just support scaler0, main only
2655 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2656 {
2657 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2658 return;
2659 }
2660 if(eWindow == MAIN_WINDOW)
2661 {
2662 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_10_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2663 }
2664 else
2665 {
2666 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_50_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2667 }
2668 }
2669
Hal_SC_set_Dual_OPMBase1(void * pInstance,MS_PHY u32OPMBase1,SCALER_WIN eWindow)2670 void Hal_SC_set_Dual_OPMBase1(void *pInstance, MS_PHY u32OPMBase1, SCALER_WIN eWindow)
2671 {
2672 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2673 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2674 // Dual just support scaler0, main only
2675 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2676 {
2677 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
2678 return;
2679 }
2680 if(eWindow == MAIN_WINDOW)
2681 {
2682 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_12_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2683 }
2684 else
2685 {
2686 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_52_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2687 }
2688 }
2689
Hal_SC_set_Dual_OPMBase2(void * pInstance,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2690 void Hal_SC_set_Dual_OPMBase2(void *pInstance, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2691 {
2692 UNUSED(u32OPMBase2);
2693 UNUSED(eWindow);
2694 }
2695
Hal_SC_set_WriteVLength(void * pInstance,SCALER_WIN eWindow)2696 void Hal_SC_set_WriteVLength(void *pInstance, SCALER_WIN eWindow)
2697 {
2698 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2699 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2700 if(eWindow == MAIN_WINDOW)
2701 {
2702 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_15_L, 0x0); // Write V length
2703 }
2704 else
2705 {
2706 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_16_L, 0x0); // Write V length
2707 }
2708 }
2709
Hal_SC_set_memoryaddress(void * pInstance,MS_PHY u32DNRBase0,MS_PHY u32DNRBase1,MS_PHY u32DNRBase2,MS_PHY u32OPMBase0,MS_PHY u32OPMBase1,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2710 void Hal_SC_set_memoryaddress(void *pInstance, MS_PHY u32DNRBase0, MS_PHY u32DNRBase1, MS_PHY u32DNRBase2, MS_PHY u32OPMBase0, MS_PHY u32OPMBase1, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2711 {
2712 Hal_SC_set_DNRBase0(pInstance, u32DNRBase0, eWindow);
2713 Hal_SC_set_DNRBase1(pInstance, u32DNRBase1, eWindow);
2714 Hal_SC_set_DNRBase2(pInstance, u32DNRBase2, eWindow);
2715 Hal_SC_set_OPMBase0(pInstance, u32OPMBase0, eWindow);
2716 Hal_SC_set_OPMBase1(pInstance, u32OPMBase1, eWindow);
2717 Hal_SC_set_OPMBase2(pInstance, u32OPMBase2, eWindow);
2718 }
2719
Hal_SC_set_frcm_memoryaddress(void * pInstance,MS_PHY u32FRCM_WBase0,MS_PHY u32FRCM_WBase1,MS_PHY u32FRCM_WBase2,MS_PHY u32FRCM_RBase0,MS_PHY u32FRCM_RBase1,MS_PHY u32FRCM_RBase2,SCALER_WIN eWindow)2720 void Hal_SC_set_frcm_memoryaddress(void *pInstance, MS_PHY u32FRCM_WBase0, MS_PHY u32FRCM_WBase1, MS_PHY u32FRCM_WBase2, MS_PHY u32FRCM_RBase0, MS_PHY u32FRCM_RBase1, MS_PHY u32FRCM_RBase2, SCALER_WIN eWindow)
2721 {
2722 Hal_SC_set_FRCM_WBase0(pInstance, u32FRCM_WBase0, eWindow);
2723 Hal_SC_set_FRCM_WBase1(pInstance, u32FRCM_WBase1, eWindow);
2724 Hal_SC_set_FRCM_WBase2(pInstance, u32FRCM_WBase2, eWindow);
2725 Hal_SC_set_FRCM_RBase0(pInstance, u32FRCM_RBase0, eWindow);
2726 Hal_SC_set_FRCM_RBase1(pInstance, u32FRCM_RBase1, eWindow);
2727 Hal_SC_set_FRCM_RBase2(pInstance, u32FRCM_RBase2, eWindow);
2728 }
2729
Hal_SC_set_dual_memoryaddress(void * pInstance,MS_PHY u32DNRBase0,MS_PHY u32DNRBase1,MS_PHY u32DNRBase2,MS_PHY u32OPMBase0,MS_PHY u32OPMBase1,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2730 void Hal_SC_set_dual_memoryaddress(void *pInstance, MS_PHY u32DNRBase0, MS_PHY u32DNRBase1, MS_PHY u32DNRBase2, MS_PHY u32OPMBase0, MS_PHY u32OPMBase1, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2731 {
2732 Hal_SC_set_Dual_DNRBase0(pInstance, u32DNRBase0, eWindow);
2733 Hal_SC_set_Dual_DNRBase1(pInstance, u32DNRBase1, eWindow);
2734 Hal_SC_set_Dual_DNRBase2(pInstance, u32DNRBase2, eWindow);
2735 Hal_SC_set_Dual_OPMBase0(pInstance, u32OPMBase0, eWindow);
2736 Hal_SC_set_Dual_OPMBase1(pInstance, u32OPMBase1, eWindow);
2737 Hal_SC_set_Dual_OPMBase2(pInstance, u32OPMBase2, eWindow);
2738 }
2739
Hal_SC_get_miu0mask(void)2740 static SC_MIUMASK_t Hal_SC_get_miu0mask(void)
2741 {
2742 SC_MIUMASK_t mask;
2743
2744 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU0_G0_REQUEST_MASK);
2745 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU0_G1_REQUEST_MASK);
2746 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU0_G2_REQUEST_MASK);
2747 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU0_G3_REQUEST_MASK);
2748 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU0_G4_REQUEST_MASK);
2749 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU0_G5_REQUEST_MASK);
2750 mask.u16MiuG6Mask = MDrv_Read2Byte(MIU0_G6_REQUEST_MASK);
2751
2752 return mask;
2753 }
2754
Hal_SC_get_miu1mask(void)2755 static SC_MIUMASK_t Hal_SC_get_miu1mask(void)
2756 {
2757 SC_MIUMASK_t mask;
2758
2759 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU1_G0_REQUEST_MASK);
2760 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU1_G1_REQUEST_MASK);
2761 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU1_G2_REQUEST_MASK);
2762 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU1_G3_REQUEST_MASK);
2763 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU1_G4_REQUEST_MASK);
2764 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU1_G5_REQUEST_MASK);
2765 mask.u16MiuG6Mask = MDrv_Read2Byte(MIU1_G6_REQUEST_MASK);
2766
2767 return mask;
2768 }
2769
Hal_SC_get_miu2mask(void)2770 static SC_MIUMASK_t Hal_SC_get_miu2mask(void)
2771 {
2772 SC_MIUMASK_t mask;
2773
2774 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU2_G0_REQUEST_MASK);
2775 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU2_G1_REQUEST_MASK);
2776 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU2_G2_REQUEST_MASK);
2777 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU2_G3_REQUEST_MASK);
2778 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU2_G4_REQUEST_MASK);
2779 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU2_G5_REQUEST_MASK);
2780 mask.u16MiuG6Mask = MDrv_Read2Byte(MIU2_G6_REQUEST_MASK);
2781
2782 return mask;
2783 }
2784
Hal_SC_set_miu0mask(SC_MIUMASK_t mask)2785 static void Hal_SC_set_miu0mask(SC_MIUMASK_t mask)
2786 {
2787 MDrv_Write2Byte(MIU0_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2788 MDrv_Write2Byte(MIU0_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2789 MDrv_Write2Byte(MIU0_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2790 MDrv_Write2Byte(MIU0_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2791 MDrv_Write2Byte(MIU0_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2792 MDrv_Write2Byte(MIU0_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2793 MDrv_Write2Byte(MIU0_G6_REQUEST_MASK, mask.u16MiuG6Mask);
2794
2795 }
2796
Hal_SC_set_miu1mask(SC_MIUMASK_t mask)2797 static void Hal_SC_set_miu1mask(SC_MIUMASK_t mask)
2798 {
2799 MDrv_Write2Byte(MIU1_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2800 MDrv_Write2Byte(MIU1_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2801 MDrv_Write2Byte(MIU1_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2802 MDrv_Write2Byte(MIU1_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2803 MDrv_Write2Byte(MIU1_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2804 MDrv_Write2Byte(MIU1_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2805 MDrv_Write2Byte(MIU1_G5_REQUEST_MASK, mask.u16MiuG6Mask);
2806 }
2807
Hal_SC_set_miu2mask(SC_MIUMASK_t mask)2808 static void Hal_SC_set_miu2mask(SC_MIUMASK_t mask)
2809 {
2810 MDrv_Write2Byte(MIU2_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2811 MDrv_Write2Byte(MIU2_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2812 MDrv_Write2Byte(MIU2_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2813 MDrv_Write2Byte(MIU2_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2814 MDrv_Write2Byte(MIU2_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2815 MDrv_Write2Byte(MIU2_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2816 MDrv_Write2Byte(MIU2_G6_REQUEST_MASK, mask.u16MiuG6Mask);
2817 }
2818
Hal_SC_Enable_MiuMask(void * pInstance)2819 void Hal_SC_Enable_MiuMask(void *pInstance)
2820 {
2821 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2822 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2823 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2824 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2825 pXCResourcePrivate->sthal_SC.Miu0MaskOld = Hal_SC_get_miu0mask();
2826 pXCResourcePrivate->sthal_SC.Miu1MaskOld = Hal_SC_get_miu1mask();
2827 pXCResourcePrivate->sthal_SC.Miu2MaskOld = Hal_SC_get_miu2mask();
2828
2829 pXCResourcePrivate->sthal_SC.Miu0Mask = pXCResourcePrivate->sthal_SC.Miu0MaskOld;
2830 pXCResourcePrivate->sthal_SC.Miu1Mask = pXCResourcePrivate->sthal_SC.Miu1MaskOld;
2831 pXCResourcePrivate->sthal_SC.Miu2Mask = pXCResourcePrivate->sthal_SC.Miu2MaskOld;
2832
2833 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2834 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2835 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2836 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2837 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2838 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2839 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG6Mask |= MIU_SC_G6REQUEST_MASK;
2840
2841
2842 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2843 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2844 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2845 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2846 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2847 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2848 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG6Mask |= MIU_SC_G6REQUEST_MASK;
2849
2850 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2851 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2852 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2853 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2854 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2855 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2856 pXCResourcePrivate->sthal_SC.Miu2Mask.u16MiuG6Mask |= MIU_SC_G6REQUEST_MASK;
2857
2858 Hal_SC_set_miu0mask(pXCResourcePrivate->sthal_SC.Miu0Mask);
2859 Hal_SC_set_miu1mask(pXCResourcePrivate->sthal_SC.Miu1Mask);
2860 Hal_SC_set_miu2mask(pXCResourcePrivate->sthal_SC.Miu2Mask);
2861 }
2862
Hal_SC_Disable_MiuMask(void * pInstance)2863 void Hal_SC_Disable_MiuMask(void *pInstance)
2864 {
2865 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2866 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2867 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2868 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2869 Hal_SC_set_miu0mask(pXCResourcePrivate->sthal_SC.Miu0MaskOld);
2870 Hal_SC_set_miu1mask(pXCResourcePrivate->sthal_SC.Miu1MaskOld);
2871 Hal_SC_set_miu2mask(pXCResourcePrivate->sthal_SC.Miu2MaskOld);
2872 }
2873
Hal_SC_set_miusel(void * pInstance,MS_U8 u8MIUSel)2874 void Hal_SC_set_miusel(void *pInstance, MS_U8 u8MIUSel)
2875 {
2876 // Scaler control MIU by itself
2877 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2878 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2879 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2880 #if 0 // remove and decided by miu_setting.txt
2881 // MIU 1, GROUP0~5: 0x78~0x7D
2882 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x60, 0x60); // IP select, group1, for [5]DIPW, [6]LD
2883 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select, group1, for [f]MC2D
2884 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFA, 0xE0, 0xE0); // IP select, group5
2885 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFB, 0xF7, 0xF7); // IP select, group5
2886 #endif
2887
2888 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU Select control by xc internal
2889 if (psXCInstPri->u32DeviceID == 0)
2890 {
2891 //IPM_R2 miu select need follow IPM miu select.
2892 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, BIT(0) | BIT(1) | BIT(15), BIT(0) | BIT(1) | BIT(15));
2893 }
2894 else
2895 {
2896 SC_W2BYTEMSK(0, REG_SC_BK7F_11_L, BIT(12) | BIT(14), BIT(12) | BIT(14));
2897 }
2898 if (u8MIUSel==0)
2899 {
2900 ///SCM
2901 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2902 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2903 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2904 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2905 }
2906 else if(u8MIUSel==1)
2907 {
2908 ///SCM
2909 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2910 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2911 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2912 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2913 }
2914 else if(u8MIUSel==2)
2915 {
2916 ///SCM
2917 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2918 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2919 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2920 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2921 }
2922 #else
2923 // When MIU select controlled by miu, miu IPM0 use: BK7F_18[0] BK7F_10[0] Selecet miu chip select
2924 // When MIU select controlled by miu, miu OPM0 use: BK7F_18[1] BK7F_10[1] Selecet miu chip select
2925 // 00'b: MIU0, 01'b: MIU1, 10'b: MIU2
2926 if (psXCInstPri->u32DeviceID == 0)
2927 {
2928 // miu request0 IPM/OPM LSB
2929 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u8MIUSel & BIT(0)) << 15)|((u8MIUSel & BIT(0)) << 1)|(u8MIUSel & BIT(0)), BIT(15)|BIT(1)| BIT(0));
2930 // miu request0 IPM/OPM MSB
2931 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, ((u8MIUSel & BIT(1)) << 14)|(u8MIUSel & BIT(1))|((u8MIUSel & BIT(1)) >> 1), BIT(15)|BIT(1)| BIT(0));
2932 }
2933 else if (psXCInstPri->u32DeviceID == 1)
2934 {
2935 // miu request0 IPM/OPM LSB
2936 SC_W2BYTEMSK(0, REG_SC_BK7F_10_L, ((u8MIUSel & BIT(0)) << 14)|((u8MIUSel & BIT(0)) << 12), BIT(14)| BIT(12));
2937 // miu request0 IPM/OPM MSB
2938 u8MIUSel = (u8MIUSel & BIT(1)) >> 1;
2939 SC_W2BYTEMSK(0, REG_SC_BK7F_18_L, (u8MIUSel << 14) | (u8MIUSel << 12), BIT(14)| BIT(12));
2940 }
2941 #endif
2942 }
2943
Hal_SC_get_miusel(void * pInstance,SC_MIUSEL_t * stMIUSel)2944 void Hal_SC_get_miusel(void *pInstance, SC_MIUSEL_t* stMIUSel)
2945 {
2946 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU Select control by xc internal
2947 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2948 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2949
2950 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, BIT(4)))
2951 {
2952 stMIUSel-> u8MainFBSel = 1;
2953 }
2954 else
2955 {
2956 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, BIT(4)))
2957 {
2958 stMIUSel-> u8MainFBSel = 2;
2959 }
2960 else
2961 {
2962 stMIUSel-> u8MainFBSel = 0;
2963 }
2964 }
2965
2966 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_05_L, BIT(4)))
2967 {
2968 stMIUSel-> u8SubFBSel = 1;
2969 }
2970 else
2971 {
2972 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK31_05_L, BIT(4)))
2973 {
2974 stMIUSel-> u8SubFBSel = 2;
2975 }
2976 else
2977 {
2978 stMIUSel-> u8SubFBSel = 0;
2979 }
2980 }
2981 #else
2982 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2983 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2984 MS_U16 u16MiuSel = 0;
2985 //return OPM MIU select
2986 if (psXCInstPri->u32DeviceID == 0)
2987 {
2988 u16MiuSel = SC_R2BYTEMSK(0, REG_SC_BK7F_10_L, BIT(1)) >> 1;
2989 u16MiuSel |= SC_R2BYTEMSK(0, REG_SC_BK7F_18_L, BIT(1));
2990
2991 stMIUSel-> u8MainFBSel = (MS_U8)(u16MiuSel & 0xff);
2992 }
2993 else if (psXCInstPri->u32DeviceID == 1)
2994 {
2995 u16MiuSel = SC_R2BYTEMSK(0, REG_SC_BK7F_10_L, BIT(12)) >> 1;
2996 u16MiuSel |= SC_R2BYTEMSK(0, REG_SC_BK7F_18_L, BIT(12));
2997
2998 stMIUSel-> u8MainFBSel = (MS_U8)(u16MiuSel & 0xff);
2999 }
3000 #endif
3001 }
3002
Hal_SC_set_dual_miusel(void * pInstance,MS_U8 u8MIUSel)3003 void Hal_SC_set_dual_miusel(void *pInstance, MS_U8 u8MIUSel)
3004 {
3005 // Scaler control MIU by itself
3006 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
3007 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3008 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3009 // Dual just support scaler0, main only
3010 if (psXCInstPri->u32DeviceID > 0)
3011 {
3012 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
3013 return;
3014 }
3015 #if 0 // remove and decided by miu_setting.txt
3016 // MIU 1, GROUP0~5: 0x78~0x7D
3017 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x60, 0x60); // IP select, group1, for [5]DIPW, [6]LD
3018 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select, group1, for [f]MC2D
3019 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFA, 0xE0, 0xE0); // IP select, group5
3020 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFB, 0xF7, 0xF7); // IP select, group5
3021 #endif
3022
3023 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU select ctorled by xc internal
3024 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, BIT(0) | BIT(1), BIT(0) | BIT(1));
3025 if (u8MIUSel==0)
3026 {
3027 ///SCM
3028 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
3029 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
3030 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
3031 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
3032 }
3033 else if(u8MIUSel==1)
3034 {
3035 ///SCM
3036 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
3037 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
3038 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
3039 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
3040 }
3041 else if(u8MIUSel==2)
3042 {
3043 ///SCM
3044 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
3045 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
3046 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
3047 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
3048 }
3049
3050 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, 0x0, BIT(0) | BIT(1));
3051 #else
3052 // When MIU select controlled by miu, IPM1 use: BK7F_19[0..1] Selecet miu chip select
3053 // When MIU select controlled by miu, OPM1 use: BK7F_19[2..3] Selecet miu chip select
3054 // 00'b: MIU0, 01'b: MIU1, 10'b: MIU2
3055
3056 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u8MIUSel << 2) | u8MIUSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
3057 #endif
3058 }
3059
Hal_SC_set_dual_disable(void * pInstance)3060 void Hal_SC_set_dual_disable(void *pInstance)
3061 {
3062 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3063 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3064 // Dual just support scaler0, main only
3065 if (psXCInstPri->u32DeviceID > 0)
3066 {
3067 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
3068 return;
3069 }
3070
3071 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, 0, BIT(15)); // reg_miu_select_f1 to MIU1
3072 }
3073
Hal_SC_get_dual_miusel(void * pInstance,SC_MIUSEL_t * stMIUSel)3074 void Hal_SC_get_dual_miusel(void *pInstance, SC_MIUSEL_t* stMIUSel)
3075 {
3076 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3077 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3078 // Dual just support scaler0, main only
3079 if (psXCInstPri->u32DeviceID > 0)
3080 {
3081 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] scmi dual mode just support scaler0 main only.\n",__func__,__LINE__);
3082 return;
3083 }
3084 #if (MIU_SEL_USE_XC_INTERNAL == TRUE) // MIU Select control by xc internal
3085 if(SC_R2BYTEMSK(0, REG_SC_BK52_05_L, BIT(4)))
3086 {
3087 stMIUSel->u8MainFBSel = 1;
3088 }
3089 else
3090 {
3091 if(SC_R2BYTEMSK(0, REG_SC_BK51_05_L, BIT(4)))
3092 {
3093 stMIUSel->u8MainFBSel = 2;
3094 }
3095 else
3096 {
3097 stMIUSel->u8MainFBSel = 0;
3098 }
3099 }
3100
3101 if(SC_R2BYTEMSK(0, REG_SC_BK52_44_L, BIT(4)))
3102 {
3103 stMIUSel->u8SubFBSel = 1;
3104 }
3105 else
3106 {
3107 if(SC_R2BYTEMSK(0, REG_SC_BK51_44_L, BIT(4)))
3108 {
3109 stMIUSel->u8SubFBSel = 2;
3110 }
3111 else
3112 {
3113 stMIUSel->u8SubFBSel = 0;
3114 }
3115 }
3116 #else // MIU Select control by miu
3117 MS_U16 u16Tmp = SC_R2BYTEMSK(0, REG_SC_BK7F_19_L, BIT(0)|BIT(1));
3118 stMIUSel->u8MainFBSel = (MS_U8)(u16Tmp & 0xff);
3119 #endif
3120 }
3121
Hal_SC_set_blsk(void * pInstance,MS_BOOL bEn)3122 void Hal_SC_set_blsk(void *pInstance, MS_BOOL bEn)
3123 {
3124 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3125 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3126 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_21_L, bEn ? BIT(12) : 0, BIT(12));
3127 }
3128
Hal_SC_set_blsk_burst(void * pInstance,MS_BOOL bEn)3129 void Hal_SC_set_blsk_burst(void *pInstance, MS_BOOL bEn)
3130 {
3131 _MLOAD_ENTRY(pInstance);
3132 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_21_L, bEn ? BIT(12) : 0, BIT(12));
3133 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3134 _MLOAD_RETURN(pInstance);
3135 }
3136
Hal_SC_set_main_black_screen_burst(void * pInstance,MS_BOOL bEn)3137 void Hal_SC_set_main_black_screen_burst(void *pInstance, MS_BOOL bEn)
3138 {
3139 _MLOAD_ENTRY(pInstance);
3140
3141 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? BIT(1) : 0, BIT(1));
3142 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3143
3144 _MLOAD_RETURN(pInstance);
3145 }
3146
Hal_SC_set_main_sub_black_screen_burst(void * pInstance,MS_BOOL bEn)3147 void Hal_SC_set_main_sub_black_screen_burst(void *pInstance, MS_BOOL bEn)
3148 {
3149 _MLOAD_ENTRY(pInstance);
3150
3151 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? (BIT(5)|BIT(1)) : 0, (BIT(6)|BIT(5)|BIT(1)));
3152 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3153
3154 _MLOAD_RETURN(pInstance);
3155 }
3156
Hal_SC_set_main_black_screen(void * pInstance,MS_BOOL bEn)3157 void Hal_SC_set_main_black_screen(void *pInstance, MS_BOOL bEn)
3158 {
3159 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3160 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3161 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? BIT(1) : 0, BIT(1));
3162 }
3163
Hal_SC_set_main_sub_black_screen(void * pInstance,MS_BOOL bEn)3164 void Hal_SC_set_main_sub_black_screen(void *pInstance, MS_BOOL bEn)
3165 {
3166 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3167 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3168 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? (BIT(5)|BIT(1)) : 0, (BIT(6)|BIT(5)|BIT(1)));
3169 }
3170
Hal_SC_set_sub_blue_screen_burst(void * pInstance,MS_BOOL bEn,MS_BOOL bBlue)3171 void Hal_SC_set_sub_blue_screen_burst(void *pInstance, MS_BOOL bEn, MS_BOOL bBlue)
3172 {
3173 _MLOAD_ENTRY(pInstance);
3174
3175 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bBlue ? BIT(6) : 0, BIT(6));
3176 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? BIT(5) : 0, BIT(5));
3177 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3178
3179 _MLOAD_RETURN(pInstance);
3180 }
3181
Hal_SC_set_sub_blue_screen(void * pInstance,MS_BOOL bEn,MS_BOOL bBlue)3182 void Hal_SC_set_sub_blue_screen(void *pInstance, MS_BOOL bEn, MS_BOOL bBlue)
3183 {
3184 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3185 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3186 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bBlue ? BIT(6) : 0, BIT(6));
3187 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? BIT(5) : 0, BIT(5));
3188 }
3189
Hal_SC_IP_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3190 E_APIXC_ReturnValue Hal_SC_IP_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3191 {
3192 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3193 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3194 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3195 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3196 if(MAIN_WINDOW == eWindow)
3197 {
3198 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, bEnable? 0 : BIT(0) , BIT(0));
3199 }
3200 else
3201 {
3202 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, bEnable? 0 : BIT(0) , BIT(0));
3203 }
3204
3205 return E_APIXC_RET_OK;
3206 }
3207
Hal_SC_IP_Memory_Read_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3208 E_APIXC_ReturnValue Hal_SC_IP_Memory_Read_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3209 {
3210 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3211 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3212 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3213 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3214 if(MAIN_WINDOW == eWindow)
3215 {
3216 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_02_L, bEnable? 0 : BIT(14) , BIT(14));
3217 }
3218 else
3219 {
3220 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_42_L, bEnable? 0 : BIT(14) , BIT(14));
3221 }
3222 return E_APIXC_RET_OK;
3223 }
3224
Hal_SC_OP_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3225 E_APIXC_ReturnValue Hal_SC_OP_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3226 {
3227 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3228 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3229 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will stop OPW and OP memory write request
3230 return E_APIXC_RET_OK;
3231 }
3232
Hal_SC_frcmw_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3233 E_APIXC_ReturnValue Hal_SC_frcmw_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3234 {
3235 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3236 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3237 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3238 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3239 if(MAIN_WINDOW == eWindow)
3240 {
3241 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_07_L, bEnable? 0 : BIT(0) , BIT(0));
3242 }
3243 else
3244 {
3245 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_47_L, bEnable? 0 : BIT(0) , BIT(0));
3246 }
3247 return E_APIXC_RET_OK;
3248 }
3249
Hal_SC_frcmr_Memory_Read_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3250 E_APIXC_ReturnValue Hal_SC_frcmr_Memory_Read_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3251 {
3252 return E_APIXC_RET_OK;
3253 }
3254
Hal_SC_disable_inputsource_burst(void * pInstance,MS_BOOL bDisable,SCALER_WIN eWindow)3255 void Hal_SC_disable_inputsource_burst(void *pInstance, MS_BOOL bDisable, SCALER_WIN eWindow)
3256 {
3257 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3258 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3259 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3260 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3261
3262 _MLOAD_ENTRY(pInstance);
3263
3264 // HW PIP architeucture
3265 // Becasue BK3_02[8] and BK20_11[15] can not be enabled toghter,
3266 // otherwise garbage will be showed,we need to use BK12_47[0] to instead.
3267 if( eWindow == MAIN_WINDOW )
3268 {
3269 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_02_L, (bDisable ? BIT(7):0), BIT(7));
3270 }
3271 else
3272 {
3273 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, (bDisable ? BIT(7):0), BIT(7));
3274 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_47_L, (bDisable ? BIT(0) : 0), BIT(0));
3275 #if (HW_DESIGN_4K2K_VER == 4)
3276 if ((psXCInstPri->u32DeviceID==0)
3277 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
3278 {
3279 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_47_L, (bDisable ? BIT(0) : 0), BIT(0));
3280 }
3281 #endif
3282 }
3283 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3284 _MLOAD_RETURN(pInstance);
3285 }
3286
Hal_SC_disable_inputsource(void * pInstance,MS_BOOL bDisable,SCALER_WIN eWindow)3287 void Hal_SC_disable_inputsource(void *pInstance, MS_BOOL bDisable, SCALER_WIN eWindow)
3288 {
3289 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3290 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3291 if( eWindow == MAIN_WINDOW )
3292 {
3293 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L, (bDisable ? BIT(7):0), BIT(7));
3294 }
3295 else
3296 {
3297 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L, (bDisable ? BIT(7):0), BIT(7));
3298 }
3299 }
3300
3301
Hal_SC_Is_InputSource_Disable(void * pInstance,SCALER_WIN eWindow)3302 MS_U16 Hal_SC_Is_InputSource_Disable(void *pInstance, SCALER_WIN eWindow)
3303 {
3304 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3305 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3306 if(eWindow == MAIN_WINDOW)
3307 return (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L)&0x80);
3308 else
3309 {
3310 if((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L)&0x01) == 0)
3311 {
3312 return (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L)&0x80);
3313 }
3314 else
3315 {
3316 return TRUE;
3317 }
3318 }
3319 }
3320
3321
Hal_SC_set_nosignal_color(void * pInstance,MS_U8 u8Color,SCALER_WIN eWindow)3322 void Hal_SC_set_nosignal_color(void *pInstance, MS_U8 u8Color,SCALER_WIN eWindow)
3323 {
3324 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3325 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3326 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
3327 {
3328 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
3329 _MLOAD_ENTRY(pInstance);
3330 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3331 if(psXCInstPri->u32DeviceID == 0)
3332 #else
3333 if ( eWindow == MAIN_WINDOW )
3334 #endif
3335 {
3336 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_24_L, u8Color, LBMASK);
3337 }
3338 else
3339 {
3340 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3341 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3342 #else
3343 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3344 #endif
3345 }
3346 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3347 _MLOAD_RETURN(pInstance);
3348 }
3349 else
3350 {
3351 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3352 if(psXCInstPri->u32DeviceID == 0)
3353 #else
3354 if ( eWindow == MAIN_WINDOW )
3355 #endif
3356 {
3357 #ifdef new_chakra
3358 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_24_L, u8Color, LBMASK);
3359 #else
3360 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_24_L, u8Color, LBMASK);
3361 #endif
3362 }
3363 else
3364 {
3365 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3366 SC_W2BYTEMSK(0, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3367 #else
3368 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
3369 #endif
3370 }
3371 }
3372 }
3373
Hal_SC_set_fbl(void * pInstance,MS_BOOL bEn)3374 void Hal_SC_set_fbl(void *pInstance, MS_BOOL bEn)
3375 {
3376 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3377 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3378 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn ? BIT(7): 0), BIT(7)); //Enable/Disable FBL
3379 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_02_L, (bEn ? BIT(14):0), BIT(14)); //F2 force IP read request disable
3380
3381 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (bEn ? 0x3:0), 0x3); //F2 IP read/write request disable
3382 }
3383
Hal_SC_get_fbl(void * pInstance)3384 MS_BOOL Hal_SC_get_fbl(void *pInstance)
3385 {
3386 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3387 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3388 return SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, BIT(7)); //Enable/Disable FBL
3389 }
3390
Hal_SC_set_freezeimg_burst(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3391 void Hal_SC_set_freezeimg_burst(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3392 {
3393 _MLOAD_ENTRY(pInstance);
3394 #if (HW_DESIGN_4K2K_VER == 4)
3395 if( eWindow == MAIN_WINDOW )
3396 {
3397 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3398 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3399 }
3400 else
3401 {
3402 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3403 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3404 }
3405 #else
3406 if( eWindow == MAIN_WINDOW )
3407 {
3408 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3409 }
3410 else
3411 {
3412 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3413 }
3414 #endif
3415 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3416 _MLOAD_RETURN(pInstance);
3417 }
3418
3419
Hal_SC_set_freezeimg(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3420 void Hal_SC_set_freezeimg(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3421 {
3422 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3423 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3424 #if (HW_DESIGN_4K2K_VER == 4)
3425 if( eWindow == MAIN_WINDOW )
3426 {
3427 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3428 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3429 }
3430 else
3431 {
3432 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3433 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3434 }
3435 #else
3436 if( eWindow == MAIN_WINDOW )
3437 {
3438 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3439 }
3440 else
3441 {
3442 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3443 }
3444 #endif
3445 }
3446
Hal_SC_set_frcm_freezeimg(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3447 void Hal_SC_set_frcm_freezeimg(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3448 {
3449 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3450 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3451 if( eWindow == MAIN_WINDOW )
3452 {
3453 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3454 }
3455 else
3456 {
3457 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3458 }
3459 }
3460
Hal_SC_get_freezeimg(void * pInstance,SCALER_WIN eWindow)3461 MS_BOOL Hal_SC_get_freezeimg(void *pInstance, SCALER_WIN eWindow)
3462 {
3463 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3464 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3465 #if (HW_DESIGN_4K2K_VER == 4)
3466 if( eWindow == MAIN_WINDOW )
3467 {
3468 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, BIT(11)) ? TRUE: FALSE);
3469 }
3470 else
3471 {
3472 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, BIT(11)) ? TRUE: FALSE);
3473 }
3474 #else
3475 if( eWindow == MAIN_WINDOW )
3476 {
3477 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, BIT(11)) ? TRUE: FALSE);
3478 }
3479 else
3480 {
3481 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, BIT(11)) ? TRUE: FALSE);
3482 }
3483 #endif
3484 }
3485
Hal_SC_exwith_miuprotect_swreset(void * pInstance,MS_U8 x)3486 void Hal_SC_exwith_miuprotect_swreset(void *pInstance, MS_U8 x)
3487 {
3488 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3489 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3490 //reset IP1F2
3491 //select pattern generator source
3492 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_02_L, x, x);
3493 //MsOS_DelayTask(2);
3494
3495 //select pattern generator source
3496 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_02_L, 0, x);
3497 //MsOS_DelayTask(2);
3498 }
3499
Hal_SC_ip_Init_for_internal_timing(void * pInstance,XC_Internal_TimingType timingtype,SCALER_WIN eWindow)3500 void Hal_SC_ip_Init_for_internal_timing(void *pInstance, XC_Internal_TimingType timingtype, SCALER_WIN eWindow)
3501 {
3502 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3503 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3504 if(eWindow == SUB_WINDOW)
3505 {
3506 if(Hal_SC_ip_get_IPAutoNoSignal(pInstance, eWindow)) Hal_SC_ip_set_IPAutoNoSignal(pInstance, DISABLE, eWindow);
3507
3508 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L, 0x104) ; //Video source
3509 Hal_SC_exwith_miuprotect_swreset(pInstance, REST_IP_F1); //when source is changed, we must reset it to make it work
3510 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, 0x890);
3511
3512 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_21_L, 0x01, 0x03); //force progressive mode
3513 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0E_L, BIT(15), BIT(15)); //auto gain 10bit
3514
3515 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_04_L, 0x020); //capture V start
3516 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_05_L, 0x50) ; //capture H start
3517
3518 switch (timingtype)
3519 {
3520 case E_XC_480P:
3521 default:
3522
3523 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x1c0) ; // V size
3524 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x280) ; // h size
3525
3526 break;
3527 case E_XC_720P:
3528 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x290) ; // V size (720 - 64) = 656 = 0x290
3529 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x460) ; // h size (1280 - 160) = 1120 = 0x460
3530
3531 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, 0x0800); //DNR Offset
3532 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, 0x0460); //DNR Fetch
3533 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, 0x0800); //OPM Offsest
3534 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, 0x0460); //OPM Fetch
3535
3536 break;
3537 case E_XC_1080P:
3538 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x3F8) ; // V size (1080 - 64) = 1016 = 0x3F8
3539 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x6E0) ; // h size (1920 - 160) = 1760 = 0x6E0
3540
3541 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, 0x0800); //DNR Offset
3542 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, 0x06E0); //DNR Fetch
3543 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, 0x0800); //OPM Offsest
3544 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, 0x06E0); //OPM Fetch
3545 break;
3546 }
3547 }
3548 else
3549 {
3550 if(Hal_SC_ip_get_IPAutoNoSignal(pInstance, eWindow)) Hal_SC_ip_set_IPAutoNoSignal(pInstance, DISABLE, eWindow);
3551
3552 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L, 0x104) ; //Video source
3553 Hal_SC_exwith_miuprotect_swreset(pInstance, REST_IP_F2); //when source is changed, we must reset it to make it work
3554 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0x890);
3555
3556 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, 0x01, 0x03); //force progressive mode
3557 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0E_L, BIT(15), BIT(15)); //auto gain 10bit
3558
3559 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_04_L, 0x020); //capture V start
3560 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_05_L, 0x50) ; //capture H start
3561
3562 switch (timingtype)
3563 {
3564 case E_XC_480P:
3565 default:
3566
3567 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x1c0) ; // V size
3568 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x280) ; // h size
3569
3570 break;
3571 case E_XC_720P:
3572 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x290) ; // V size (720 - 64) = 656 = 0x290
3573 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x460) ; // h size (1280 - 160) = 1120 = 0x460
3574
3575 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, 0x0800); //DNR Offset
3576 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, 0x0460); //DNR Fetch
3577 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, 0x0800); //OPM Offsest
3578 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, 0x0460); //OPM Fetch
3579
3580 break;
3581 case E_XC_1080P:
3582 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x3F8) ; // V size (1080 - 64) = 1016 = 0x3F8
3583 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x6E0) ; // h size (1920 - 160) = 1760 = 0x6E0
3584
3585 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, 0x0800); //DNR Offset
3586 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, 0x06E0); //DNR Fetch
3587 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, 0x0800); //OPM Offsest
3588 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, 0x06E0); //OPM Fetch
3589 break;
3590 }
3591
3592 }
3593 }
3594
Hal_SC_rgb_average_info(void * pInstance,MS_U16 u16mask,SCALER_WIN eWindow)3595 MS_U16 Hal_SC_rgb_average_info(void *pInstance, MS_U16 u16mask, SCALER_WIN eWindow)
3596 {
3597 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3598 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3599 MS_U16 u16value;
3600
3601 if(eWindow == MAIN_WINDOW)
3602 {
3603 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, u16mask, 0x0F);
3604 u16value=SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_11_L);
3605 }
3606 else
3607 {
3608 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0F_L, u16mask, 0x0F);
3609 u16value=SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_11_L);
3610 }
3611
3612 return u16value;
3613 }
3614
3615
Hal_SC_autogain_enable(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3616 void Hal_SC_autogain_enable(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3617 {
3618 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3619 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3620 //auto gain enable
3621 if(eWindow == MAIN_WINDOW)
3622 {
3623 if(bEnable)
3624 W2BYTEMSK(REG_SC_BK01_0E_L, 0x11, 0x11);
3625 else
3626 W2BYTEMSK(REG_SC_BK01_0E_L, 0x00, 0x11);
3627 }
3628 else
3629 {
3630 if(bEnable)
3631 W2BYTEMSK(REG_SC_BK03_0E_L, 0x11, 0x11);
3632 else
3633 W2BYTEMSK(REG_SC_BK03_0E_L, 0x00, 0x11);
3634 }
3635 }
3636
Hal_SC_autogain_status(void * pInstance,SCALER_WIN eWindow)3637 MS_BOOL Hal_SC_autogain_status(void *pInstance, SCALER_WIN eWindow)
3638 {
3639 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3640 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3641 MS_BOOL bvalue;
3642 if(eWindow == MAIN_WINDOW)
3643 bvalue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0E_L, BIT(1));
3644 else
3645 bvalue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0E_L, BIT(1));
3646
3647 return bvalue;
3648
3649 }
3650
Hal_SC_set_mirror(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3651 void Hal_SC_set_mirror(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3652 {
3653 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3654 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3655 MS_U32 u32NoSigReg, u32MirrorReg;
3656
3657 if(eWindow == MAIN_WINDOW)
3658 {
3659 u32NoSigReg = REG_SC_BK01_02_L;
3660 u32MirrorReg = REG_SC_BK12_03_L;
3661 }
3662 else
3663 {
3664 u32NoSigReg = REG_SC_BK03_02_L;
3665 u32MirrorReg = REG_SC_BK12_43_L;
3666
3667 }
3668
3669 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32NoSigReg, BIT(7), BIT(7));
3670
3671 if( bEnable )
3672 {
3673 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, (BIT(12)|BIT(13)), (BIT(12)|BIT(13)));
3674 }
3675 else
3676 {
3677 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, 0x0, (BIT(12)|BIT(13)));
3678 }
3679 }
3680
Hal_SC_set_frcm_mirror(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3681 void Hal_SC_set_frcm_mirror(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3682 {
3683 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3684 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3685 MS_U32 u32NoSigReg = 0, u32MirrorReg = 0;
3686
3687 if(eWindow == MAIN_WINDOW)
3688 {
3689 u32NoSigReg = REG_SC_BK01_02_L;
3690 u32MirrorReg = REG_SC_BK32_03_L;
3691 }
3692 else
3693 {
3694 u32NoSigReg = REG_SC_BK03_02_L;
3695 u32MirrorReg = REG_SC_BK32_43_L;
3696 }
3697
3698 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32NoSigReg, BIT(7), BIT(7));
3699
3700 if( bEnable )
3701 {
3702 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, (BIT(12)|BIT(13)), (BIT(12)|BIT(13)));
3703 }
3704 else
3705 {
3706 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, 0x0, (BIT(12)|BIT(13)));
3707 }
3708 }
3709
Hal_SC_GetAVDStatus(void)3710 MS_U16 Hal_SC_GetAVDStatus(void)
3711 {
3712 return MDrv_Read2Byte(L_BK_AFEC(0x66));
3713 }
3714
Hal_SC_set_rep_window(void * pInstance,MS_BOOL bEnable,MS_U16 x,MS_U16 y,MS_U16 w,MS_U16 h,MS_U8 u8Color)3715 void Hal_SC_set_rep_window(void *pInstance, MS_BOOL bEnable,MS_U16 x,MS_U16 y,MS_U16 w,MS_U16 h,MS_U8 u8Color)
3716 {
3717 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3718 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3719 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, bEnable?BIT(9):0x0, BIT(9));
3720 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L,x);
3721 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L,x + w);
3722 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L,y);
3723 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L,y + h);
3724 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, (~u8Color)<<8, 0xFF00);
3725 }
3726
3727 //--------------------------------------------------
3728 //update display window registers with input window
3729 //IN:
3730 // pdspwin: input window info
3731 //--------------------------------------------------
Hal_SC_set_disp_window(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)3732 void Hal_SC_set_disp_window(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
3733 {
3734 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3735 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3736 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3737 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3738 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
3739 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
3740 {
3741 _MLOAD_ENTRY(pInstance);
3742
3743 if(eWindow == MAIN_WINDOW)
3744 {
3745 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3746 if (psXCInstPri->u32DeviceID == 1)
3747 {
3748 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
3749 //Display window
3750 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, u16HDEStart+90, VOP_DISPLAY_HSTART_MASK);//temp solution(+90)
3751 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (u16HDEStart+pdspwin->x+pdspwin->width-1 - pdspwin->x+90), VOP_DISPLAY_HEND_MASK);
3752 }
3753 else
3754 {
3755 //Display window
3756 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pdspwin->x>>00), VOP_DISPLAY_HSTART_MASK);
3757 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)((pdspwin->x+pdspwin->width-1)>>00), VOP_DISPLAY_HEND_MASK);
3758 }
3759 if(Hal_SC_3D_IsDualViewMode(pInstance,MAIN_WINDOW) && (E_XC_3D_OUTPUT_TOP_BOTTOM == MDrv_XC_Get_3D_Output_Mode(pInstance)))
3760 {
3761 if (IsVMirrorMode(eWindow))
3762 {
3763 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pdspwin->y+(pdspwin->height)/2), VOP_DISPLAY_VSTART_MASK);
3764 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pdspwin->y+(pdspwin->height)-1), VOP_DISPLAY_VEND_MASK);
3765 }
3766 else
3767 {
3768 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pdspwin->y), VOP_DISPLAY_VSTART_MASK);
3769 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pdspwin->y+(pdspwin->height)/2-1), VOP_DISPLAY_VEND_MASK);
3770 }
3771 }
3772 else
3773 {
3774 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pdspwin->y), VOP_DISPLAY_VSTART_MASK);
3775 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pdspwin->y+pdspwin->height-1), VOP_DISPLAY_VEND_MASK);
3776 }
3777
3778 if (psXCInstPri->u32DeviceID == 1)//follow HW_DESIGN_4K2K_VER = 6 rule
3779 {
3780 //Display window
3781 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_07_L, (MS_U16)(pdspwin->x>>00), VOP_DISPLAY_HSTART_MASK);
3782 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_08_L, (MS_U16)((pdspwin->x+pdspwin->width-1)>>00), VOP_DISPLAY_HEND_MASK);
3783 if(Hal_SC_3D_IsDualViewMode(pInstance,MAIN_WINDOW) && (E_XC_3D_OUTPUT_TOP_BOTTOM == MDrv_XC_Get_3D_Output_Mode(pInstance)))
3784 {
3785 if (IsVMirrorMode(eWindow))
3786 {
3787 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_09_L, (MS_U16)(pdspwin->y), 0xFFFF);
3788 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_0A_L, (MS_U16)(pdspwin->y+pdspwin->height/2-1), 0xFFFF);
3789 }
3790 else
3791 {
3792 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_09_L, (MS_U16)(pdspwin->y+(pdspwin->height)/2), 0xFFFF);
3793 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_0A_L, (MS_U16)(pdspwin->y+pdspwin->height-1), 0xFFFF);
3794 }
3795 }
3796 else
3797 {
3798 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_09_L, (MS_U16)(pdspwin->y), 0xFFFF);
3799 MDrv_XC_MLoad_WriteCmd(g_pDevice0Instance, REG_SC_BK0F_0A_L, (MS_U16)(pdspwin->y+pdspwin->height-1), 0xFFFF);
3800 }
3801 }
3802 #else
3803 //Display window
3804 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, pdspwin->x,VOP_DISPLAY_HSTART_MASK); // Display H start
3805 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1,VOP_DISPLAY_HEND_MASK); // Display H end
3806 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, pdspwin->y,VOP_DISPLAY_VSTART_MASK); // Display V start
3807 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1,VOP_DISPLAY_VEND_MASK); // Display V end
3808 #endif
3809 }
3810 else
3811 {
3812 //Display window
3813 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, pdspwin->x,0x3FFF); // Display H start
3814 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1,0x3FFF); // Display H end
3815 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, pdspwin->y,0x1FFF); // Display V start
3816 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1,0x1FFF); // Display V end
3817 }
3818
3819 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3820 _MLOAD_RETURN(pInstance);
3821 }
3822 else
3823 {
3824 if(eWindow == MAIN_WINDOW)
3825 {
3826 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3827 //FIX ME:following HW_DESIGN_4K2K_VER = 6 rule
3828 //Display window
3829 if (psXCInstPri->u32DeviceID == 1)
3830 {
3831 MS_U16 u16HDEStart = SC_R2BYTE(0, REG_SC_BK10_04_L);
3832 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, u16HDEStart+90);//temp solution(+90)
3833 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, (u16HDEStart+ pdspwin->width+90-1));
3834 }
3835 else
3836 {
3837 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pdspwin->x);
3838 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1);
3839 }
3840 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pdspwin->y);
3841 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1);
3842 if (psXCInstPri->u32DeviceID == 1)//follow HW_DESIGN_4K2K_VER = 6 rule
3843 {
3844 //Display window
3845 SC_W2BYTE(0, REG_SC_BK0F_07_L, pdspwin->x); // Display H start
3846 SC_W2BYTE(0, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1); // Display H end
3847 SC_W2BYTE(0, REG_SC_BK0F_09_L, pdspwin->y); // Display V start
3848 SC_W2BYTE(0, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1); // Display V end
3849 }
3850 #else
3851 //Display window
3852 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pdspwin->x); // Display H start
3853 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1); // Display H end
3854 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pdspwin->y); // Display V start
3855 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1); // Display V end
3856 #endif
3857 }
3858 else
3859 {
3860 //Display window
3861 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pdspwin->x); // Display H start
3862 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1); // Display H end
3863 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pdspwin->y); // Display V start
3864 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1); // Display V end
3865 }
3866 }
3867 }
3868
3869 //--------------------------------------------------
3870 //get display window registers setting
3871 //OUT:
3872 // pdspwin: Pointer for ouput disp window register
3873 //--------------------------------------------------
Hal_SC_get_disp_window(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)3874 void Hal_SC_get_disp_window(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
3875 {
3876 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3877 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3878 if(eWindow == MAIN_WINDOW)
3879 {
3880 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
3881 //Display window
3882 pdspwin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L); // Display H start
3883 pdspwin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L) - pdspwin->x + 1; // Display H end
3884 pdspwin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L); // Display V start
3885 pdspwin->height = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L) - pdspwin->y + 1; // Display V end
3886 }
3887 else
3888 {
3889 //Display window
3890 pdspwin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L); // Display H start
3891 pdspwin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L) - pdspwin->x + 1; // Display H end
3892 pdspwin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L); // Display V start
3893 pdspwin->height = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L) - pdspwin->y + 1; // Display V end
3894 }
3895 }
3896
Hal_SC_set_Fclk(void * pInstance,EN_SET_FCLK_CASE enCase)3897 void Hal_SC_set_Fclk(void *pInstance, EN_SET_FCLK_CASE enCase)
3898 {
3899 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3900 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3901 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3902 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3903
3904 if (enCase == EN_FCLK_FBL)
3905 {
3906 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
3907 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK);
3908 else
3909 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK);
3910 }
3911 else
3912 {
3913 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
3914 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_DEFAULT, CKG_FCLK_MASK);
3915 else
3916 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK);
3917 }
3918 }
3919
Hal_SC_get_framebuf_Info(void * pInstance,SC_FRAMEBUF_INFO_t * pFrameBufInfo,SCALER_WIN eWindow)3920 void Hal_SC_get_framebuf_Info(void *pInstance, SC_FRAMEBUF_INFO_t *pFrameBufInfo, SCALER_WIN eWindow)
3921 {
3922 MS_U8 u8Reg;
3923
3924 if (!pFrameBufInfo) return;
3925
3926 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3927 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3928 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3929 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3930
3931 pFrameBufInfo->u32IPMBase0 = (((MS_PHY)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_09_L:REG_SC_BK12_49_L, 0x00FF)<<16) |
3932 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_08_L:REG_SC_BK12_48_L))) * BYTE_PER_WORD;
3933 pFrameBufInfo->u32IPMBase1 = (((MS_PHY)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0B_L:REG_SC_BK12_4B_L, 0x00FF)<<16) |
3934 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0A_L:REG_SC_BK12_4A_L))) * BYTE_PER_WORD;
3935 pFrameBufInfo->u32IPMBase2 = (((MS_PHY)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0D_L:REG_SC_BK12_4D_L, 0x00FF)<<16) |
3936 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0C_L:REG_SC_BK12_4C_L))) * BYTE_PER_WORD;
3937 pFrameBufInfo->u16IPMOffset = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0E_L:REG_SC_BK12_4E_L);
3938 pFrameBufInfo->u16IPMFetch = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0F_L:REG_SC_BK12_4F_L);
3939 pFrameBufInfo->u16VLength = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_18_L:REG_SC_BK12_58_L, 0x0FFF);
3940 pFrameBufInfo->bLinearAddrMode = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_03_L:REG_SC_BK12_43_L, BIT(4));
3941 pFrameBufInfo->bYCSeparate = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L, BIT(10)) )?TRUE:FALSE;
3942 pFrameBufInfo->u32WriteLimitBase = SC_R4BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK0D_42_L:REG_SC_BK0D_44_L);
3943 // frcm write base address limit
3944 #if 0
3945 #if (HW_DESIGN_4K2K_VER == 4)
3946 if ((psXCInstPri->u32DeviceID==0)
3947 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
3948 {
3949 pFrameBufInfo->u32FRCMWriteLimitBase = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L);
3950 }
3951 #endif
3952 #endif
3953 pFrameBufInfo->u8BitPerPixel = 24;//default
3954
3955 u8Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_01_L:REG_SC_BK12_41_L, 0x00FF);
3956 if (u8Reg & 0x30)
3957 {//444
3958 pFrameBufInfo->bMemFormat422 = FALSE;
3959 if (u8Reg & 0x10)
3960 { // 444 8BIT
3961 pFrameBufInfo->u8BitPerPixel = 24;
3962 }
3963 else
3964 { // 444 10BIT
3965 pFrameBufInfo->u8BitPerPixel = 32;
3966 }
3967 pFrameBufInfo->bInterlace = FALSE;
3968 }
3969 else
3970 {//422
3971 pFrameBufInfo->bMemFormat422 = TRUE;
3972
3973 if((BIT(8)|BIT(9)) == SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L, BIT(8)|BIT(9))) //user mode
3974 {
3975 MS_U8 u8MemFmt = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L) & 0x0F;
3976 if((4 == u8MemFmt) || (5 == u8MemFmt) || (6 == u8MemFmt))
3977 {
3978 pFrameBufInfo->u8BitPerPixel = 20;
3979 }
3980 else if((8 == u8MemFmt) || (9 == u8MemFmt) || (10 == u8MemFmt) || (11 == u8MemFmt))
3981 {
3982 pFrameBufInfo->u8BitPerPixel = 24;
3983 }
3984 }
3985 else
3986 {
3987 u8Reg = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_01_L:REG_SC_BK12_41_L, 0xFF00)) >> 8;
3988
3989 switch(u8Reg & 0x77)
3990 {
3991 case 0x25:
3992 pFrameBufInfo->u8BitPerPixel = 24;
3993 pFrameBufInfo->bInterlace = TRUE;
3994 break;
3995 case 0x24:
3996 pFrameBufInfo->u8BitPerPixel = 20;
3997 pFrameBufInfo->bInterlace = TRUE;
3998 break;
3999 case 0x27:
4000 pFrameBufInfo->u8BitPerPixel = 16;
4001 pFrameBufInfo->bInterlace = TRUE;
4002 break;
4003 case 0x21:
4004 if(BIT(1) == SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_04_L:REG_SC_BK12_44_L, BIT(0)|BIT(1)))
4005 {
4006 pFrameBufInfo->u8BitPerPixel = 24;
4007 }
4008 else
4009 {
4010 pFrameBufInfo->u8BitPerPixel = 20;
4011 }
4012 pFrameBufInfo->bInterlace = FALSE;
4013 break;
4014 case 0x20:
4015 pFrameBufInfo->u8BitPerPixel = 16;
4016 pFrameBufInfo->bInterlace = FALSE;
4017 break;
4018 case 0x00:
4019 default:
4020 pFrameBufInfo->u8BitPerPixel = 16;
4021 pFrameBufInfo->bInterlace = FALSE;
4022 break;
4023 }
4024 }
4025 }
4026
4027 //In M10/J2/A5/A6/A3, New SCMI
4028 pFrameBufInfo->u8FBNum = (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_19_L:REG_SC_BK12_59_L, 0x1F));
4029
4030 #if 0
4031 printf("base0=0x%x, base1=0x%x, base2=0x%x, offset=%u, 422=%u, i=%u, bpp=%u, fbnum=%u\n",
4032 (unsigned int)pFrameBufInfo->u32IPMBase0,
4033 (unsigned int)pFrameBufInfo->u32IPMBase1,
4034 (unsigned int)pFrameBufInfo->u32IPMBase2,
4035 pFrameBufInfo->u16IPMOffset,
4036 pFrameBufInfo->bMemFormat422,
4037 pFrameBufInfo->bInterlace,
4038 pFrameBufInfo->u8BitPerPixel,
4039 pFrameBufInfo->u8FBNum);
4040 #endif
4041 }
Hal_SC_set_framebuf_Info(void * pInstance,SC_FRAMEBUF_INFO_t pFrameBufInfo)4042 void Hal_SC_set_framebuf_Info(void *pInstance, SC_FRAMEBUF_INFO_t pFrameBufInfo)
4043 {
4044 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4045 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4046 MS_PHY u32IPMBase0, u32IPMBase1, u32IPMBase2;
4047 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4048 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4049
4050 u32IPMBase0=pFrameBufInfo.u32IPMBase0/BYTE_PER_WORD;
4051 u32IPMBase1=pFrameBufInfo.u32IPMBase1/BYTE_PER_WORD;
4052 u32IPMBase2=pFrameBufInfo.u32IPMBase2/BYTE_PER_WORD;
4053
4054 //Step 5.4, Memory Limit V : BK12_18[15] = 1, BK12_18[12:0] to the real V line number
4055 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, (pFrameBufInfo.u16VLength|0x8000),0x8FFF);
4056
4057 // u32WritelimitBase = ((u32IPMBase0 + u32MemSize) / BYTE_PER_WORD - 1) | 0x2000000;
4058 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pFrameBufInfo.u32IPMBase1);
4059 // frcm write base address limit
4060 #if 0
4061 #if (HW_DESIGN_4K2K_VER == 4)
4062 if ((psXCInstPri->u32DeviceID==0)
4063 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
4064 {
4065 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L, pFrameBufInfo.u32FRCMWriteLimitBase);
4066 }
4067 #endif
4068 #endif
4069 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_09_L, (MS_U16)(u32IPMBase0 & 0xFF0000)>>16,0x00FF);
4070 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, (MS_U16)(u32IPMBase0 & 0xFFFF));
4071
4072 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_0B_L, (MS_U16)(u32IPMBase1 & 0xFF0000)>>16,0x00FF);
4073 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L, (MS_U16)(u32IPMBase1 & 0xFFFF));
4074
4075 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_0D_L, (MS_U16)(u32IPMBase2 & 0xFF0000)>>16,0x00FF);
4076 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0C_L, (MS_U16)(u32IPMBase2 & 0xFFFF));
4077
4078
4079 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, pFrameBufInfo.u16IPMOffset);
4080 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, pFrameBufInfo.u16IPMFetch);
4081 // SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, (pFrameBufInfo.u16VLength|0x1000),0x1FFF);
4082 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_03_L, ((pFrameBufInfo.bLinearAddrMode)?BIT(4):0),BIT(4));
4083
4084 }
4085
Hal_SC_get_cs_det_cnt(void * pInstance,SCALER_WIN eWindow)4086 MS_U8 Hal_SC_get_cs_det_cnt(void *pInstance, SCALER_WIN eWindow)
4087 {
4088 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4089 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4090 MS_U8 u8val;
4091
4092 if(eWindow == MAIN_WINDOW)
4093 {
4094 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0C_L) & 0xFF00) >> 8);
4095 }
4096 else
4097 {
4098 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_0C_L) & 0xFF00) >> 8);
4099 }
4100 return u8val;
4101 }
4102
Hal_SC_set_cs_det_cnt(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)4103 void Hal_SC_set_cs_det_cnt(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
4104 {
4105 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4106 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4107 if(eWindow == MAIN_WINDOW)
4108 {
4109 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0C_L, (((MS_U16)u8val)<<8), 0xFF00);
4110 }
4111 else
4112 {
4113 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0C_L, (((MS_U16)u8val)<<8), 0xFF00);
4114 }
4115 }
4116
Hal_SC_get_plus_width(void * pInstance,SCALER_WIN eWindow)4117 MS_U8 Hal_SC_get_plus_width(void *pInstance, SCALER_WIN eWindow)
4118 {
4119 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4120 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4121 MS_U8 u8val;
4122
4123 if(eWindow == MAIN_WINDOW)
4124 {
4125 u8val = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_22_L) & 0x00FF);
4126 }
4127 else
4128 {
4129 u8val = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_22_L) & 0x00FF);
4130 }
4131 return u8val;
4132 }
4133
Hal_SC_set_opm_fetch(void * pInstance,SCALER_WIN eWindow,MS_U16 u16OPMFetch)4134 void Hal_SC_set_opm_fetch(void *pInstance, SCALER_WIN eWindow, MS_U16 u16OPMFetch)
4135 {
4136 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4137 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4138 if(eWindow == MAIN_WINDOW)
4139 {
4140 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, u16OPMFetch, 0x1FFF);
4141 }
4142 else
4143 {
4144 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, u16OPMFetch, 0x1FFF);
4145 }
4146 }
4147
Hal_SC_get_opm_fetch(void * pInstance,SCALER_WIN eWindow)4148 MS_U16 Hal_SC_get_opm_fetch(void *pInstance, SCALER_WIN eWindow)
4149 {
4150 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4151 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4152 MS_U16 u16Val = 0;
4153 if(eWindow == MAIN_WINDOW)
4154 {
4155 u16Val = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L) & 0x0FFF;
4156 }
4157 else
4158 {
4159 u16Val = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L) & 0x0FFF;
4160 }
4161 return u16Val;
4162 }
4163
HAL_SC_get_dnr_setting(void * pInstance,SCALER_WIN eWindow)4164 MS_U8 HAL_SC_get_dnr_setting(void *pInstance, SCALER_WIN eWindow)
4165 {
4166 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4167 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4168 if(eWindow == MAIN_WINDOW)
4169 return (MS_U8)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_21_L, BIT(1)|BIT(0));
4170 else
4171 return (MS_U8)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_01_L, BIT(1)|BIT(0));
4172 }
4173
HAL_SC_enable_field_avg_y(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4174 void HAL_SC_enable_field_avg_y(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4175 {
4176 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4177 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4178 if(eWindow == MAIN_WINDOW)
4179 {
4180 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_21_L, bEnable ? BIT(6) : 0, BIT(6));
4181 }
4182 else
4183 {
4184 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_01_L, bEnable ? BIT(6) : 0, BIT(6));
4185 }
4186
4187 }
4188
HAL_SC_enable_field_avg_c(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4189 void HAL_SC_enable_field_avg_c(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4190 {
4191 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4192 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4193 if(eWindow == MAIN_WINDOW)
4194 {
4195 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_21_L, bEnable ? BIT(7) : 0, BIT(7));
4196 }
4197 else
4198 {
4199 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_01_L, bEnable ? BIT(7) : 0, BIT(7));
4200 }
4201 }
4202
HAL_SC_enable_dnr(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)4203 void HAL_SC_enable_dnr(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
4204 {
4205 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4206 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4207 if(eWindow == MAIN_WINDOW)
4208 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_21_L, u8Val, BIT(1)|BIT(0));
4209 else
4210 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_01_L, u8Val, BIT(1)|BIT(0));
4211 }
4212
HAL_SC_VOP_Set_Contrast_En(void * pInstance,MS_BOOL bEenable,SCALER_WIN eWindow)4213 void HAL_SC_VOP_Set_Contrast_En(void *pInstance, MS_BOOL bEenable, SCALER_WIN eWindow)
4214 {
4215 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4216 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4217 if(eWindow == MAIN_WINDOW)
4218 {
4219 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(0):0), BIT(0));
4220 }
4221 else
4222 {
4223 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(8):0), BIT(8));
4224 }
4225 }
HAL_SC_VOP_Set_Contrast_Value(void * pInstance,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val,SCALER_WIN eWindow)4226 void HAL_SC_VOP_Set_Contrast_Value(void *pInstance, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val, SCALER_WIN eWindow)
4227 {
4228 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4229 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4230 if(eWindow == MAIN_WINDOW)
4231 {
4232 switch(eVop_Channel)
4233 {
4234 default:
4235 case XC_VOP_CHR:
4236 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_47_L, u16Val, 0x0FFF);
4237 break;
4238 case XC_VOP_CHG:
4239 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_48_L, u16Val, 0x0FFF);
4240 break;
4241 case XC_VOP_CHB:
4242 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_49_L, u16Val, 0x0FFF);
4243 break;
4244 case XC_VOP_ALL:
4245 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_47_L, u16Val, 0x0FFF);
4246 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_48_L, u16Val, 0x0FFF);
4247 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_49_L, u16Val, 0x0FFF);
4248 break;
4249 }
4250 }
4251 else
4252 {
4253 switch(eVop_Channel)
4254 {
4255 default:
4256 case XC_VOP_CHR:
4257 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4A_L, u16Val, 0x0FFF);
4258 break;
4259 case XC_VOP_CHG:
4260 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4B_L, u16Val, 0x0FFF);
4261 break;
4262 case XC_VOP_CHB:
4263 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4C_L, u16Val, 0x0FFF);
4264 break;
4265 case XC_VOP_ALL:
4266 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4A_L, u16Val, 0x0FFF);
4267 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4B_L, u16Val, 0x0FFF);
4268 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4C_L, u16Val, 0x0FFF);
4269 break;
4270 }
4271 }
4272 }
4273
HAL_SC_VOP_Set_Brightness_En(void * pInstance,MS_BOOL bEenable,SCALER_WIN eWindow)4274 void HAL_SC_VOP_Set_Brightness_En(void *pInstance, MS_BOOL bEenable, SCALER_WIN eWindow)
4275 {
4276 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4277 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4278 if(eWindow == MAIN_WINDOW)
4279 {
4280 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(1):0), BIT(1));
4281 }
4282 else
4283 {
4284 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(9):0), BIT(9));
4285 }
4286 }
HAL_SC_VOP_Set_Brightness_Value(void * pInstance,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val,SCALER_WIN eWindow)4287 void HAL_SC_VOP_Set_Brightness_Value(void *pInstance, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val, SCALER_WIN eWindow)
4288 {
4289 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4290 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4291 if(eWindow == MAIN_WINDOW)
4292 {
4293 switch(eVop_Channel)
4294 {
4295 default:
4296 case XC_VOP_CHR:
4297 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4D_L, u16Val, 0x07FF);
4298 break;
4299 case XC_VOP_CHG:
4300 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4E_L, u16Val, 0x07FF);
4301 break;
4302 case XC_VOP_CHB:
4303 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4F_L, u16Val, 0x07FF);
4304 break;
4305 case XC_VOP_ALL:
4306 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4D_L, u16Val, 0x07FF);
4307 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4E_L, u16Val, 0x07FF);
4308 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4F_L, u16Val, 0x07FF);
4309 break;
4310 }
4311 }
4312 else
4313 {
4314 switch(eVop_Channel)
4315 {
4316 default:
4317 case XC_VOP_CHR:
4318 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_50_L, u16Val, 0x07FF);
4319 break;
4320 case XC_VOP_CHG:
4321 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_51_L, u16Val, 0x07FF);
4322 break;
4323 case XC_VOP_CHB:
4324 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_52_L, u16Val, 0x07FF);
4325 break;
4326 case XC_VOP_ALL:
4327 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_50_L, u16Val, 0x07FF);
4328 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_51_L, u16Val, 0x07FF);
4329 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_52_L, u16Val, 0x07FF);
4330 break;
4331 }
4332 }
4333 }
4334
HAL_SC_Set_FB_Num(void * pInstance,SCALER_WIN eWindow,XC_FRAME_STORE_NUMBER enFBType,MS_BOOL bInterlace)4335 void HAL_SC_Set_FB_Num(void *pInstance, SCALER_WIN eWindow, XC_FRAME_STORE_NUMBER enFBType, MS_BOOL bInterlace)
4336 {
4337 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4338 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4339 MS_U8 u8FrameCount = 2;
4340
4341 switch( enFBType )
4342 {
4343 case IMAGE_STORE_2_FRAMES:
4344 u8FrameCount = 2;
4345 break;
4346 case IMAGE_STORE_3_FRAMES:
4347 u8FrameCount = 3;
4348 break;
4349 case IMAGE_STORE_4_FRAMES:
4350 u8FrameCount = 4;
4351 break;
4352 case IMAGE_STORE_6_FRAMES:
4353 u8FrameCount = 6;
4354 break;
4355 case IMAGE_STORE_8_FRAMES:
4356 u8FrameCount = 8;
4357 break;
4358 case IMAGE_STORE_12_FRAMES:
4359 u8FrameCount = 12;
4360 break;
4361 default:
4362 break;
4363 }
4364
4365 if (!bInterlace)
4366 {
4367 if (eWindow == MAIN_WINDOW)
4368 {
4369 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L, u8FrameCount , BITMASK(4:0) );
4370 }
4371 else
4372 {
4373 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L, u8FrameCount , BITMASK(4:0) );
4374 }
4375 }
4376 }
4377
HAL_SC_Enable_VInitFactor(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4378 void HAL_SC_Enable_VInitFactor(void *pInstance, MS_BOOL bEnable,SCALER_WIN eWindow)
4379 {
4380 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4381 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4382 if (eWindow == MAIN_WINDOW)
4383 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_13_L, (MS_U16)(bEnable?BIT(0):0), BIT(0));
4384 else
4385 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_33_L, (MS_U16)(bEnable?BIT(0):0), BIT(0));
4386 }
4387
HAL_SC_Set_VInitFactorOne(void * pInstance,MS_U32 u32Value,SCALER_WIN eWindow)4388 void HAL_SC_Set_VInitFactorOne(void *pInstance, MS_U32 u32Value,SCALER_WIN eWindow)
4389 {
4390 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4391 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4392 if (eWindow == MAIN_WINDOW)
4393 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_03_L, u32Value);
4394 else
4395 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_23_L, u32Value);
4396 }
4397
HAL_SC_Set_VInitFactorTwo(void * pInstance,MS_U32 u32Value,SCALER_WIN eWindow)4398 void HAL_SC_Set_VInitFactorTwo(void *pInstance, MS_U32 u32Value,SCALER_WIN eWindow)
4399 {
4400 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4401 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4402 if (eWindow == MAIN_WINDOW)
4403 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_05_L, u32Value);
4404 else
4405 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_25_L, u32Value);
4406 }
4407
HAL_SC_Set_vsd_output_line_count(void * pInstance,MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_WIN eWindow)4408 void HAL_SC_Set_vsd_output_line_count(void *pInstance, MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_WIN eWindow)
4409 {
4410 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4411 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4412 MS_U16 u16OutputLineCount = 0x00;
4413
4414 if (bEnable)
4415 {
4416 u16OutputLineCount = BIT(15);
4417 u16OutputLineCount |= (MS_U16)(u32LineCount & 0x1FFF);
4418 }
4419
4420 if (eWindow == MAIN_WINDOW)
4421 {
4422 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_37_L, u16OutputLineCount);
4423 }
4424 else
4425 {
4426 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_37_L, u16OutputLineCount);
4427 }
4428
4429 }
4430
4431 /*
4432 bEnable : Enable input line count.
4433 bUserMode : 1 -> the input line count will ref u32UserLineCount
4434 0 -> the input line count will ref V capture win
4435 */
HAL_SC_Set_vsd_input_line_count(void * pInstance,MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_WIN eWindow)4436 void HAL_SC_Set_vsd_input_line_count(void *pInstance, MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_WIN eWindow)
4437 {
4438 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4439 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4440 MS_U16 u16InputLineCount = 0x00;
4441
4442 if (bEnable)
4443 {
4444 u16InputLineCount = BIT(15);
4445
4446 if (bUserMode)
4447 {
4448 u16InputLineCount |= BIT(14);
4449 u16InputLineCount |= (MS_U16)(u32UserLineCount & 0x1FFF);
4450 }
4451 }
4452
4453 if (eWindow == MAIN_WINDOW)
4454 {
4455 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_36_L, u16InputLineCount);
4456 }
4457 else
4458 {
4459 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_36_L, u16InputLineCount);
4460 }
4461
4462 }
4463
Hal_SC_CheckSubWinPreScaling(MS_U16 u16ScaleDst,MS_BOOL bInterlace)4464 MS_U32 Hal_SC_CheckSubWinPreScaling(MS_U16 u16ScaleDst,MS_BOOL bInterlace)
4465 {
4466 UNUSED(u16ScaleDst);
4467 UNUSED(bInterlace);
4468 //New chip sub window unnecessary to the same with the main window's pre scaling setting.
4469 return 0;
4470 }
4471
HAL_SC_FilmMode_Patch1(void * pInstance)4472 void HAL_SC_FilmMode_Patch1(void *pInstance)
4473 {
4474 #if 1
4475 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4476 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4477 MS_U16 u16Value;
4478 MS_U16 u16RegValue;
4479 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4480 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4481
4482 u16RegValue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK22_7D_L, 0xFF);
4483 if(pXCResourcePrivate->sthal_SC.g_bCntFlg)
4484 pXCResourcePrivate->sthal_SC.g_u16TmpValue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, 0xFF);
4485
4486 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_21_L, BIT(6)))
4487 {
4488 //Counter
4489 if(pXCResourcePrivate->sthal_SC.u8Time_count != 0xFF)
4490 pXCResourcePrivate->sthal_SC.u8Time_count ++;
4491
4492 if(pXCResourcePrivate->sthal_SC.u8Time_count < u16RegValue) // fake out duration
4493 u16Value = 0x06; // madi fake out enable
4494 else
4495 u16Value = 0x00; // madi fake out disable
4496
4497 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_25_L, (0x10<<8), 0xFF00);
4498 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, 0x22, 0xFF);
4499 pXCResourcePrivate->sthal_SC.g_bCntFlg = 0;
4500 }
4501 else
4502 {
4503 pXCResourcePrivate->sthal_SC.u8Time_count = 0;
4504 u16Value = 0x00; // madi fake out disable
4505 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_25_L, (0x08<<8), 0xFF00);
4506 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, pXCResourcePrivate->sthal_SC.g_u16TmpValue, 0xFF);
4507 pXCResourcePrivate->sthal_SC.g_bCntFlg = 1;
4508 }
4509 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_21_L, u16Value, BIT(2)|BIT(1));
4510
4511 #else
4512 MS_U8 u8Bank, u8Value;
4513 MS_U8 u8RegValue;
4514
4515 static MS_U8 u8Time_count = 0;
4516
4517 MDrv_WriteByte(BK_SELECT_00, REG_BANK_MADI); //bk22
4518 u8RegValue = MDrv_ReadByte(L_BK_MADI(0x7D));
4519
4520 MDrv_WriteByte(BK_SELECT_00, REG_BANK_FILM);
4521
4522
4523 if(MDrv_ReadRegBit(L_BK_FILM(0x21), BIT(6)))
4524 {
4525 //Counter
4526 if(u8Time_count != 0xFF)
4527 u8Time_count ++;
4528
4529 if(u8Time_count < u8RegValue) // fake out duration
4530 u8Value = 0x06; // madi fake out enable
4531 else
4532 u8Value = 0x00; // madi fake out disable
4533
4534 MDrv_WriteByte(H_BK_FILM(0x25), 0x10);
4535
4536 }
4537 else
4538 {
4539 u8Time_count = 0;
4540 u8Value = 0x00; // madi fake out disable
4541 MDrv_WriteByte(H_BK_FILM(0x25), 0x08);
4542 }
4543
4544 MDrv_WriteByteMask(L_BK_FILM(0x21), u8Value, BIT(2)|BIT(1));
4545 MDrv_WriteByte(BK_SELECT_00, u8Bank);
4546 #endif
4547 }
4548
HAL_SC_EnableFPLL(void)4549 void HAL_SC_EnableFPLL(void)
4550 {
4551 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3));
4552 MDrv_WriteByteMask(L_BK_LPLL(0x0C), 0, BIT(6));
4553 }
4554
4555
_HAL_SC_GetFPLLPhaseDiffISR(SC_INT_SRC eIntNum,void * pParam)4556 static void _HAL_SC_GetFPLLPhaseDiffISR(SC_INT_SRC eIntNum, void *pParam)
4557 {
4558 volatile MS_XC_GET_FPLL_PHASEDIFF * pFpllPhaseDiff = (volatile MS_XC_GET_FPLL_PHASEDIFF *) pParam;
4559
4560 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11));
4561 pFpllPhaseDiff->eFpllDir = (MDrv_Read2Byte(L_BK_LPLL(0x12)) & BIT(0)) == BIT(0) ? E_XC_FPLL_DIR_UP : E_XC_FPLL_DIR_DOWN;
4562 pFpllPhaseDiff->u8Debounce++;
4563
4564 if(pFpllPhaseDiff->u8Debounce > 3)
4565 {
4566 if(pFpllPhaseDiff->u16PhaseDiff < 0x200)
4567 {
4568 pFpllPhaseDiff->eFpllResult = E_XC_FPLL_RES_FINISHED;
4569 }
4570 else
4571 {
4572 if(pFpllPhaseDiff->u8Debounce > 90)
4573 {
4574 pFpllPhaseDiff->eFpllResult = E_XC_FPLL_RES_TIMEOUT;
4575 }
4576 }
4577 }
4578 }
4579
HAL_SC_WaitFPLLDone(void * pInstance)4580 MS_BOOL HAL_SC_WaitFPLLDone(void *pInstance)
4581 {
4582 MS_XC_GET_FPLL_PHASEDIFF stGetFpllPhaseDiff = {0, 0, E_XC_FPLL_DIR_UNKNOWN, E_XC_FPLL_RES_WAITING};
4583
4584 MDrv_XC_InterruptAttach(pInstance, SC_INT_VSINT, _HAL_SC_GetFPLLPhaseDiffISR, (void *) &stGetFpllPhaseDiff);
4585 while(*(volatile MS_BOOL*)(&(stGetFpllPhaseDiff.eFpllResult)) == E_XC_FPLL_RES_WAITING);
4586 MDrv_XC_InterruptDeAttach(pInstance, SC_INT_VSINT, _HAL_SC_GetFPLLPhaseDiffISR, (void *) &stGetFpllPhaseDiff);
4587
4588 if(stGetFpllPhaseDiff.eFpllResult == E_XC_FPLL_RES_FINISHED)
4589 {
4590 return TRUE;
4591 }
4592 else
4593 {
4594 return FALSE;
4595 }
4596 }
4597
HAL_SC_GetOutputVFreqX100(MS_U32 u32XTAL_Clock)4598 MS_U16 HAL_SC_GetOutputVFreqX100(MS_U32 u32XTAL_Clock)
4599 {
4600 return ((MS_U16) ((u32XTAL_Clock * 100) / MDrv_Read4Byte(L_BK_LPLL(0x23))));
4601 }
4602
4603 //Line buffer offset between Main and Sub, MAX(Main+Sub) = 1920+960
4604 //Main Win Line buffer offset , start from max size of main's
HAL_SC_SetMainLineBufferOffset(void * pInstance,MS_U16 u16Linebuffer)4605 void HAL_SC_SetMainLineBufferOffset(void *pInstance, MS_U16 u16Linebuffer)
4606 {
4607 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4608 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4609 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_12_L, u16Linebuffer);
4610 }
4611
4612 //Line buffer offset between Main and Sub, MAX(Main+Sub) = 1920+960
4613 //Sub Win Line buffer offset , start from max size of main's
HAL_SC_SetSubLineBufferOffset(void * pInstance,MS_U16 u16Linebuffer)4614 void HAL_SC_SetSubLineBufferOffset(void *pInstance, MS_U16 u16Linebuffer)
4615 {
4616 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4617 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4618 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_13_L, u16Linebuffer);
4619 }
4620
4621 //Select the trig mode
4622 //0: Line base(Line Buffer Mode)
4623 //1: Fill line buffer(Ring Buffer Mode)
HAL_SC_SetDisplay_LineBuffer_Mode(void * pInstance,MS_BOOL bEnable)4624 void HAL_SC_SetDisplay_LineBuffer_Mode(void *pInstance, MS_BOOL bEnable)
4625 {
4626 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4627 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4628 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1F_L, (bEnable ? BIT(4) : 0), BIT(4));
4629 }
4630
4631 //Select the start mode
4632 //0: start at advance 1 display line
4633 //1: start at faling edge of Vsync_init
HAL_SC_SetDisplay_Start_Mode(void * pInstance,MS_BOOL bEnable)4634 void HAL_SC_SetDisplay_Start_Mode(void *pInstance, MS_BOOL bEnable)
4635 {
4636 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4637 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4638 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1F_L, (bEnable ? BIT(5) : 0), BIT(5));
4639 }
4640
4641 //bk20_10[10]: Fill the main window's line buffer in vertical blanking for pip left and up corner
4642 //bk20_10[11]: Fill the sub window's line buffer in vertical blanking for pip left and down corner
HAL_SC_FillLineBuffer(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4643 void HAL_SC_FillLineBuffer(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4644 {
4645 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4646 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4647 if(bEnable)
4648 {
4649 if(eWindow == MAIN_WINDOW)
4650 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(10), BIT(10));
4651 else
4652 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(11), BIT(11));
4653 }
4654 else
4655 {
4656 if(eWindow == MAIN_WINDOW)
4657 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(10));
4658 else
4659 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(11));
4660 }
4661 }
4662
Hal_SC_enable_window(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)4663 void Hal_SC_enable_window(void *pInstance, MS_BOOL bEn,SCALER_WIN eWindow)
4664 {
4665 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4666 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4667 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4668 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4669
4670 if (eWindow == MAIN_WINDOW)
4671 {
4672 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, bEn ? BIT(0) : 0, BIT(0));
4673 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4674 if (psXCInstPri->u32DeviceID == 1)
4675 {
4676 if (bEn)
4677 {
4678 MHal_XC_PixelShiftStatusChange(pInstance, EN_XC_PIXEL_SHIFT_DISABLE);
4679 }
4680 // set SC1 auto no signal by SC1 control
4681 SC_W2BYTEMSK(0, REG_SC_BK11_07_L, bEn ? BIT(5) : 0, BIT(5));
4682 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4683 if (Hal_SC_3D_IsDualViewMode(pInstance, eWindow))
4684 {
4685 SC_W2BYTEMSK(0, REG_SC_BK20_10_L, bEn ? BIT(1) : 0, BIT(1));
4686 }
4687 else
4688 #endif
4689 {
4690 SC_W2BYTEMSK(0, REG_SC_BK20_10_L, bEn ? BIT(2)|BIT(1) : 0, BIT(2)|BIT(1));
4691 SC_W2BYTEMSK(0, REG_SC_BK68_40_L, bEn ? BIT(4) : 0, BIT(4));
4692 }
4693 SC_W2BYTEMSK(0, REG_SC_BK46_3F_L, bEn ? 0 : BIT(0), BIT(0));
4694 }
4695 #endif
4696 }
4697 else
4698 {
4699 // Sub prefill line must be enable, when PIP on (enable input source of sub win)
4700 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(11) , BIT(11));
4701 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, bEn ? BIT(1) : 0, BIT(1));
4702 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK58_10_L, bEn ? BIT(0) : 0, BIT(0));
4703 }
4704 }
4705
_Hal_SC_GetInputVPeriod(void * pInstance,SCALER_WIN eWindow)4706 static MS_U16 _Hal_SC_GetInputVPeriod(void *pInstance, SCALER_WIN eWindow)
4707 {
4708 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4709 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4710 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4711 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4712 MS_U16 u16VFreq = gSrcInfo[eWindow].u16InputVFreq * 10;
4713 SC_DBG(printf("(100000+u16VFreq/2)/u16VFreq)=%u, u16VFreq=%u\n",((100000+u16VFreq/2)/u16VFreq), u16VFreq));
4714 if(u16VFreq == 0)
4715 {
4716 return 0;
4717 }
4718 else
4719 {
4720 return ((100000+u16VFreq/2)/u16VFreq); //Period = 1000/(vfreq/100)
4721 }
4722 }
4723
Hal_SC_enable_window_burst(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)4724 void Hal_SC_enable_window_burst(void *pInstance, MS_BOOL bEn,SCALER_WIN eWindow)
4725 {
4726 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4727 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4728 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4729 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4730 _MLOAD_ENTRY(pInstance);
4731 if (eWindow == MAIN_WINDOW)
4732 {
4733 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, bEn ? BIT(0) : 0, BIT(0));
4734 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4735 void *pInstanceTmp = NULL;
4736 if (psXCInstPri->u32DeviceID == 1)
4737 {
4738 pInstanceTmp = pInstance; // store instance 0
4739 pInstance = g_pDevice0Instance; //switch to instance 1
4740 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4741 // PIP enable need disable pixelshift
4742 if (bEn)
4743 {
4744 MHal_XC_PixelShiftStatusChange(pInstanceTmp, EN_XC_PIXEL_SHIFT_DISABLE);
4745 }
4746 // set SC1 auto no signal by SC1 control
4747 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_07_L, bEn ? BIT(5) : 0, BIT(5));
4748 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4749 if (Hal_SC_3D_IsDualViewMode(pInstance, eWindow))//FIXME: Manhattan dual view patch
4750 {
4751 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, bEn ? BIT(1) : 0, BIT(2)|BIT(1));
4752 }
4753 else
4754 #endif
4755 {
4756 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, bEn ? BIT(2)|BIT(1) : 0, BIT(2)|BIT(1));
4757 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_40_L, bEn ? BIT(4) : 0, BIT(4));
4758 }
4759 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3F_L, bEn ? 0 : BIT(0), BIT(0));
4760 //MDrv_WriteRegBit(REG_CLKGEN2_BASE + 0x87, bEn ? TRUE : FALSE, BIT(1));//FIXME:patch for PIP
4761 pInstance = pInstanceTmp; // restore instance 0
4762 }
4763
4764 #endif
4765
4766 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4767 }
4768 else
4769 {
4770 if(bEn == TRUE)
4771 {
4772 MS_U16 u16extra_req = 0;
4773 MS_U16 u16Delaytime = 0;
4774
4775 // When Main is foreground, sub is background, extra must enable.
4776 u16extra_req = 0x01;
4777
4778 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL , NULL , NULL))
4779 {
4780 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
4781 u16extra_req = u16extra_req | 0x8000;
4782 }
4783
4784 // HW PIP architeucture
4785 // Becasue BK3_02[8] and BK20_11[15] should enable together, otherwise garbage will be showed,
4786 // we need to use BK12_47[0] to instead. And the default value of BK3_02[8] is 1. So, we need
4787 // to set it to 0 in this function.
4788 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, u16extra_req , 0x800F);
4789 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, 0, 0x0080);
4790
4791 // Sub prefill line must be enable, when PIP on (enable input source of sub win)
4792 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, BIT(11), BIT(11) );
4793 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4794 //if we let REG_SC_BK20_10_L[1] to enable with other register settings in the same menuload fire
4795 //it will produce a rectangular horizontal noise. so we move outside to let those register settings
4796 //to be set first then let REG_SC_BK20_10_L[1] on.
4797
4798 //betwen REG_SC_BK03_02_L[7] and REG_SC_BK20_10_L[1], we need to delay time of wr mapping mode,
4799 // to let the data fill in xc sub buffer
4800 u16Delaytime = _Hal_SC_GetInputVPeriod(pInstance, eWindow) * (Hal_SC_Get_WR_Bank_Mapping(pInstance, eWindow) + 1);
4801 MsOS_DelayTask(u16Delaytime);
4802
4803 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, BIT(1), BIT(1));
4804 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK58_10_L, BIT(0), BIT(0));
4805
4806 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4807 }
4808 else
4809 {
4810 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK58_10_L, 0, BIT(0));
4811 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, 0, BIT(1));
4812 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4813 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, 0x0080, 0x0080);
4814 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4815 }
4816 }
4817
4818 _MLOAD_RETURN(pInstance);
4819 }
4820
Hal_SC_set_trigger_signal(void)4821 void Hal_SC_set_trigger_signal(void)
4822 {
4823 // only used in U4
4824 }
4825
Hal_SC_Set_OSD2VE(void * pInstance,EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)4826 void Hal_SC_Set_OSD2VE(void *pInstance, EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)
4827 {
4828 UNUSED(eVOPSelOSD_MUX);
4829 }
4830
Hal_SC_IsOPMFetchPatch_Enable(void)4831 MS_BOOL Hal_SC_IsOPMFetchPatch_Enable(void)
4832 {
4833 //Patch for Janus u01 and T4 U01/02: OPMFetch need +2
4834 return FALSE;
4835 }
Hal_SC_Check_HNonLinearScaling(void * pInstance)4836 MS_BOOL Hal_SC_Check_HNonLinearScaling(void *pInstance)
4837 {
4838 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4839 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4840 MS_U16 u16Offset = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_15_L)>>8);
4841 MS_U16 u16MaxOffset = ((SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L) & 0xFFFFFF)>>12);
4842 //Non-Linear scaling Postive offset, the maximum offset is HPstRatio[23:12]
4843 if(((u16Offset & BIT(7)) == 0) && (u16Offset > u16MaxOffset))
4844 {
4845 return FALSE;
4846 }
4847 return TRUE;
4848 }
4849
4850 //IP2 Pre-Filter enable
Hal_SC_IP2_PreFilter_Enable(void * pInstance,MS_BOOL bEnable)4851 void Hal_SC_IP2_PreFilter_Enable(void* pInstance, MS_BOOL bEnable)
4852 {
4853 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4854 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4855 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_48_L, (bEnable?BIT(15):0), BIT(15));
4856 }
4857
Hal_SC_Set_extra_fetch_line(void * pInstance,MS_U8 u8val)4858 void Hal_SC_Set_extra_fetch_line(void *pInstance, MS_U8 u8val)
4859 {
4860 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4861 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4862 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_17_L, ((MS_U16)(u8val & 0x0F))<<8, 0x0F00);
4863 }
4864
Hal_SC_Set_extra_adv_line(void * pInstance,MS_U8 u8val)4865 void Hal_SC_Set_extra_adv_line(void *pInstance, MS_U8 u8val)
4866 {
4867 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4868 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4869 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_17_L, ((MS_U16)(u8val & 0x0F))<<12, 0xF000);
4870 }
4871
HAL_SC_Set_FPLL_Limit(void * pInstance,MS_U32 * u32PllSet,MS_U32 u32LowBound,MS_U32 u32UpBound,MS_BOOL _bInFPLLDbgMode,MS_U32 _U32LimitD5D6D7)4872 void HAL_SC_Set_FPLL_Limit(void *pInstance, MS_U32 *u32PllSet, MS_U32 u32LowBound, MS_U32 u32UpBound, MS_BOOL _bInFPLLDbgMode, MS_U32 _U32LimitD5D6D7)
4873 {
4874 MS_U32 u32LpllLimitLow, u32LpllLimitHigh;
4875 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4876 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4877 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4878 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4879 //printf("Fpll_Limit: Set %lx, bound (%lx -> %lx)\n", *u32PllSet, u32UpBound, u32LowBound);
4880
4881 if(_bInFPLLDbgMode)
4882 {
4883 MDrv_WriteByteMask(L_BK_LPLL(0x0D), 0x00, BIT(4)); // turn off 2 limit
4884 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
4885 {
4886 MDrv_Write3Byte(L_BK_LPLL(0x06), _U32LimitD5D6D7);
4887 }
4888 }
4889 else
4890 {
4891 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit
4892
4893 // check if u32PllSet out of range and also the FPLL limit
4894 if (*u32PllSet <= u32LowBound)
4895 {
4896 *u32PllSet = u32LowBound;
4897 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
4898 }
4899 else if (*u32PllSet >= u32UpBound)
4900 {
4901 *u32PllSet = u32UpBound;
4902 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
4903 }
4904
4905 u32LpllLimitHigh = u32UpBound - *u32PllSet;
4906 u32LpllLimitLow = *u32PllSet - u32LowBound - 1;
4907
4908 //printf("Fpll set %lx, limit (high %lx, low %lx)\n", *u32PllSet, u32LpllLimitHigh, u32LpllLimitLow);
4909
4910 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
4911 {
4912 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh);
4913 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow);
4914 }
4915
4916 //printf("Fpll limit reg (high %lx, low %lx)\n", MDrv_Read4Byte(L_BK_LPLL(0x06)), MDrv_Read4Byte(L_BK_LPLL(0x08)));
4917 }
4918 }
4919
Hal_XC_H3D_Enable(void * pInstance,MS_BOOL bEn)4920 void Hal_XC_H3D_Enable(void *pInstance, MS_BOOL bEn)
4921 {
4922 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4923 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4924 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_70_L, (bEn<<15), (BIT(15)));
4925 }
4926
Hal_XC_H3D_Input3DType(void * pInstance,E_XC_3D_INPUT_MODE e3DType)4927 void Hal_XC_H3D_Input3DType(void *pInstance, E_XC_3D_INPUT_MODE e3DType)
4928 {
4929 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4930 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4931 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (e3DType), (BIT(1) | BIT(0)));
4932 }
4933
Hal_XC_H3D_Breakline_Enable(void * pInstance,MS_BOOL bEn)4934 void Hal_XC_H3D_Breakline_Enable(void *pInstance, MS_BOOL bEn)
4935 {
4936 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4937 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4938 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (bEn<<7), (BIT(7)));
4939 if(bEn)
4940 {
4941 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (8<<8), HBMASK);
4942 }
4943 else
4944 {
4945 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (0<<8), HBMASK);
4946 }
4947 }
4948
Hal_XC_H3D_HDE(void * pInstance,MS_U16 u16Hde)4949 void Hal_XC_H3D_HDE(void *pInstance, MS_U16 u16Hde)
4950 {
4951 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4952 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4953 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_71_L, (u16Hde), 0x0FFF);
4954 }
4955
Hal_XC_H3D_VDE_F0(MS_U16 u16Vde)4956 void Hal_XC_H3D_VDE_F0(MS_U16 u16Vde)
4957 {
4958 SC_W2BYTEMSK(0, REG_SC_BK01_73_L, (u16Vde), 0x0FFF);
4959 }
4960
Hal_XC_H3D_VDE_F2(MS_U16 u16Vde)4961 void Hal_XC_H3D_VDE_F2(MS_U16 u16Vde)
4962 {
4963 SC_W2BYTEMSK(0, REG_SC_BK01_77_L, (u16Vde), 0x0FFF);
4964 }
4965
Hal_XC_H3D_HBLANK(MS_U16 u16Hblank)4966 void Hal_XC_H3D_HBLANK(MS_U16 u16Hblank)
4967 {
4968 SC_W2BYTEMSK(0, REG_SC_BK01_70_L, (u16Hblank), 0x03FF);
4969 }
4970
Hal_XC_H3D_INIT_VBLANK(MS_U8 u8Vblank)4971 void Hal_XC_H3D_INIT_VBLANK(MS_U8 u8Vblank)
4972 {
4973 SC_W2BYTEMSK(0, REG_SC_BK01_72_L, (u8Vblank), LBMASK);
4974 }
4975
Hal_XC_H3D_VBLANK0(MS_U8 u8Vblank)4976 void Hal_XC_H3D_VBLANK0(MS_U8 u8Vblank)
4977 {
4978 SC_W2BYTEMSK(0, REG_SC_BK01_74_L, (u8Vblank), LBMASK);
4979 }
4980
Hal_XC_H3D_VBLANK1(MS_U8 u8Vblank)4981 void Hal_XC_H3D_VBLANK1(MS_U8 u8Vblank)
4982 {
4983 SC_W2BYTEMSK(0, REG_SC_BK01_76_L, (u8Vblank), LBMASK);
4984 }
4985
Hal_XC_H3D_VBLANK2(MS_U8 u8Vblank)4986 void Hal_XC_H3D_VBLANK2(MS_U8 u8Vblank)
4987 {
4988 SC_W2BYTEMSK(0, REG_SC_BK01_78_L, (u8Vblank), LBMASK);
4989 }
4990
Hal_XC_H3D_VSYNC_WIDTH(MS_U8 u8Width)4991 void Hal_XC_H3D_VSYNC_WIDTH(MS_U8 u8Width)
4992 {
4993 SC_W2BYTEMSK(0, REG_SC_BK01_7A_L, (u8Width), 0x001F);
4994 }
4995
Hal_XC_H3D_VSYNC_POSITION(MS_U16 u16Position)4996 void Hal_XC_H3D_VSYNC_POSITION(MS_U16 u16Position)
4997 {
4998 SC_W2BYTEMSK(0, REG_SC_BK01_7A_L, (u16Position), HBMASK);
4999 }
5000
Hal_XC_H3D_SELECT_REGEN_TIMING(MS_BOOL bEn)5001 void Hal_XC_H3D_SELECT_REGEN_TIMING(MS_BOOL bEn)
5002 {
5003 SC_W2BYTEMSK(0, REG_SC_BK01_7B_L, (bEn<<4), (BIT(4)));
5004 }
5005
Hal_XC_H3D_LR_Toggle_Enable(void * pInstance,MS_BOOL bEn,MS_BOOL b2DTo3D,MS_BOOL bSkipDefaultLRFlag)5006 void Hal_XC_H3D_LR_Toggle_Enable(void *pInstance, MS_BOOL bEn, MS_BOOL b2DTo3D, MS_BOOL bSkipDefaultLRFlag)
5007 {
5008 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5009 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5010 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5011 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5012
5013 if(!bSkipDefaultLRFlag)
5014 {
5015 if(bEn)
5016 {
5017 //Enanble I2S_IN_SD to send out lr flag
5018 MDrv_WriteByteMask(0x101E24, 0x00, BIT(4)|BIT(5)|BIT(6));
5019 MDrv_WriteByteMask(0x101EC9, 0x00, BIT(0)|BIT(1));
5020 MDrv_WriteByteMask(0x101EDC, 0x00, BIT(2));
5021 MDrv_WriteByteMask(0x101EB3, 0xC0, 0xC0);
5022 // after timing change , hw must do L/R alignment,BK12, 33[2]=1 to enable it.
5023 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, BIT(2), BIT(2));
5024 }
5025 else
5026 {
5027 MDrv_WriteByteMask(0x101EB3, 0x00, 0xC0);
5028 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, BIT(2));
5029 }
5030 }
5031
5032 ///3D lr flag selection: RD's advice
5033 ///{BK20_24[13], BK20_24[11], BK20_24[1:0]}
5034 ///4'b0100: source 3D + FB
5035 ///4'b0101: source 3D + RFBL
5036 ///4'b0111: 2D to 3D
5037 ///4'b1000: FRC on : controlled by Hal_XC_Enable_FRC_3D_LR_Flag.
5038 if(bEn)
5039 {
5040 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, BIT(11), BIT(11)); //Output 3D L/R selection
5041 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, (bEn<<8), (BIT(8))); //enable Enable free run 3D LR flag: if disable, when image freezed,the output is always L or always R.
5042 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, (bEn<<1), (BIT(1)));//L first,
5043
5044 if(b2DTo3D)
5045 {
5046 if(pXCResourcePrivate->stdrvXC_3D._bFALLRRToFA)//output FA_LLRR for 4k0.5k@240Hz
5047 {
5048 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0x00, BIT(0)|BIT(1));
5049 }
5050 else
5051 {
5052 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
5053 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, BIT(11), (BIT(11)));
5054 }
5055 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, BIT(15), BIT(15));///2Dto3D LR flag enable
5056 }
5057 else
5058 {
5059 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0x00, BIT(0)|BIT(1));
5060 }
5061 }
5062 else
5063 {
5064 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0x0000, BIT(0)|BIT(1)|BIT(11)); //Output 3D L/R selection
5065 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0, (BIT(8))); //enable Enable free run 3D LR flag
5066 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, (BIT(1)));
5067 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, BIT(15));
5068 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0, (BIT(11)));
5069 }
5070 }
5071
Hal_SC_3D_Enable_FRC_LR_Flag(void * pInstance,MS_BOOL bEnable)5072 void Hal_SC_3D_Enable_FRC_LR_Flag(void *pInstance, MS_BOOL bEnable)
5073 {
5074 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5075 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5076 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5077 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5078
5079 //BK20_24[13] = 1: use FRC LR flag, BK20_24[13] = 0: use scaler LR flag
5080 if(bEnable)//FRC 3D enabled
5081 {
5082 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, BIT(13), BIT(13));
5083 }
5084 else
5085 {
5086 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, 0, BIT(13));
5087 }
5088 }
5089
HAL_XC_H3D_OPM_SBYS_PIP_Enable(void * pInstance,MS_BOOL bEn)5090 void HAL_XC_H3D_OPM_SBYS_PIP_Enable(void *pInstance, MS_BOOL bEn)
5091 {
5092 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5093 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5094 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_34_L, (bEn<<7), (BIT(7)));
5095 }
5096
Hal_SC_enable_cursor_report(void * pInstance,MS_BOOL bEn)5097 void Hal_SC_enable_cursor_report(void *pInstance, MS_BOOL bEn)
5098 {
5099 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5100 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5101 if(bEn)
5102 {
5103 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8) | BIT(10), BIT(8) | BIT(10));
5104 }
5105 else
5106 {
5107 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00 , BIT(8) | BIT(10));
5108 }
5109 }
5110
Hal_SC_get_pixel_rgb(void * pInstance,XC_Get_Pixel_RGB * pData)5111 MS_BOOL Hal_SC_get_pixel_rgb(void *pInstance, XC_Get_Pixel_RGB *pData)
5112 {
5113 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5114 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5115 MS_BOOL bret = TRUE;
5116
5117 switch(pData->enStage)
5118 {
5119 case E_XC_GET_PIXEL_STAGE_AFTER_DLC:
5120 //SC_W2BYTEMSK(0, REG_SC_BK0F_46_L, 0x00 , BMASK(3:0));
5121 bret = FALSE;//Not support, Must set to stage C for HW issue
5122 break;
5123 case E_XC_GET_PIXEL_STAGE_PRE_GAMMA:
5124 //SC_W2BYTEMSK(0, REG_SC_BK0F_46_L, 0x08, BMASK(3:0));
5125 bret = FALSE;//Not support, Must set to stage C for HW issue
5126 break;
5127 case E_XC_GET_PIXEL_STAGE_AFTER_OSD:
5128 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, 0x0D, 0xFF);
5129 break;
5130 default:
5131 bret = FALSE;
5132 break;
5133 }
5134 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5135 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5136 if(bret)
5137 {
5138 // Enable
5139 if(!pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear)
5140 {
5141 Hal_SC_enable_cursor_report(pInstance, TRUE);
5142 }
5143
5144 // Initial position (x,y) Set point you want to read.
5145 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_19_L, pData->u16x);
5146 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_1A_L, pData->u16y);
5147
5148 //SW trigger for reading
5149 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, BIT(8), BIT(8));
5150 MsOS_DelayTask(5);
5151 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, 0, BIT(8));
5152 MsOS_DelayTask(32); // Must wait .
5153
5154 pData->u32r = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2D_L);
5155 pData->u32g = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2E_L);
5156 pData->u32b = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2F_L);
5157
5158 // Disable
5159 if(!pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear)
5160 {
5161 Hal_SC_enable_cursor_report(pInstance, FALSE);
5162 }
5163 }
5164 return bret;
5165 }
5166
Hal_SC_SetOPWriteOff(void * pInstance,MS_BOOL bEna)5167 void Hal_SC_SetOPWriteOff(void *pInstance, MS_BOOL bEna)
5168 {
5169 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5170 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5171 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5172 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5173
5174 MS_BOOL u16OldReg = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, BIT(0)));
5175
5176 #if (HW_DESIGN_4K2K_VER == 4)
5177 // For monaco new chip design, only Legacy mode need to control OPW
5178 // If Monaco mode, always keep OPW is on
5179 if ((psXCInstPri->u32DeviceID==0)
5180 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
5181 {
5182 bEna = FALSE;
5183 }
5184 #endif
5185
5186 if(u16OldReg != bEna)
5187 {
5188 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, bEna, BIT(0));//This will stop OPW only, OP memory write request still on
5189 }
5190 }
5191
5192
Hal_SC_GetOPWriteOff(void * pInstance)5193 MS_BOOL Hal_SC_GetOPWriteOff(void *pInstance)
5194 {
5195 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5196 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5197 return (MS_BOOL)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, BIT(0));
5198 }
5199
Hal_SC_Detect_RequestFBL_Mode(void * pInstance)5200 MS_BOOL Hal_SC_Detect_RequestFBL_Mode(void *pInstance)
5201 {
5202 UNUSED(pInstance);
5203 return ENABLE_REQUEST_FBL;
5204 }
5205
Hal_SC_Set_RequestFBL_Mode(void * pInstance,MS_BOOL bEn)5206 MS_BOOL Hal_SC_Set_RequestFBL_Mode(void *pInstance, MS_BOOL bEn)
5207 {
5208 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5209 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5210 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5211 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5212
5213 if(IsSrcTypeDTV(gSrcInfo[MAIN_WINDOW].enInputSourceType) || (IsSrcTypeStorage(gSrcInfo[MAIN_WINDOW].enInputSourceType)))//MVOP source
5214 {
5215 gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode = bEn;
5216
5217 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, bEn?BIT(14):0 , BIT(14)); //reg_short_1line_disable 1:Disable 0:Enable
5218 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_10_L, bEn?(BIT(0)|BIT(2)):0 , BIT(0)|BIT(2)); // Bit0: Enable HSK mode Bit2:reg_ip2_vs_sel 0:ip1 1:mvop
5219
5220 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5D_L, 0x0828 , 0xFFFF);
5221
5222 //this feature conflicts with HSK mode
5223 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_45_L, 0x0000, 0x9FFF); // edclk pd control start and edclk pd control enable
5224 }
5225 else
5226 {
5227 gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode = FALSE;
5228
5229 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, 0x0 , BIT(14)); //reg_short_1line_disable 1:Disable 0:Enable
5230 // Disable HSK mode Bit0 Bit2 Bit5 in no-mvop case
5231 // BIT0: reg_mvop_din_en 1: data is form mvop 0: form yc delay
5232 // BIT2: reg_ip2_vs_sel 1: mvop 0:ip1
5233 // BIT5: reg_ip2_fd_sel 1: use mvop_field 0:use ip1_field
5234 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_10_L, 0x0 , BIT(0)|BIT(2)|BIT(5));
5235 }
5236
5237 #ifdef UFO_XC_HDR
5238 #if (UFO_XC_HDR_VERSION == 2)
5239 if (IsSrcTypeHDMI(gSrcInfo[MAIN_WINDOW].enInputSourceType))
5240 {
5241 // enable hdr dma seamless with rfbl mode on maserati
5242 MApi_XC_W2BYTEMSK(REG_SC_BK79_03_L, 1, BIT(15));
5243 }
5244 #endif
5245 #endif
5246
5247 return ENABLE_REQUEST_FBL;
5248 }
5249
Hal_XC_SetFrameColor(void * pInstance,MS_U32 u32aRGB)5250 void Hal_XC_SetFrameColor(void *pInstance, MS_U32 u32aRGB)
5251 {
5252 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5253 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5254 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, (u32aRGB >> 8),0xFF00); ///< R
5255 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB >> 8),0x00FF); ///< G
5256 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB << 8),0xFF00); ///< B
5257 }
Hal_SC_getVSyncWidth(void * pInstance,SCALER_WIN eWindow)5258 MS_U8 Hal_SC_getVSyncWidth(void *pInstance, SCALER_WIN eWindow)
5259 {
5260 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5261 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5262 MS_U8 u8val = 0;
5263
5264 if(eWindow == MAIN_WINDOW)
5265 {
5266 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_22_L) & 0xFF00) >> 8);
5267 }
5268 else
5269 {
5270 }
5271 return u8val;
5272 }
5273
Hal_SC_Set_OSDLayer(void * pInstance,E_VOP_OSD_LAYER_SEL eVOPOSDLayer,SCALER_WIN eWindow)5274 E_APIXC_ReturnValue Hal_SC_Set_OSDLayer(void *pInstance, E_VOP_OSD_LAYER_SEL eVOPOSDLayer, SCALER_WIN eWindow)
5275 {
5276 return E_APIXC_RET_FAIL;
5277 }
5278
Hal_SC_Get_OSDLayer(void * pInstance,SCALER_WIN eWindow)5279 E_VOP_OSD_LAYER_SEL Hal_SC_Get_OSDLayer(void *pInstance, SCALER_WIN eWindow)
5280 {
5281 //do nothing
5282 return E_VOP_LAYER_RESERVED;
5283 }
5284
Hal_SC_Set_VideoAlpha(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)5285 E_APIXC_ReturnValue Hal_SC_Set_VideoAlpha(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
5286 {
5287 //do nothing
5288 return E_APIXC_RET_FAIL;
5289 }
5290
Hal_SC_Get_VideoAlpha(void * pInstance,MS_U8 * pu8Val,SCALER_WIN eWindow)5291 E_APIXC_ReturnValue Hal_SC_Get_VideoAlpha(void *pInstance, MS_U8 *pu8Val, SCALER_WIN eWindow)
5292 {
5293 *pu8Val += 0;
5294
5295 //do nothing
5296 return E_APIXC_RET_FAIL;
5297 }
5298
Hal_SC_SetOSDBlendingFormula(void * pInstance,E_XC_OSD_INDEX enOsdIndex,E_XC_OSD_BlENDING_TYPE enType,SCALER_WIN eWindow)5299 E_APIXC_ReturnValue Hal_SC_SetOSDBlendingFormula(void *pInstance, E_XC_OSD_INDEX enOsdIndex, E_XC_OSD_BlENDING_TYPE enType, SCALER_WIN eWindow)
5300 {
5301 E_APIXC_ReturnValue bRet = E_APIXC_RET_OK;
5302 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5303 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5304
5305 if (eWindow == MAIN_WINDOW)
5306 {
5307 switch(enOsdIndex)
5308 {
5309 case E_XC_OSD_0:
5310 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
5311 {
5312 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(5)|BIT(4), BIT(5)|BIT(4));
5313 //osd check alpha define
5314 //1: for define 8'hFF is transparent
5315 //0: for define 8'h00 is transparent
5316 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(0), BIT(0));
5317 // for zorder
5318 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, BIT(15), BIT(15));
5319
5320 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5321 #ifdef GOP_SUPPORT_DUALRATE
5322 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_50_L, BIT(10), BIT(10));
5323 #endif
5324 #endif
5325 }
5326 else //a*OSD + (1-a)*Video
5327 {
5328 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(5)|BIT(4));
5329 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(0));
5330 // for zorder
5331 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, 0, BIT(15));
5332
5333 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5334 #ifdef GOP_SUPPORT_DUALRATE
5335 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_50_L, 0, BIT(10));
5336 #endif
5337 #endif
5338 }
5339 break;
5340
5341 case E_XC_OSD_1:
5342 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
5343 {
5344 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(7)|BIT(6), BIT(7)|BIT(6));
5345 //osd check alpha define
5346 //1: for define 8'hFF is transparent
5347 //0: for define 8'h00 is transparent
5348 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(1), BIT(1));
5349 // for zorder
5350 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_60_L, BIT(15), BIT(15));
5351
5352 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5353 #ifdef GOP_SUPPORT_DUALRATE
5354 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_51_L, BIT(10), BIT(10));
5355 #endif
5356 #endif
5357 }
5358 else //a*OSD + (1-a)*Video
5359 {
5360 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(7)|BIT(6));
5361 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(1));
5362 // for zorder
5363 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_60_L, 0, BIT(15));
5364
5365 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5366 #ifdef GOP_SUPPORT_DUALRATE
5367 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_51_L, 0, BIT(10));
5368 #endif
5369 #endif
5370 }
5371 break;
5372
5373 case E_XC_OSD_2:
5374 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
5375 {
5376 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(9)|BIT(8), BIT(9)|BIT(8));
5377 //osd check alpha define
5378 //1: for define 8'hFF is transparent
5379 //0: for define 8'h00 is transparent
5380 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(2), BIT(2));
5381 // for zorder
5382 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_61_L, BIT(15), BIT(15));
5383
5384 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5385 #ifdef GOP_SUPPORT_DUALRATE
5386 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_52_L, BIT(10), BIT(10));
5387 #endif
5388 #endif
5389 }
5390 else //a*OSD + (1-a)*Video
5391 {
5392 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(9)|BIT(8));
5393 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(2));
5394 // for zorder
5395 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_61_L, 0, BIT(15));
5396
5397 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5398 #ifdef GOP_SUPPORT_DUALRATE
5399 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_52_L, 0, BIT(10));
5400 #endif
5401 #endif
5402 }
5403 break;
5404 #if (OSD_LAYER_NUM > 3)
5405 case E_XC_OSD_3:
5406 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
5407 {
5408 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(13)|BIT(12), BIT(13)|BIT(12));
5409 //osd check alpha define
5410 //1: for define 8'hFF is transparent
5411 //0: for define 8'h00 is transparent
5412 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(3), BIT(3));
5413 // for zorder
5414 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_62_L, BIT(15), BIT(15));
5415 }
5416 else //a*OSD + (1-a)*Video
5417 {
5418 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(13)|BIT(12));
5419 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(3));
5420 // for zorder
5421 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_62_L, 0, BIT(15));
5422 }
5423 break;
5424 #endif
5425 #if (OSD_LAYER_NUM > 4)
5426 case E_XC_OSD_4:
5427 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
5428 {
5429 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(15)|BIT(14), BIT(15)|BIT(14));
5430 //osd check alpha define
5431 //1: for define 8'hFF is transparent
5432 //0: for define 8'h00 is transparent
5433 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(4), BIT(4));
5434 // for zorder
5435 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1B_L, BIT(15), BIT(15));
5436 }
5437 else //a*OSD + (1-a)*Video
5438 {
5439 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(15)|BIT(14));
5440 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(4));
5441 // for zorder
5442 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1B_L, 0, BIT(15));
5443 }
5444 break;
5445 #endif
5446 default:
5447 printf("[MDrv_SC_SetOSDBlendingFormula]Invalid Parameter!enOsdIndex=%u\n", enOsdIndex);
5448 bRet = E_APIXC_RET_FAIL_INVALID_PARAMETER;
5449 break;
5450 }
5451 }
5452 else
5453 {
5454 // do nothing
5455 printf("[MDrv_SC_SetOSDBlendingFormula] Not support sub window now \n");
5456 bRet = E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
5457 }
5458
5459 return bRet;
5460 }
Hal_XC_ClearScalingFactorForInternalCalib(void * pInstance)5461 void Hal_XC_ClearScalingFactorForInternalCalib(void *pInstance)
5462 {
5463 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5464 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5465 //MDrv_WriteRegBit(H_BK_SCMI(0x09), FALSE, BIT(7));
5466 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_04_L, 0x0000); // H pre-scaling
5467 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_05_L, 0xC010); // H pre-scaling
5468 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_08_L, 0x0000); // V pre-scaling
5469 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_09_L, 0x0000); // V pre-scaling
5470
5471 //HVSP
5472 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L, 0x0000); // H post-scaling
5473 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_08_L, 0x0100); // H post-scaling
5474 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L, 0x0000); // V post-scaling
5475 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_0A_L, 0x0100); // V post-scaling
5476 }
5477
MHal_SC_cal_usedgain_to_reggain(MS_U32 u16UsedGain_x32)5478 MS_U8 MHal_SC_cal_usedgain_to_reggain(MS_U32 u16UsedGain_x32)
5479 {
5480 MS_U8 u8Value = 0;
5481
5482 if (u16UsedGain_x32 >=65536) u8Value = 16;
5483 else if (u16UsedGain_x32 >=32768) u8Value = 15;
5484 else if (u16UsedGain_x32 >=16384) u8Value = 14;
5485 else if (u16UsedGain_x32 >= 8192) u8Value = 13;
5486 else if (u16UsedGain_x32 >= 4096) u8Value = 12;
5487 else if (u16UsedGain_x32 >= 2048) u8Value = 11;
5488 else if (u16UsedGain_x32 >= 1024) u8Value = 10;
5489 else if (u16UsedGain_x32 >= 512) u8Value = 9;
5490 else if (u16UsedGain_x32 >= 256) u8Value = 8;
5491 else if (u16UsedGain_x32 >= 128) u8Value = 7;
5492 else if (u16UsedGain_x32 >= 64) u8Value = 6;
5493 else if (u16UsedGain_x32 >= 32) u8Value = 5;
5494 else if (u16UsedGain_x32 >= 16) u8Value = 4;
5495 else if (u16UsedGain_x32 >= 8) u8Value = 3;
5496 else if (u16UsedGain_x32 >= 4) u8Value = 2;
5497 else if (u16UsedGain_x32 >= 2) u8Value = 1;
5498 else if (u16UsedGain_x32 >= 1) u8Value = 0;
5499 else {
5500 u8Value = 0;
5501 }
5502
5503 u8Value += IPGAIN_REFACTOR;
5504
5505 return u8Value;
5506 }
5507
Hal_SC_OP2VOPDESel(void * pInstance,E_OP2VOP_DE_SEL eVopDESel)5508 E_APIXC_ReturnValue Hal_SC_OP2VOPDESel(void *pInstance, E_OP2VOP_DE_SEL eVopDESel)
5509 {
5510 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5511 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5512 //Select op2vop de, for DWIN capture etc
5513 if(eVopDESel == E_OP2VOPDE_WHOLEFRAME_WITHOSD)
5514 {
5515 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, ((MS_U16)(E_OP2VOPDE_WHOLEFRAME) << 12), (BIT(12)+BIT(13)));
5516 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(15), BIT(15));
5517 }
5518 else
5519 {
5520 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, 0, BIT(15));
5521 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, (eVopDESel << 12), (BIT(12)+BIT(13)));
5522 }
5523 return E_APIXC_RET_OK;
5524 }
5525
Hal_XC_SVOutput_GetCaps(void * pInstance)5526 MS_BOOL Hal_XC_SVOutput_GetCaps(void *pInstance)
5527 {
5528 return FALSE;
5529 }
5530
5531 /////Add for FRC
_MHal_SC_Flock_Caculate_LPLLSet(MS_U32 u32Dclk)5532 void _MHal_SC_Flock_Caculate_LPLLSet(MS_U32 u32Dclk)
5533 {
5534 #if 0 // Manhattan only 1 LPLL
5535 MS_U64 ldPllSet = 0xff;
5536
5537 ldPllSet = ((MS_U64)320 * 524288 * 10000000 + (u32Dclk>>1)); // LPLL BK01 LPLL Set
5538 do_div(ldPllSet, u32Dclk);
5539
5540 LPLL_BK_STORE;
5541 LPLL_BK_SWITCH(0x01);
5542 W4BYTE(L_BK_LPLL(0x0F), (MS_U32)ldPllSet);
5543 LPLL_BK_RESTORE;
5544 #endif
5545 }
5546
_MHal_SC_Set_LPLL_Limit(MS_U32 u32LpllLimitHigh,MS_U32 u32LpllLimitLow,MS_U8 u8Lpll_bank)5547 void _MHal_SC_Set_LPLL_Limit(MS_U32 u32LpllLimitHigh, MS_U32 u32LpllLimitLow, MS_U8 u8Lpll_bank)
5548 {
5549 //printf("Fpll_Limit: Set %lx, bound (%lx -> %lx)\n", *u32PllSet, u32UpBound, u32LowBound);
5550 LPLL_BK_STORE;
5551 LPLL_BK_SWITCH(u8Lpll_bank);
5552
5553
5554 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit
5555
5556 //printf("Fpll set %lx, limit (high %lx, low %lx)\n", *u32PllSet, u32LpllLimitHigh, u32LpllLimitLow);
5557 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh);
5558 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow);
5559
5560 //printf("Fpll limit reg (high %lx, low %lx)\n", MDrv_Read4Byte(L_BK_LPLL(0x06)), MDrv_Read4Byte(L_BK_LPLL(0x08)));
5561
5562 LPLL_BK_RESTORE;
5563 }
5564 #define LVDS_FRC_CLOCK_MHZ 320
_MHal_SC_Flock_Set_IGainPGain(void * pInstance,MS_U8 u8FRC_Out,MS_U16 u16OutputVfreqAfterFRC,MS_U16 u16Htt,MS_U16 u16Vtt)5565 void _MHal_SC_Flock_Set_IGainPGain(void *pInstance, MS_U8 u8FRC_Out, MS_U16 u16OutputVfreqAfterFRC, MS_U16 u16Htt, MS_U16 u16Vtt)
5566 {
5567 #if 0 // Manhattan only 1 LPLL
5568 MS_U32 u32dclk=0;
5569 MS_U8 u8GainI, u8GainP;
5570 MS_U64 u64Div_Factor;
5571 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5572 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5573 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5574 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5575
5576 //check parameter valid, avoiding the diving zero failure
5577 if(0 == u8FRC_Out)
5578 {
5579 u8FRC_Out = 1;
5580 }
5581
5582 u32dclk = (MS_U32)(u16Vtt * u16Htt * u8FRC_Out);
5583 //u64Div_Factor = (MS_U64)LVDS_FRC_CLOCK_MHZ*524288*1000000/pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock;
5584 u64Div_Factor = (MS_U64)LVDS_FRC_CLOCK_MHZ*524288*1000000;
5585 do_div(u64Div_Factor, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock);
5586 do_div(u64Div_Factor, (MS_U32)u32dclk * 8);
5587
5588 u8GainI = MHal_SC_cal_usedgain_to_reggain(u64Div_Factor);
5589
5590 if((u8FRC_Out == 5)&&(u64Div_Factor==0))
5591 {
5592 //24 to 60Hz, because the SW can't get the real value by log table
5593 u8GainI = 1;
5594
5595 u8GainI += 2;
5596 }
5597
5598 u8GainP = u8GainI+1;
5599 if((u8FRC_Out >= 2) && (u8GainP == u8GainI))
5600 {
5601 u8GainP++;
5602 }
5603
5604 LPLL_BK_STORE;
5605 LPLL_BK_SWITCH(0x01);
5606 MDrv_WriteByte(H_BK_LPLL(0x0B), (u8GainP<<4)|u8GainI); //Gain
5607 LPLL_BK_RESTORE;
5608 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "i_Gain= 0x%tx (%tu)\n", (ptrdiff_t)u64Div_Factor, (ptrdiff_t)u64Div_Factor)
5609 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_IGain= 0x%x (%u)\n", u8GainI, u8GainI)
5610 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_PGain= 0x%x (%u)\n", u8GainP, u8GainP)
5611 #endif
5612 }
5613
5614
_MHal_SC_Flock_Set_LPLL_Enable(E_XC_FLOCK_TYPE eFlock_type)5615 void _MHal_SC_Flock_Set_LPLL_Enable(E_XC_FLOCK_TYPE eFlock_type)
5616 {
5617 #if 0 // Manhattan only 1 LPLL
5618 MS_BOOL bDiv_en = DISABLE;
5619
5620 switch(eFlock_type)
5621 {
5622 case E_XC_FLOCK_DIV_ON:
5623 bDiv_en = ENABLE;
5624 break;
5625
5626 case E_XC_FLOCK_FPLL_ON:
5627 case E_XC_FLOCK_DIV_OFF:
5628 default:
5629 break;
5630 }
5631
5632 LPLL_BK_STORE;
5633 LPLL_BK_SWITCH(0x01);
5634 MDrv_Write2ByteMask(L_BK_LPLL(0x7F), bDiv_en?BIT(8):0, BIT(8));
5635 LPLL_BK_RESTORE;
5636 #endif
5637
5638 }
5639
MHal_CLKGEN_FRC_Init(void * pInstance,MS_U8 u8LPLL_Mode)5640 void MHal_CLKGEN_FRC_Init(void *pInstance,MS_U8 u8LPLL_Mode)
5641 {
5642 //Patch for MSTV_TOOL to R/W FRC base address
5643 MDrv_WriteByte(0x103C0E, 0x02);
5644
5645 // Enable FSC CLK: reg_ckg_fclk_frc_fsc
5646 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x000C); // 345MHz
5647 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0002); // Not Invert
5648 W2BYTEMSK(L_CLKGEN1(0x3B), 0x0000, 0x0001); // Enable clock
5649
5650 // Enable FRC CLK: reg_ckg_fdclk_frc
5651 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0C00); // 172MHz
5652 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert
5653 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock
5654
5655 #if FRC_INSIDE
5656 // Enable CLK_IDCLK_FRC, Reg_ckg_idclk_frc: bk119_02[8]
5657 // Enable CLK_FICLK_FRC, Reg_ckg_ficlk_frc: bk119_02[14]
5658 // Enable CLK_FDCLK_FRC, Reg_ckg_fdclk_frc: bk119_03[8]
5659 // Enable CLK_FOCLK_FRC, Reg_ckg_foclk_frc: bk119_02[6]
5660 // Enable CLK_ODCLK_FRC, Reg_ckg_odclk_frc: bk119_02[0]
5661
5662 W2BYTEMSK(REG_FRC_BK119_02_L, 0x3434, 0x7777);
5663 W2BYTEMSK(REG_FRC_BK119_03_L, 0x0000, 0x0100);
5664 #endif
5665
5666 #if 0 // Move into Panel driver
5667 // Enable CLK_DOT_MINI
5668 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK
5669 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert
5670 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock
5671
5672 // Enable CLK_DOT_MINI_PRE
5673 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK
5674 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert
5675 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock
5676 #endif
5677
5678 #if 0 // Move into panel driver
5679 // Enable CLK_R2_FRC
5680 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz
5681 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert
5682 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock
5683
5684 // Enable CLK_MCU_FRC
5685 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz
5686 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0200); // Not Invert
5687 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0100); // Enable clock
5688
5689 // Enable CLK_ODCLK_FRC
5690 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0C00); // CLK_LPLL
5691 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0200); // Not Invert
5692 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0100); // Enable clock
5693
5694
5695 // Enable CLK_TX_MOD_FRC
5696 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x000C); // clk_odclk_frc
5697 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0002); // Not Invert
5698 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0001); // Enable clock
5699
5700
5701 // Enable CLK_MINIFIFO_FRC
5702 if (u8LPLL_Mode== E_XC_MOD_OUTPUT_SINGLE ) //0: single, 1: dual
5703 {
5704 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0C00); // CLK_LPLL
5705 }
5706 else
5707 {
5708 W2BYTEMSK(L_CLKGEN1(0x32), 0x0800, 0x0C00); // CLK_LPLL_div2
5709 }
5710 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0200); // Not Invert
5711 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0100); // Enable clock
5712
5713
5714 // Enable CLK_MISC_FRC
5715 if (u8LPLL_Mode == E_XC_MOD_OUTPUT_SINGLE)
5716 {
5717 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0C00); // CLK_LPLL
5718 }
5719 else
5720 {
5721 W2BYTEMSK(L_CLKGEN1(0x33), 0x0400, 0x0C00); // CLK_LPLL_div2
5722 }
5723
5724 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0200); // Not Invert
5725 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0100); // Enable clock
5726
5727
5728
5729 // Enable CLK_MFT_FRC
5730 W2BYTEMSK(L_CLKGEN1(0x34), 0x0008, 0x000C); // CLK_LPLL_div2
5731 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0002); // Not Invert
5732 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0001); // Enable clock
5733
5734 // Enable CLK_FDCLK_FRC
5735 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x1C00); // 172 MHz
5736 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert
5737 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock
5738
5739 // Enable CLK_ICLK_FRC
5740 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0004); // clk_fdclk_frc
5741 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0002); // Not Invert
5742 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0001); // Enable clock
5743
5744 // Enable CLK_OP2_SRAM_FRC
5745 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0004); // clk_odclk_frc_p
5746 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0002); // Not Invert
5747 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0001); // Enable clock
5748
5749 // Enable CLK_LD_SRAM_FRC
5750 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0400); // clk_odclk_frc_p
5751 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0200); // Not Invert
5752 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0100); // Enable clock
5753
5754 // Enable CLK_OD_SRAM_FRC
5755 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0004); // clk_odclk_frc_p
5756 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0002); // Not Invert
5757 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0001); // Enable clock
5758
5759 // Enable CLK_LPLL_FRC
5760 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x000C); // CLK_LPLL
5761 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0002); // Not Invert
5762 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0001); // Enable clock
5763
5764 // Enable CLK_OCC_FRC
5765 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0C00); // flock_clk_synth_out
5766 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0200); // Not Invert
5767 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0100); // Enable clock
5768 #endif
5769 // Enable LVDS_MPLL
5770 //[10]reg_lvds_mpll_clk_adc432m_pd, [8]reg_lvds_mpll_pd
5771 //W2BYTEMSK(L_BK_AFEC(0x41), 0x0000, 0x0500); // MPLL_CLK_DP432M
5772 }
5773
MHal_CLKGEN_FRC_Bypass_Enable(MS_BOOL bEnable)5774 void MHal_CLKGEN_FRC_Bypass_Enable(MS_BOOL bEnable)
5775 {
5776
5777 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert
5778 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock
5779
5780 if (bEnable)
5781 {
5782 // Enable CLK_ODCLK
5783 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock
5784 // Disable CLK_R2_FRC
5785 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0xFFFF); // turn-on clk_mcu_frc
5786 // Enable CLK_SPI_M_FRC
5787 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Disable clock
5788 }
5789 else
5790 {
5791 // Enable CLK_ODCLK
5792 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out
5793 // Enable CLK_R2_FRC
5794 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x0C); // 216 MHz
5795 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x02); // Not Invert
5796 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x01); // Enable clock
5797 // Enable CLK_SPI_M_FRC
5798 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x1C); // 27 MHz
5799 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x02); // Not Invert
5800 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Enable clock
5801 }
5802 }
5803
5804
Hal_XC_IsForcePrescaling(void * pInstance,const XC_InternalStatus * pSrcInfo,MS_BOOL * pbForceV,MS_BOOL * pbForceH,SCALER_WIN eWindow)5805 E_APIXC_ReturnValue Hal_XC_IsForcePrescaling(void *pInstance, const XC_InternalStatus *pSrcInfo, MS_BOOL *pbForceV, MS_BOOL *pbForceH, SCALER_WIN eWindow)
5806 {
5807 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5808 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5809 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5810 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5811 *pbForceV = FALSE;
5812 *pbForceH = FALSE;
5813
5814 //-----------------------------------------
5815 // Vertical
5816 //-----------------------------------------
5817
5818 //FHD case. FHD has tight bandwidth in FCLK (post scaling), so force pre-scaling if disp.v size > 80% of crop.v size.
5819 if ( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1000) &&
5820 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 1600) ) //consider 1680x1050 into this case
5821 {
5822 // 80%
5823 if ( ( pSrcInfo->stDispWin.height * 10 ) < ( pSrcInfo->stCropWin.height * 8 ) )
5824 {
5825 *pbForceV = TRUE;
5826 }
5827 }
5828 else // SD, HD panel.
5829 {
5830 // 60%
5831 if ( ( pSrcInfo->stDispWin.height * 10 ) < ( pSrcInfo->stCropWin.height * 6 ) )
5832 {
5833 *pbForceV = TRUE;
5834 }
5835 }
5836
5837 //-----------------------------------------
5838 // Horizontal
5839 //-----------------------------------------
5840
5841 if ( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1000)
5842 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 1600) ) //consider 1680x1050 into this case
5843 {
5844 // 80% ( SEC using 80% for HD panel ). Increase % if meet FCLK bandwidth issue in the future.
5845 if ( ( pSrcInfo->stDispWin.width * 10 ) < ( pSrcInfo->stCropWin.width * 8 ) )
5846 {
5847 *pbForceH = TRUE;
5848 }
5849 }
5850 else // SD panel.
5851 {
5852 // 60%
5853 if ( ( pSrcInfo->stDispWin.width * 10 ) < ( pSrcInfo->stCropWin.width * 6 ) )
5854 {
5855 *pbForceH = TRUE;
5856 }
5857 }
5858
5859 if (psXCInstPri->u32DeviceID == 1)
5860 {
5861 // SC1 attach sc0, postscaling down performance not enough
5862 if ( ( pSrcInfo->stDispWin.height ) < ( pSrcInfo->stCropWin.height) )
5863 {
5864 *pbForceV = TRUE;
5865 }
5866 if ( ( pSrcInfo->stDispWin.width) < ( pSrcInfo->stCropWin.width) )
5867 {
5868 *pbForceH = TRUE;
5869 }
5870 }
5871
5872 return E_APIXC_RET_OK;
5873 }
5874
Hal_SC_IsHW2Dto3DPatch_Enable(void)5875 MS_BOOL Hal_SC_IsHW2Dto3DPatch_Enable(void)
5876 {
5877 MS_BOOL bRet = FALSE;
5878 if(PM_R1BYTE(REG_CHIP_REVISION, 7:0) < 1)//a1 u01 2d to 3d hw bug
5879 {
5880 bRet = TRUE;
5881 }
5882 return bRet;
5883 }
5884
MHal_SC_Get_LpllSet_Factor(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)5885 MS_U32 MHal_SC_Get_LpllSet_Factor(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)
5886 {
5887 MS_U32 u32Factor = 0;
5888 UNUSED(u8LPLL_Type);
5889 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5890 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5891 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5892 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5893
5894 u32Factor = LPLL_LOOPGAIN/8/2;
5895
5896 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal> 3000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
5897 {
5898 //printf("\033[0;31m [%s][%d] enter For 4K2K used!!! \033[0m\n", __FUNCTION__, __LINE__);
5899 u32Factor = 1;
5900 }
5901
5902 if (u8LPLL_Type == E_XC_PNL_LPLL_LVDS)
5903 {
5904 u32Factor = 3;
5905 }
5906
5907 // for the WUXGA 1920x1200 case
5908 if((u8LPLL_Mode==E_XC_MOD_OUTPUT_DUAL)&&(u32DefaultDClk > 1500000000)
5909 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1100)
5910 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width < 2000))
5911 {
5912 u32Factor = LPLL_LOOPGAIN/8;
5913 }
5914
5915 if((u8LPLL_Type >= E_XC_PNL_LPLL_VBY1_10BIT_4LANE)&&(u8LPLL_Type <= E_XC_PNL_LPLL_VBY1_8BIT_8LANE))
5916 {
5917 u32Factor = 1;
5918 }
5919
5920 return u32Factor;
5921 }
5922
MHal_SC_Get_LpllSet_Div(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)5923 MS_U32 MHal_SC_Get_LpllSet_Div(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)
5924 {
5925 MS_U32 u32Div = 1;
5926
5927 if (u8LPLL_Type == E_XC_PNL_LPLL_LVDS)
5928 {
5929 u32Div = 2;
5930 }
5931
5932 return u32Div;
5933 }
5934
Hal_SC_Enable_AVMute(void * pInstance,SCALER_WIN eWindow)5935 E_APIXC_ReturnValue Hal_SC_Enable_AVMute(void *pInstance, SCALER_WIN eWindow)
5936 {
5937 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5938 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5939 if (eWindow == MAIN_WINDOW)
5940 {
5941 //HDMI V-mute detect enable
5942 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_34_L, BIT(9), BIT(9));
5943 //force IPM enable at av-mute case
5944 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L, BIT(5), BIT(5));
5945 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_19_L, BIT(5), BIT(5));
5946
5947 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, BIT(13) | BIT(15), BIT(13) | BIT(15));
5948 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5949 // SC1 as subwindow case, use bank25_2E to back main window,HW bug fix after manhattan U02
5950 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, BIT(2), BIT(2));
5951 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(9) | BIT(11), BIT(9) | BIT(11));
5952 #else
5953 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(9) | BIT(11), BIT(9) | BIT(11));
5954 #endif
5955 }
5956 else
5957 {
5958 //HDMI V-mute detect enable
5959 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_34_L, BIT(9), BIT(9));
5960 //force IPM enable at av-mute case
5961 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L, BIT(5), BIT(5));
5962 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_59_L, BIT(5), BIT(5));
5963
5964 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, BIT(12) | BIT(14), BIT(12) | BIT(14));
5965 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(8) | BIT(10), BIT(8) | BIT(10));
5966 }
5967
5968 return E_APIXC_RET_OK;
5969 }
5970
Hal_XC_ReportPixelInfo(void * pInstance,MS_XC_REPORT_PIXELINFO * pstRepPixInfo)5971 MS_BOOL Hal_XC_ReportPixelInfo(void *pInstance, MS_XC_REPORT_PIXELINFO *pstRepPixInfo)
5972 {
5973 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5974 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5975 MS_BOOL bret = TRUE;
5976
5977 switch(pstRepPixInfo->enStage)
5978 {
5979 case E_XC_GET_PIXEL_STAGE_AFTER_DLC:
5980 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x00 , BMASK(3:0));
5981 break;
5982 case E_XC_GET_PIXEL_STAGE_PRE_GAMMA:
5983 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x08, BMASK(3:0));
5984 break;
5985 case E_XC_GET_PIXEL_STAGE_AFTER_OSD:
5986 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x0C, BMASK(3:0));
5987 break;
5988 default:
5989 bret = FALSE;
5990 break;
5991 }
5992
5993 if(bret)
5994 {
5995 // Enable
5996 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8), BIT(8));
5997
5998 if(pstRepPixInfo->bShowRepWin)
5999 {
6000 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(9), BIT(9));
6001 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, pstRepPixInfo->u16RepWinColor<<8, 0xFF00);
6002 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, BIT(0), BIT(0));
6003 }
6004
6005 // Set Report Window
6006 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L, pstRepPixInfo->u16XStart);
6007 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L, pstRepPixInfo->u16XEnd);
6008 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L, pstRepPixInfo->u16YStart);
6009 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L, pstRepPixInfo->u16YEnd);
6010
6011 MsOS_DelayTask(50); // Must wait .
6012
6013 pstRepPixInfo->u16RCrMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_64_L);
6014 pstRepPixInfo->u16RCrMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_65_L);
6015 pstRepPixInfo->u16GYMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_66_L);
6016 pstRepPixInfo->u16GYMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_67_L);
6017 pstRepPixInfo->u16BCbMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_68_L);
6018 pstRepPixInfo->u16BCbMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_69_L);
6019 pstRepPixInfo->u32RCrSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_01_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_02_L)<<16);
6020 pstRepPixInfo->u32GYSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_03_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_04_L)<<16);
6021 pstRepPixInfo->u32BCbSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_05_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_06_L)<<16);
6022
6023 if(pstRepPixInfo->bShowRepWin)
6024 {
6025 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, 0x00, BIT(0));
6026 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00, BIT(9));
6027 }
6028 // Disable
6029 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00, BIT(8));
6030 }
6031
6032 return bret;
6033 }
6034
Hal_SC_set_mrq_miusel(void * pInstance,MS_U8 u8MIUSel)6035 void Hal_SC_set_mrq_miusel(void *pInstance, MS_U8 u8MIUSel)
6036 {
6037 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6038 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6039
6040 // Scaler control MRQ MIU by itself
6041 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
6042 if (u8MIUSel==0)
6043 {
6044 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, 0, BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU0
6045 }
6046 else if (u8MIUSel==1)
6047 {
6048 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, BIT(8), BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU1
6049 }
6050 else if (u8MIUSel==2)
6051 {
6052 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, BIT(9), BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU2
6053 }
6054
6055 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x80); // MIU select (Group1 BIT15)
6056 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select
6057 }
6058
Hal_SC_get_mcdi_memoryaddressfromreg(void * pInstance,E_XC_MCDI_TYPE eType)6059 MS_PHY Hal_SC_get_mcdi_memoryaddressfromreg(void *pInstance, E_XC_MCDI_TYPE eType)
6060 {
6061 MS_PHY phyFBAddressTemp = 0;
6062 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6063 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6064
6065 if (eType == E_XC_MCDI_BOTH) // MAIN
6066 {
6067 phyFBAddressTemp = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L) * MCDI_BYTE_PER_WORD;
6068 }
6069 else if(eType == E_XC_MCDI_SUB_BOTH) // SUB
6070 {
6071 phyFBAddressTemp = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L) * MCDI_BYTE_PER_WORD;
6072 }
6073 else if(eType == E_XC_MCDI_ME1)
6074 {
6075 phyFBAddressTemp = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L) * MCDI_BYTE_PER_WORD; // MAIN ME1 address
6076 }
6077 else if (eType == E_XC_MCDI_ME2)
6078 {
6079 phyFBAddressTemp = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L) * MCDI_BYTE_PER_WORD; // MAIN ME2 address
6080 }
6081 else if (eType == E_XC_MCDI_SUB_ME1)
6082 {
6083 phyFBAddressTemp = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L) * MCDI_BYTE_PER_WORD; // SUB ME1 address
6084 }
6085 else if (eType == E_XC_MCDI_SUB_ME2)
6086 {
6087 phyFBAddressTemp = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L) * MCDI_BYTE_PER_WORD; // SUB ME2 address
6088 }
6089
6090 return phyFBAddressTemp;
6091 }
6092
Hal_SC_set_mcdi_memoryaddress(void * pInstance,MS_PHY u32FBAddress,E_XC_MCDI_TYPE eType)6093 void Hal_SC_set_mcdi_memoryaddress(void *pInstance, MS_PHY u32FBAddress, E_XC_MCDI_TYPE eType)
6094 {
6095 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6096 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6097
6098 if (eType == E_XC_MCDI_BOTH) // MAIN
6099 {
6100 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME1 address
6101 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME2 address
6102 }
6103 else if(eType == E_XC_MCDI_SUB_BOTH) // SUB
6104 {
6105 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME1 address
6106 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME2 address
6107 }
6108 else if(eType == E_XC_MCDI_ME1)
6109 {
6110 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME1 address
6111 }
6112 else if (eType == E_XC_MCDI_ME2)
6113 {
6114 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME2 address
6115 }
6116 else if (eType == E_XC_MCDI_SUB_ME1)
6117 {
6118 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME1 address
6119 }
6120 else if (eType == E_XC_MCDI_SUB_ME2)
6121 {
6122 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME2 address
6123 }
6124 }
6125
Hal_SC_set_mcdi_write_limit(void * pInstance,MS_BOOL bEn,MS_PHY u32LimitAddress,E_XC_MCDI_TYPE eType)6126 void Hal_SC_set_mcdi_write_limit(void *pInstance, MS_BOOL bEn, MS_PHY u32LimitAddress, E_XC_MCDI_TYPE eType)
6127 {
6128 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6129 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6130
6131 u32LimitAddress = u32LimitAddress / MCDI_BYTE_PER_WORD -1;
6132
6133 if(eType == E_XC_MCDI_BOTH)
6134 {
6135 // Main/Sub shares the same enable bit of ME1
6136 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6137 // Bit 0 ~ 26
6138 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0C_L, u32LimitAddress & 0xFFFF);
6139 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0D_L, (u32LimitAddress >> 16) & 0x3FF);
6140
6141 // Main/Sub shares the same enable bit of ME2
6142 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6143 // Bit 0 ~ 26
6144 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_14_L, u32LimitAddress & 0xFFFF);
6145 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_15_L, (u32LimitAddress >> 16) & 0x3FF);
6146 }
6147 else if(eType==E_XC_MCDI_SUB_BOTH)
6148 {
6149 // Main/Sub shares the same enable bit of ME1
6150 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6151 // Bit 0 ~ 26
6152 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2A_L, u32LimitAddress & 0xFFFF);
6153 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2B_L, (u32LimitAddress >> 16) & 0x3FF);
6154
6155 // Main/Sub shares the same enable bit of ME2
6156 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6157 // Bit 0 ~ 26
6158 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2E_L, u32LimitAddress & 0xFFFF);
6159 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2F_L, (u32LimitAddress >> 16) & 0x3FF);
6160 }
6161 else if(eType == E_XC_MCDI_ME1)
6162 {
6163 // Main/Sub shares the same enable bit
6164 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6165 // Bit 0 ~ 26
6166 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0C_L, u32LimitAddress & 0xFFFF);
6167 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0D_L, (u32LimitAddress >> 16) & 0x3FF);
6168 }
6169 else if (eType == E_XC_MCDI_ME2)
6170 {
6171 // Main/Sub shares the same enable bit
6172 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6173 // Bit 0 ~ 26
6174 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_14_L, u32LimitAddress & 0xFFFF);
6175 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_15_L, (u32LimitAddress >> 16) & 0x3FF);
6176 }
6177 else if (eType == E_XC_MCDI_SUB_ME1)
6178 {
6179 // Main/Sub shares the same enable bit
6180 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
6181 // Bit 0 ~ 26
6182 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2A_L, u32LimitAddress & 0xFFFF);
6183 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2B_L, (u32LimitAddress >> 16) & 0x3FF);
6184 }
6185 else if (eType == E_XC_MCDI_SUB_ME2)
6186 {
6187 // Main/Sub shares the same enable bit
6188 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
6189 // Bit 0 ~ 26
6190 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2E_L, u32LimitAddress & 0xFFFF);
6191 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2F_L, (u32LimitAddress >> 16) & 0x3FF);
6192 }
6193 }
Hal_SC_enable_mcdi(void * pInstance,MS_BOOL bEn,E_XC_MCDI_TYPE eType)6194 void Hal_SC_enable_mcdi(void *pInstance, MS_BOOL bEn, E_XC_MCDI_TYPE eType)
6195 {
6196 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6197 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6198
6199 #define ME1_CTRL_BIT ( BIT(1) )
6200 #define ME2_CTRL_BIT ( BIT(2) )
6201 MS_U16 u16Value = 0;
6202 MS_U16 u16Mask = 0;
6203 switch (eType)
6204 {
6205 case E_XC_MCDI_ME1:
6206 u16Value = u16Value | (bEn ? 0 : ME1_CTRL_BIT);
6207 u16Mask = ME1_CTRL_BIT;
6208 break;
6209 case E_XC_MCDI_ME2:
6210 u16Value = u16Value | (bEn ? 0 : ME2_CTRL_BIT);
6211 u16Mask = ME2_CTRL_BIT;
6212 break;
6213 case E_XC_MCDI_BOTH:
6214 u16Value = u16Value | (bEn ? 0 : ME1_CTRL_BIT);
6215 u16Value = u16Value | (bEn ? 0 : ME2_CTRL_BIT);
6216 u16Mask = ME1_CTRL_BIT | ME2_CTRL_BIT;
6217 break;
6218 case E_XC_MCDI_SUB_ME1:
6219 u16Value = u16Value | ((bEn ? 0 : ME1_CTRL_BIT)<<3);
6220 u16Mask = ME1_CTRL_BIT << 3;
6221 break;
6222 case E_XC_MCDI_SUB_ME2:
6223 u16Value = u16Value | ((bEn ? 0 : ME2_CTRL_BIT)<<3);
6224 u16Mask = ME2_CTRL_BIT << 3;
6225 break;
6226 case E_XC_MCDI_SUB_BOTH:
6227 u16Value = u16Value | ((bEn ? 0 : ME1_CTRL_BIT)<<3);
6228 u16Value = u16Value | ((bEn ? 0 : ME2_CTRL_BIT)<<3);
6229 u16Mask = (ME1_CTRL_BIT | ME2_CTRL_BIT)<<3;
6230 break;
6231 default:
6232 u16Value = 0;
6233 break;
6234 }
6235 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L, u16Value, u16Mask);
6236 if (bEn)
6237 {
6238 // Turn on MIU access arbitor
6239 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_04_L, 0x00 , BIT(6) );
6240 }
6241 else
6242 {
6243 MS_U16 u16MCDiCtrl_Main = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L) & ( ME1_CTRL_BIT | ME2_CTRL_BIT ) ;
6244 MS_U16 u16MCDiCtrl_Sub = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L) & (( ME1_CTRL_BIT | ME2_CTRL_BIT )<<3) ;
6245 MS_U16 u16MCDiCtrl = u16MCDiCtrl_Main | u16MCDiCtrl_Sub;
6246 // Current ME1/2 is turned off
6247 if ( u16MCDiCtrl == ( ( ME1_CTRL_BIT | ME2_CTRL_BIT) // Main_Window
6248 | ((ME1_CTRL_BIT | ME2_CTRL_BIT)<<3))) // Sub_Window
6249 {
6250 // Turn off arbitor only when all MCDi function is off.
6251 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_04_L, BIT(6) , BIT(6) );
6252 }
6253 }
6254 }
6255
6256 /// bandwidth saving Mode
Hal_SC_set_bws_mode(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6257 void Hal_SC_set_bws_mode(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6258 {
6259 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6260 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6261
6262 if(eWindow == MAIN_WINDOW)
6263 {
6264 //ipm Main
6265 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, (bEnable? 0x00:BIT(0)), BIT(0));
6266 }
6267 else
6268 {
6269 //ipm Sub
6270 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, (bEnable? 0x00:BIT(1)), BIT(1));
6271 }
6272 }
6273
Hal_SC_sw_lcnt_en(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6274 void Hal_SC_sw_lcnt_en(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6275 {
6276 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6277 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6278
6279 if(eWindow == MAIN_WINDOW)
6280 {
6281 //ipm Main
6282 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_11_L, (bEnable? BIT(0):0x00), BIT(0));
6283 }
6284 else
6285 {
6286 //ipm Sub
6287 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_21_L, (bEnable? BIT(0):0x00), BIT(0));
6288 }
6289 }
6290
Hal_SC_set_sw_lcnt(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6291 void Hal_SC_set_sw_lcnt(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6292 {
6293 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6294 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6295
6296 if(eWindow == MAIN_WINDOW)
6297 {
6298 //ipm Main
6299 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_11_L, (bEnable? BIT(1):0x00), BIT(1));
6300 }
6301 else
6302 {
6303 //ipm Sub
6304 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_21_L, (bEnable? BIT(1):0x00), BIT(1));
6305 }
6306 }
6307
Hal_SC_set_ipmw_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6308 void Hal_SC_set_ipmw_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6309 {
6310 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6311 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6312
6313 if(eWindow == MAIN_WINDOW)
6314 {
6315 //ipm Main
6316 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_12_L, (bEnable? BIT(4):0x00), BIT(4));
6317 }
6318 else
6319 {
6320 //ipm Sub
6321 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_22_L, (bEnable? BIT(4):0x00), BIT(4));
6322 }
6323 }
6324
Hal_SC_set_ipmr_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6325 void Hal_SC_set_ipmr_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6326 {
6327 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6328 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6329
6330 if(eWindow == MAIN_WINDOW)
6331 {
6332 //ipm Main
6333 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_12_L, (bEnable? BIT(12):0x00), BIT(12));
6334 }
6335 else
6336 {
6337 //ipm Sub
6338 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_22_L, (bEnable? BIT(12):0x00), BIT(12));
6339 }
6340 }
6341
Hal_SC_set_opm_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6342 void Hal_SC_set_opm_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6343 {
6344 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6345 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6346 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6347 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6348
6349 if(eWindow == MAIN_WINDOW)
6350 {
6351 //opm Main
6352 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, (bEnable? BIT(5):0x00), BIT(5));
6353 }
6354 else
6355 {
6356 //opm Sub
6357 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, (bEnable? BIT(4):0x00), BIT(4));
6358 }
6359
6360 }
6361
MHal_XC_Calc_IGainPGain(void * pInstance,MS_U8 * u8GainI,MS_U8 * u8GainP,MS_U32 u32XTAL_Clock,MS_U8 u8LGain,MS_U8 u8Vco,MS_U16 u16HTotal,MS_U16 u16VTotal,MS_U8 u8FRC_Out)6362 void MHal_XC_Calc_IGainPGain(void *pInstance, MS_U8 *u8GainI, MS_U8 *u8GainP, MS_U32 u32XTAL_Clock, MS_U8 u8LGain, MS_U8 u8Vco, MS_U16 u16HTotal, MS_U16 u16VTotal, MS_U8 u8FRC_Out)
6363 {
6364 MS_U32 u32Factor, u32Temp;
6365 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6366 UtopiaResourceGetPrivate(g_pXCResource[E_XC_POOL_ID_INTERNAL_VARIABLE],(void**)(&pXCResourcePrivate));
6367 u32Temp = (MS_U32)(u16VTotal*u16HTotal*u8FRC_Out);
6368 u32XTAL_Clock*=2;
6369 u32Factor = ((LVDS_MPLL_CLOCK_MHZ*1000000UL/u32XTAL_Clock)*524288*u8LGain)/((MS_U32)(u32Temp*u8Vco/2*8));
6370
6371 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MM=%ld,u8LGain1=%d,Htt=%d,Vtt=%d,Ovs=%d,Vco=%d,i_gain=%td,REGIg=%d,u32XTAL_Clock=%tu\n",
6372 (LVDS_MPLL_CLOCK_MHZ*1000000UL/pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock),u8LGain,
6373 u16HTotal,u16VTotal,u8FRC_Out,u8Vco/2,(ptrdiff_t)u32Factor,MHal_SC_cal_usedgain_to_reggain(u32Factor),(ptrdiff_t)u32XTAL_Clock);
6374
6375 *u8GainI = MHal_SC_cal_usedgain_to_reggain(u32Factor);
6376 /// for high accurate log value
6377 u32Factor = ((LVDS_MPLL_CLOCK_MHZ*1000000UL/u32XTAL_Clock)*524288*u8LGain*10)/((MS_U32)(u32Temp*u8Vco/2*8));
6378
6379 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "new i_gain=%td\n", (ptrdiff_t)u32Factor);
6380
6381 if(u32Factor <= 1)
6382 *u8GainI=2;
6383 else if(u32Factor <= 3)
6384 *u8GainI=3;
6385 else if(u32Factor <= 7)
6386 *u8GainI=4;
6387
6388 *u8GainP = *u8GainI+1;
6389
6390 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "==>LG1=%d,iGain=%td,I=%d,P=%d\n",u8LGain,(ptrdiff_t)u32Factor,*u8GainI,*u8GainP);
6391 }
6392
MHAL_SC_set_osdc_tgen_hsync_start(void * pInstance,MS_U16 u16Value)6393 void MHAL_SC_set_osdc_tgen_hsync_start(void *pInstance, MS_U16 u16Value)
6394 {
6395 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6396 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6397
6398 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_01_L, u16Value, 0x1FFF);
6399 }
6400
MHAL_SC_set_osdc_tgen_hsync_end(void * pInstance,MS_U16 u16Value)6401 void MHAL_SC_set_osdc_tgen_hsync_end(void *pInstance, MS_U16 u16Value)
6402 {
6403 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6404 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6405
6406 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_02_L, u16Value, 0x1FFF);
6407 }
6408
MHAL_SC_set_osdc_tgen_hframe_de_start(void * pInstance,MS_U16 u16Value)6409 void MHAL_SC_set_osdc_tgen_hframe_de_start(void *pInstance, MS_U16 u16Value)
6410 {
6411 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6412 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6413
6414 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_03_L, u16Value, 0x1FFF);
6415 }
6416
MHAL_SC_set_osdc_tgen_hframe_de_end(void * pInstance,MS_U16 u16Value)6417 void MHAL_SC_set_osdc_tgen_hframe_de_end(void *pInstance, MS_U16 u16Value)
6418 {
6419 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6420 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6421
6422 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_04_L, u16Value, 0x1FFF);
6423 }
6424
MHAL_SC_set_osdc_tgen_htotal(void * pInstance,MS_U16 u16Value)6425 void MHAL_SC_set_osdc_tgen_htotal(void *pInstance, MS_U16 u16Value)
6426 {
6427 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6428 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6429
6430 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_05_L, u16Value, 0x1FFF);
6431 }
6432
MHAL_SC_set_osdc_tgen_vtotal(void * pInstance,MS_U16 u16Value)6433 void MHAL_SC_set_osdc_tgen_vtotal(void *pInstance, MS_U16 u16Value)
6434 {
6435 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6436 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6437
6438 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_07_L, u16Value, 0x1FFF);
6439 }
6440
MHAL_SC_set_osdc_tgen_vframe_de_start(void * pInstance,MS_U16 u16Value)6441 void MHAL_SC_set_osdc_tgen_vframe_de_start(void *pInstance, MS_U16 u16Value)
6442 {
6443 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6444 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6445
6446 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0A_L, u16Value, 0x1FFF);
6447 }
6448
MHAL_SC_set_osdc_tgen_vframe_de_end(void * pInstance,MS_U16 u16Value)6449 void MHAL_SC_set_osdc_tgen_vframe_de_end(void *pInstance, MS_U16 u16Value)
6450 {
6451 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6452 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6453
6454 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0B_L, u16Value, 0x1FFF);
6455 }
6456
MHAL_SC_set_osdc_tgen_vsync_start(void * pInstance,MS_U16 u16Value)6457 void MHAL_SC_set_osdc_tgen_vsync_start(void *pInstance, MS_U16 u16Value)
6458 {
6459 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6460 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6461
6462 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0E_L, u16Value, 0x1FFF);
6463 }
6464
MHAL_SC_set_osdc_tgen_vsync_end(void * pInstance,MS_U16 u16Value)6465 void MHAL_SC_set_osdc_tgen_vsync_end(void *pInstance, MS_U16 u16Value)
6466 {
6467 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6468 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6469
6470 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0F_L, u16Value, 0x1FFF);
6471 }
6472
MHAL_SC_set_osdc_tgen_reset_enable(void * pInstance,MS_BOOL bEnable)6473 void MHAL_SC_set_osdc_tgen_reset_enable(void *pInstance, MS_BOOL bEnable)
6474 {
6475 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6476 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6477
6478 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_20_L, bEnable?BIT(0):0x00, BIT(0));
6479 }
6480
MHAL_SC_set_osdc_swreset_enable(void * pInstance,MS_BOOL bEnable)6481 void MHAL_SC_set_osdc_swreset_enable(void *pInstance, MS_BOOL bEnable)
6482 {
6483 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6484 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6485
6486 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_21_L, bEnable?BIT(0):0x00, BIT(0));
6487 }
6488
MHAL_SC_set_osdc_mixer_bypass_enable(void * pInstance,MS_BOOL bEnable)6489 void MHAL_SC_set_osdc_mixer_bypass_enable(void *pInstance, MS_BOOL bEnable)
6490 {
6491 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6492 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6493
6494 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(0):0x00, BIT(0));
6495 }
6496
MHAL_SC_set_osdc_mixer_inv_alpha_enable(void * pInstance,MS_BOOL bEnable)6497 void MHAL_SC_set_osdc_mixer_inv_alpha_enable(void *pInstance, MS_BOOL bEnable)
6498 {
6499 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6500 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6501
6502 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(1):0x00, BIT(1));
6503 }
6504 //1:hs_out = hs&vfde
MHAL_SC_set_osdc_mixer_hs_n_vfde_enable(void * pInstance,MS_BOOL bEnable)6505 void MHAL_SC_set_osdc_mixer_hs_n_vfde_enable(void *pInstance, MS_BOOL bEnable)
6506 {
6507 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6508 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6509
6510 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(2):0x00, BIT(2));
6511 }
6512 //1:de(hfde)_out = de(hfde)&vfde
MHAL_SC_set_osdc_mixer_hfde_n_vfde_enable(void * pInstance,MS_BOOL bEnable)6513 void MHAL_SC_set_osdc_mixer_hfde_n_vfde_enable(void *pInstance, MS_BOOL bEnable)
6514 {
6515 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6516 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6517
6518 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(3):0x00, BIT(3));
6519 }
6520
MHAL_SC_set_osdc_clk_mux(void * pInstance,MS_U8 u8Clk_Mux)6521 void MHAL_SC_set_osdc_clk_mux(void *pInstance, MS_U8 u8Clk_Mux)
6522 {
6523 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK);
6524 }
6525
MHAL_SC_enable_osdc(void * pInstance,MS_BOOL bEnable)6526 void MHAL_SC_enable_osdc(void *pInstance, MS_BOOL bEnable)
6527 {
6528 // Enable OSDC LPLL
6529 if(bEnable)
6530 {
6531 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert
6532 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock
6533 }
6534 else
6535 {
6536 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert
6537 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock
6538 }
6539 }
6540
MHAL_SC_get_osdc_tgen_hsync_start(void * pInstance)6541 MS_U16 MHAL_SC_get_osdc_tgen_hsync_start(void *pInstance)
6542 {
6543 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6544 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6545
6546 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_01_L, 0x1FFF);
6547 }
6548
MHAL_SC_get_osdc_tgen_hsync_end(void * pInstance)6549 MS_U16 MHAL_SC_get_osdc_tgen_hsync_end(void *pInstance)
6550 {
6551 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6552 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6553
6554 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_02_L, 0x1FFF);
6555 }
6556
MHAL_SC_get_osdc_tgen_hframe_de_start(void * pInstance)6557 MS_U16 MHAL_SC_get_osdc_tgen_hframe_de_start(void *pInstance)
6558 {
6559 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6560 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6561
6562 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_03_L, 0x1FFF);
6563 }
6564
MHAL_SC_get_osdc_tgen_hframe_de_end(void * pInstance)6565 MS_U16 MHAL_SC_get_osdc_tgen_hframe_de_end(void *pInstance)
6566 {
6567 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6568 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6569
6570 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_04_L, 0x1FFF);
6571 }
6572
MHAL_SC_get_osdc_tgen_htotal(void * pInstance)6573 MS_U16 MHAL_SC_get_osdc_tgen_htotal(void *pInstance)
6574 {
6575 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6576 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6577
6578 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_05_L, 0x1FFF);
6579 }
6580
MHAL_SC_get_osdc_tgen_vtotal(void * pInstance)6581 MS_U16 MHAL_SC_get_osdc_tgen_vtotal(void *pInstance)
6582 {
6583 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6584 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6585
6586 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_07_L, 0x1FFF);
6587 }
6588
MHAL_SC_get_osdc_tgen_vframe_de_start(void * pInstance)6589 MS_U16 MHAL_SC_get_osdc_tgen_vframe_de_start(void *pInstance)
6590 {
6591 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6592 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6593
6594 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0A_L, 0x1FFF);
6595 }
6596
MHAL_SC_get_osdc_tgen_vframe_de_end(void * pInstance)6597 MS_U16 MHAL_SC_get_osdc_tgen_vframe_de_end(void *pInstance)
6598 {
6599 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6600 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6601
6602 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0B_L, 0x1FFF);
6603 }
6604
MHAL_SC_get_osdc_tgen_vsync_start(void * pInstance)6605 MS_U16 MHAL_SC_get_osdc_tgen_vsync_start(void *pInstance)
6606 {
6607 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6608 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6609
6610 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0E_L, 0x1FFF);
6611 }
6612
MHAL_SC_get_osdc_tgen_vsync_end(void * pInstance)6613 MS_U16 MHAL_SC_get_osdc_tgen_vsync_end(void *pInstance)
6614 {
6615 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6616 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6617
6618 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0F_L, 0x1FFF);
6619 }
6620
MHAL_SC_get_osdc_mixer_bypass_status(void * pInstance)6621 MS_BOOL MHAL_SC_get_osdc_mixer_bypass_status(void *pInstance)
6622 {
6623 MS_BOOL bEnable = DISABLE;
6624 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6625 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6626
6627 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(0)));
6628 return bEnable;
6629 }
6630
MHAL_SC_get_osdc_mixer_inv_alpha_status(void * pInstance)6631 MS_BOOL MHAL_SC_get_osdc_mixer_inv_alpha_status(void *pInstance)
6632 {
6633 MS_BOOL bEnable = DISABLE;
6634 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6635 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6636
6637 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(1))>>1);
6638 return bEnable;
6639 }
6640 //1:hs_out = hs&vfde
MHAL_SC_get_osdc_mixer_hs_n_vfde_status(void * pInstance)6641 MS_BOOL MHAL_SC_get_osdc_mixer_hs_n_vfde_status(void *pInstance)
6642 {
6643 MS_BOOL bEnable = DISABLE;
6644 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6645 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6646
6647 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(2))>>2);
6648 return bEnable;
6649 }
6650 //1:de(hfde)_out = de(hfde)&vfde
MHAL_SC_get_osdc_mixer_hfde_n_vfde_status(void * pInstance)6651 MS_BOOL MHAL_SC_get_osdc_mixer_hfde_n_vfde_status(void *pInstance)
6652 {
6653 MS_BOOL bEnable = DISABLE;
6654 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6655 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6656
6657 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(3))>>3);
6658 return bEnable;
6659 }
6660
MHAL_SC_get_osdc_onoff_status(void * pInstance)6661 MS_BOOL MHAL_SC_get_osdc_onoff_status(void *pInstance)
6662 {
6663 // Enable OSDC LPLL
6664 MS_BOOL bEnable = DISABLE;
6665 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED));
6666 return bEnable;
6667 }
6668
MHal_XC_SetForceCurrentReadBank(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6669 void MHal_XC_SetForceCurrentReadBank(void *pInstance,MS_BOOL bEnable, SCALER_WIN eWindow)
6670 {
6671 UNUSED(pInstance);
6672 UNUSED(bEnable);
6673 UNUSED(eWindow);
6674 }
6675
MHal_XC_SetForceReadBank(void * pInstance,MS_BOOL bEnable,MS_U8 u8Bank,SCALER_WIN eWindow)6676 void MHal_XC_SetForceReadBank(void *pInstance, MS_BOOL bEnable, MS_U8 u8Bank, SCALER_WIN eWindow)
6677 {
6678 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6679 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6680 if (eWindow == MAIN_WINDOW)
6681 {
6682 if (bEnable)
6683 {
6684 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(11), BIT(11));
6685 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (u8Bank & 0x7) << 8, BIT(10)|BIT(9)|BIT(8));
6686 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_06_L, ((u8Bank & 0x8) >> 3) << 14, BIT(14));
6687 }
6688 else
6689 {
6690 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0, BIT(11));
6691 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0, BIT(10)|BIT(9)|BIT(8));
6692 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_06_L, 0, BIT(14));
6693 }
6694 }
6695 else
6696 {
6697 if (bEnable)
6698 {
6699 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(11), BIT(11));
6700 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, (u8Bank & 0x7) << 8, BIT(10)|BIT(9)|BIT(8));
6701 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_46_L, ((u8Bank & 0x8) >> 3) << 14, BIT(14));
6702 }
6703 else
6704 {
6705 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0, BIT(11));
6706 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0, BIT(10)|BIT(9)|BIT(8));
6707 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_46_L, 0, BIT(14));
6708 }
6709 }
6710 }
6711
MHal_XC_SetDNRBufAddress(void * pInstance,MS_PHY u32DNRBaseAddr,SCALER_WIN eWindow)6712 MS_BOOL MHal_XC_SetDNRBufAddress(void *pInstance, MS_PHY u32DNRBaseAddr, SCALER_WIN eWindow)
6713 {
6714 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6715 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6716 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6717 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6718 pXCResourcePrivate->sthal_SC._u32DNRBaseAddress[eWindow] = u32DNRBaseAddr;
6719 return TRUE;
6720 }
6721
MHal_XC_GetDNRBufAddress(void * pInstance,SCALER_WIN eWindow)6722 MS_PHY MHal_XC_GetDNRBufAddress(void *pInstance, SCALER_WIN eWindow)
6723 {
6724 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6725 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6726 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6727 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6728 return pXCResourcePrivate->sthal_SC._u32DNRBaseAddress[eWindow] ;
6729 }
6730
MHal_XC_SetDNRBufSize(void * pInstance,MS_PHY u32DNRBufSize,SCALER_WIN eWindow)6731 MS_BOOL MHal_XC_SetDNRBufSize(void *pInstance, MS_PHY u32DNRBufSize, SCALER_WIN eWindow)
6732 {
6733 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6734 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6735 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6736 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6737 pXCResourcePrivate->sthal_SC._u32DNRBufferSize[eWindow] = u32DNRBufSize;
6738 return TRUE;
6739 }
6740
MHal_XC_GetDNRBufSize(void * pInstance,SCALER_WIN eWindow)6741 MS_PHY MHal_XC_GetDNRBufSize(void *pInstance, SCALER_WIN eWindow)
6742 {
6743 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6744 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6745 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6746 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6747 return pXCResourcePrivate->sthal_SC._u32DNRBufferSize[eWindow] ;
6748 }
6749
MHal_XC_SetFRCMBufAddress(void * pInstance,MS_PHY u32BaseAddr,SCALER_WIN eWindow)6750 MS_BOOL MHal_XC_SetFRCMBufAddress(void *pInstance, MS_PHY u32BaseAddr, SCALER_WIN eWindow)
6751 {
6752 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6753 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6754 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6755 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6756 pXCResourcePrivate->sthal_SC._u32FRCBaseAddress[eWindow] = u32BaseAddr;
6757 return TRUE;
6758 }
6759
MHal_XC_GetFRCMBufAddress(void * pInstance,SCALER_WIN eWindow)6760 MS_PHY MHal_XC_GetFRCMBufAddress(void *pInstance, SCALER_WIN eWindow)
6761 {
6762 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6763 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6764 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6765 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6766 return pXCResourcePrivate->sthal_SC._u32FRCBaseAddress[eWindow] ;
6767 }
6768
MHal_XC_SetFRCMBufSize(void * pInstance,MS_PHY u32BufSize,SCALER_WIN eWindow)6769 MS_BOOL MHal_XC_SetFRCMBufSize(void *pInstance, MS_PHY u32BufSize, SCALER_WIN eWindow)
6770 {
6771 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6772 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6773 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6774 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6775 pXCResourcePrivate->sthal_SC._u32FRCBufferSize[eWindow] = u32BufSize;
6776 return TRUE;
6777 }
6778
MHal_XC_GetFRCMBufSize(void * pInstance,SCALER_WIN eWindow)6779 MS_PHY MHal_XC_GetFRCMBufSize(void *pInstance, SCALER_WIN eWindow)
6780 {
6781 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6782 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6783 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6784 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6785 return pXCResourcePrivate->sthal_SC._u32FRCBufferSize[eWindow] ;
6786 }
6787
MHal_XC_SetDualDNRBufAddress(void * pInstance,MS_PHY u32DNRBaseAddr,SCALER_WIN eWindow)6788 MS_BOOL MHal_XC_SetDualDNRBufAddress(void *pInstance, MS_PHY u32DNRBaseAddr, SCALER_WIN eWindow)
6789 {
6790 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6791 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6792 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6793 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6794 pXCResourcePrivate->_u32DualDNRBaseAddress[eWindow] = u32DNRBaseAddr;
6795 return TRUE;
6796 }
6797
MHal_XC_GetDualDNRBufAddress(void * pInstance,SCALER_WIN eWindow)6798 MS_PHY MHal_XC_GetDualDNRBufAddress(void *pInstance, SCALER_WIN eWindow)
6799 {
6800 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6801 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6802 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6803 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6804 return pXCResourcePrivate->_u32DualDNRBaseAddress[eWindow];
6805 }
6806
MHal_XC_SetDualDNRBufSize(void * pInstance,MS_PHY u32DNRBufSize,SCALER_WIN eWindow)6807 MS_BOOL MHal_XC_SetDualDNRBufSize(void *pInstance, MS_PHY u32DNRBufSize, SCALER_WIN eWindow)
6808 {
6809 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6810 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6811 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6812 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6813 pXCResourcePrivate->_u32DualDNRBufferSize[eWindow] = u32DNRBufSize;
6814 return TRUE;
6815 }
6816
MHal_XC_GetDualDNRBufSize(void * pInstance,SCALER_WIN eWindow)6817 MS_PHY MHal_XC_GetDualDNRBufSize(void *pInstance, SCALER_WIN eWindow)
6818 {
6819 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6820 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6821 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6822 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6823 return pXCResourcePrivate->_u32DualDNRBufferSize[eWindow] ;
6824 }
6825
MHal_XC_Init_Patch(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6826 MS_BOOL MHal_XC_Init_Patch(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6827 {
6828 if (eWindow >= MAX_WINDOW)
6829 {
6830 printf("[%s,%5d] maximum window exceeded",__FUNCTION__,__LINE__);
6831 return FALSE;
6832 }
6833
6834 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6835 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6836 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6837 //FIX ME:review manhattan need it?
6838 if (psXCInstPri->u32DeviceID >= 1)
6839 {
6840 // by HW RD's request, for sub video BW issue, adjust R/W line buffer length
6841 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_20_L, 0x1E1E);
6842 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_21_L, 0x1E1E);
6843 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_22_L, 0x1E1E);
6844 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_23_L, 0x1010);
6845 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_24_L, 0x20, 0xFF);
6846 return FALSE;
6847 }
6848 #endif
6849
6850 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_6F_L, 0x20, 0x3F); // by HW RD's request, for BB section offset issue
6851
6852 // by HW RD's request, for main video BW issue, adjust R/W line buffer length
6853 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_20_L, 0x1818);
6854 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_21_L, 0x1818);
6855 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_22_L, 0x1818);
6856
6857 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_25_L, 0x3030); // by HW RD's request, for HDMI 4K BW issue, adjust R/W line buffer length
6858 #ifdef UFO_XC_SUPPORT_DUAL_MIU
6859 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_25_L, 0x3030); // by HW RD's request, for HDMI 4K BW issue, adjust R/W line buffer length
6860 #endif
6861
6862 // SW patch for Monaco
6863 // by HW RD's request, to fix HDMI 1080i repeat garbage at left side
6864 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_37_L, 0x20); // bypass main line buffer length setting
6865 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK11_37_L, 0x20); // bypass sub line buffer length setting
6866
6867 // ECO item for Monaco: hvsp PIP B section last flag error
6868 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_5F_L, BIT(14), BIT(14));
6869
6870 // ECO item for Monaco: ip2ve 4K path Vsync need inverse
6871 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_7F_L, BIT(14), BIT(14));
6872 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_7F_L, BIT(14), BIT(14));
6873
6874 // SW patch for muji : 4k2k 3D LA out show garbage on the top, issue with BW
6875 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK58_10_L, 0x0000, BIT(0));//disable SCM sub OP
6876
6877 // BK00_03[13] conflict with compression mode (patch for HW issue)
6878 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_03_L, 0x0000, 0x2000);
6879
6880 if(MDrv_ReadByte(REG_CHIP_REVISION) < 1)//Monaco U02 fix .
6881 {
6882 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_53_L, 0x00, BIT(10));
6883 }
6884
6885 //U03 compatible setting
6886 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_66_L, BIT(13), BIT(13));
6887
6888 ///Patch here ////
6889 #if (FRC_INSIDE)
6890 MHal_FRC_interrupt_mask(pInstance, 0xFF);
6891
6892 //enable fsc clk
6893 MDrv_WriteByteMask( REG_FSC_BK20_05, 0x10, 0x10); // reg_ckg_ficlk
6894 #endif
6895
6896 // SW patch for Eisntein
6897 // With HW Auto no signal case, sub video source change would causes OP1 broken, looks like main video broken
6898 Hal_SC_ip_enable_turnoff_OP1_for_AutoNoSignal(pInstance, DISABLE);
6899
6900 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_61_L, 0x01, 0x03); // for HDMI 2.0, always receive 444 format
6901 SC_W2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK01_63_L, 0x01, 0x01); // for HDMI odd Htt support
6902
6903
6904 return TRUE;
6905 }
MHal_XC_IsPNLYUVOutput(void * pInstance)6906 MS_BOOL MHal_XC_IsPNLYUVOutput(void *pInstance)
6907 {
6908 MS_BOOL bIsPNLYUVOutput = TRUE;
6909 #if 0//below is logic from TV, need box RD's confirm, disable it temporary
6910 MS_BOOL bIsY2REnable = FALSE, bIsR2YEnable = FALSE;
6911 SCALER_WIN eWindow = MAIN_WINDOW;
6912 MS_U16 u16Temp = 0;
6913 //Get CSC state before OP2
6914 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled || gSrcInfo[MAIN_WINDOW].bBluescreenEnabled)
6915 {
6916 //Main is mute, so check sub
6917 if(Hal_SC_Is_subwindow_enable())
6918 {
6919 if(!(gSrcInfo[SUB_WINDOW].bBlackscreenEnabled || gSrcInfo[SUB_WINDOW].bBluescreenEnabled))
6920 {
6921 eWindow = SUB_WINDOW;
6922 }
6923 }
6924 }
6925
6926 if(eWindow == MAIN_WINDOW)
6927 {
6928 u16Temp = SC_R2BYTE(REG_SC_BK10_2F_L);
6929 if((u16Temp & ( BIT(0) | BIT(2) | BIT(4))) == ( BIT(0) | BIT(2) | BIT(4)))
6930 {
6931 bIsY2REnable = TRUE;
6932 }
6933 }
6934 else
6935 {
6936 u16Temp = SC_R2BYTE(REG_SC_BK0F_26_L);
6937 if((u16Temp & ( BIT(0) | BIT(2) | BIT(4))) == ( BIT(0) | BIT(2) | BIT(4)))
6938 {
6939 bIsY2REnable = TRUE;
6940 }
6941 }
6942
6943 if(bIsY2REnable)
6944 {
6945 bIsPNLYUVOutput = FALSE;
6946 }
6947 else
6948 {
6949 //OP Y2R disable, so check op input
6950 if(eWindow == MAIN_WINDOW)
6951 {
6952 bIsR2YEnable = (MS_BOOL)(SC_R2BYTEMSK(REG_SC_BK02_40_L, BIT(3)) || SC_R2BYTEMSK(REG_SC_BK18_06_L, BIT(0)));
6953
6954 }
6955 else
6956 {
6957 bIsR2YEnable = (MS_BOOL)(SC_R2BYTEMSK(REG_SC_BK04_40_L, BIT(3)) || SC_R2BYTEMSK(REG_SC_BK18_76_L, BIT(0)));
6958 }
6959
6960 if(bIsR2YEnable)
6961 {
6962 //Y2R enable
6963 bIsPNLYUVOutput = TRUE;
6964 }
6965 else
6966 {
6967 //All Csc is off, so check input
6968 //VGA/DVI/rgb HDMI is rgb input
6969 if( IsSrcTypeVga(gSrcInfo[eWindow].enInputSourceType) //VGA
6970 ||IsSrcTypeDVI(gSrcInfo[eWindow].enInputSourceType) //DVI
6971 ||( IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)
6972 &&(g_HdmiPollingStatus.bIsHDMIMode == TRUE)
6973 &&(g_HdmiPollingStatus.u8ColorFormat == MS_HDMI_COLOR_RGB))//HDMI RGB
6974 ||( IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)
6975 &&(g_HdmiPollingStatus.bIsHDMIMode == FALSE)) //HDMI_DVI
6976 )
6977 {
6978 bIsPNLYUVOutput = FALSE;
6979 }
6980 else
6981 {
6982 bIsPNLYUVOutput = TRUE;
6983 }
6984 }
6985 }
6986 #endif
6987 return bIsPNLYUVOutput;
6988 }
6989
Hal_SC_Init(void * pInstance)6990 MS_BOOL Hal_SC_Init(void *pInstance)
6991 {
6992 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6993 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6994 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6995 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6996
6997 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
6998 MHal_FRC_Composer_User_Mode_Enable(pInstance, ENABLE);
6999 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_VIP, FALSE);
7000 MHal_FRC_Set_Pipe_Delay_Mode(pInstance, E_FRC_PIPE_DELAY_MODE_USER);
7001 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FRC, FRC_PIPE_DELAY_VCNT_FRC);
7002 MHal_FRC_Set_FSC_DE_Selection(pInstance, E_FRC_FSC_SOURCE_MODE_FDE); // make FSC use FDE range from VIP to do SR
7003
7004 // For FSC/FRC clk init
7005 MHal_CLKGEN_FRC_Init(pInstance,pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode);
7006
7007 // For STGEN init
7008 MHal_FRC_TGEN_Init(pInstance);
7009
7010 // For STGEN init setting
7011 MST_PANEL_INFO_t stFRCPanelInfo;
7012 if (FALSE == pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
7013 {
7014 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelHSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth;
7015 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelHSyncBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch;
7016 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelVSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth;
7017 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelVSyncBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch;
7018 }
7019
7020 MDrv_FRC_PNLInfo_Transform(pInstance, &pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo,&pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc, &stFRCPanelInfo);
7021 MDrv_FRC_Tx_SetTgen(pInstance, &stFRCPanelInfo);
7022
7023 MHal_FRC_ByPass_Enable(pInstance, TRUE); // default disable FRC
7024 #endif
7025
7026 #if 0
7027 MHal_XC_FRCR2_IP_Patch(pInstance, MAIN_WINDOW);
7028 MHal_XC_FRCR2_OP_Patch(pInstance, MAIN_WINDOW);
7029 #endif
7030
7031 return TRUE;
7032 }
7033
Hal_SC_Get_Device_Offset(MS_U8 deviceIdx)7034 MS_U32 Hal_SC_Get_Device_Offset(MS_U8 deviceIdx)
7035 {
7036 MS_U32 ret_U32 = 0 ;
7037 if(deviceIdx == 0 )
7038 {
7039 ret_U32 = MAX_XC_DEVICE0_OFFSET;
7040 }
7041 else if(deviceIdx == 1)
7042 {
7043 ret_U32 = MAX_XC_DEVICE1_OFFSET;
7044 }
7045 return ret_U32;
7046 }
7047
HAL_SC_Set_LB_MergeAddress(void * pInstance)7048 void HAL_SC_Set_LB_MergeAddress(void *pInstance)
7049 {
7050 return;
7051 }
7052
Hal_SC_set_edclk(void * pInstance,MS_U8 u8Clk_Mux,MS_BOOL bEnable,SCALER_WIN eWindow)7053 void Hal_SC_set_edclk(void *pInstance, MS_U8 u8Clk_Mux, MS_BOOL bEnable, SCALER_WIN eWindow)
7054 {
7055 if(eWindow==MAIN_WINDOW)
7056 {
7057 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED);
7058 if(bEnable)
7059 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK);
7060 }
7061 else if(eWindow==SUB_WINDOW)
7062 {
7063 MDrv_WriteByteMask(REG_CKG_EDCLK_F1, (bEnable? 0x00 : CKG_EDCLK_F1_GATED), CKG_EDCLK_F1_GATED);
7064 if(bEnable)
7065 MDrv_WriteByteMask(REG_CKG_EDCLK_F1, u8Clk_Mux, CKG_EDCLK_F1_MASK);
7066 }
7067 }
7068
Hal_SC_set_ficlk2(void * pInstance,MS_U8 u8Clk_Mux,MS_BOOL bEnable,SCALER_WIN eWindow)7069 void Hal_SC_set_ficlk2(void *pInstance, MS_U8 u8Clk_Mux, MS_BOOL bEnable, SCALER_WIN eWindow)
7070 {
7071 if(eWindow==MAIN_WINDOW)
7072 {
7073 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED);
7074 if(bEnable)
7075 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK);
7076 }
7077 else if(eWindow==SUB_WINDOW)
7078 {
7079 printf("[%s,%5d] ficlk2_f2 not support sub!",__FUNCTION__,__LINE__);// no ficlk2_f1 for sub window
7080 }
7081 }
7082
Hal_SC_set_fmclk(void * pInstance,MS_BOOL bEnable)7083 void Hal_SC_set_fmclk(void *pInstance, MS_BOOL bEnable)
7084 {
7085 if(bEnable == TRUE)
7086 {
7087 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK);
7088 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED);
7089 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT);
7090 }
7091 else
7092 {
7093 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock
7094 }
7095 }
7096
HAL_SC_EnableLegacyMode(void * pInstance,MS_BOOL bEnable)7097 void HAL_SC_EnableLegacyMode(void *pInstance, MS_BOOL bEnable)
7098 {
7099 #if (HW_DESIGN_4K2K_VER == 4)
7100 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7101 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7102
7103 if (psXCInstPri->u32DeviceID == 0)
7104 {
7105 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_01_L, (bEnable<<0), BIT(0));
7106 }
7107 else
7108 {
7109 // do nothing, because there is only legacy mode in SC2, we don't have to do any switch
7110 }
7111 #endif
7112 }
7113
MHal_XC_DTVPatchISR(SC_INT_SRC eIntNum,void * pParam)7114 static void MHal_XC_DTVPatchISR(SC_INT_SRC eIntNum, void * pParam)
7115 {
7116 void *pInstance = pu32XCInst_private;
7117 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7118 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7119 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7120 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7121
7122 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled==FALSE)
7123 {
7124 //Check timing 2s
7125 if(((MsOS_GetSystemTime()- u32DTVPatchTimer)>2000))
7126 {
7127 u32DTVPatchTimer = MsOS_GetSystemTime();
7128 u16FDMaskCount=0;
7129 }
7130
7131 //Check FD mask
7132 if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0))
7133 {
7134 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0);
7135 u16FDMaskCount++;
7136 }
7137
7138 if(u16FDMaskCount>6)
7139 {
7140 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
7141 {
7142 //UC_CTL off
7143 _MLOAD_ENTRY(pInstance);
7144 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK17_01_L, 0 ,BIT(0));
7145 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK57_23_L, 0 ,0x40);
7146 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0);
7147 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_07_L, 0 ,BIT(0));
7148 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_20_L, 0 ,BIT(7));
7149 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_21_L, 0 ,BIT(15));
7150 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_78_L, 0 ,0xC000);
7151 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2A_02_L, BIT(1) ,BIT(1)|BIT(15));
7152 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_20_L, 0 ,BIT(0));
7153 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_12_L, 0 ,BIT(0));
7154 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2A_07_L, 0 ,BIT(0));
7155 MDrv_XC_MLoad_Fire(pInstance, TRUE);
7156 _MLOAD_RETURN(pInstance);
7157 }
7158 else
7159 {
7160 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_01_L, 0 ,BIT(0));
7161 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_23_L, 0 ,0x40);
7162 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0);
7163 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0 ,BIT(0));
7164 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_20_L, 0 ,BIT(7));
7165 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_21_L, 0 ,BIT(15));
7166 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_78_L, 0 ,0xC000);
7167 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(1) ,BIT(1)|BIT(15));
7168 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_20_L, 0 ,BIT(0));
7169 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_12_L, 0 ,BIT(0));
7170 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_07_L, 0 ,BIT(0));
7171 }
7172
7173 u16FDMaskCount=0;
7174
7175 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL))
7176 {
7177 //Disable ISR
7178 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL);
7179 }
7180 }
7181 }
7182 }
7183
MHal_XC_DTVPatch(void * pInstance,SCALER_WIN eWindow)7184 void MHal_XC_DTVPatch(void *pInstance, SCALER_WIN eWindow)
7185 {
7186 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7187 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7188 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7189 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7190
7191 if(eWindow ==MAIN_WINDOW)
7192 {
7193 if(IsSrcTypeDTV(gSrcInfo[MAIN_WINDOW].enInputSourceType)
7194 &&(gSrcInfo[MAIN_WINDOW].stCapWin.width==1920)
7195 &&(gSrcInfo[MAIN_WINDOW].stCapWin.height==1080)
7196 &&(gSrcInfo[MAIN_WINDOW].bInterlace==TRUE))
7197 {
7198 //DTV 1080i patch
7199 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT,MHal_XC_DTVPatchISR, (void *)NULL))
7200 {
7201 //Start DTV 1080i patch, enable ISR
7202 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT,MHal_XC_DTVPatchISR, (void *)NULL);
7203 }
7204 }
7205 else
7206 {
7207 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL))
7208 {
7209 //Disable ISR
7210 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL);
7211 }
7212 }
7213 }
7214 }
7215
7216
7217 #ifndef DONT_USE_CMA
7218 #if (XC_SUPPORT_CMA ==TRUE)
MHal_XC_Get_CMA_Addr(void * pInstance,XC_CMA_CLIENT enCmaClient,MS_U32 u32GetCMASize,SCALER_WIN eWindow)7219 MS_U64 MHal_XC_Get_CMA_Addr(void *pInstance, XC_CMA_CLIENT enCmaClient, MS_U32 u32GetCMASize, SCALER_WIN eWindow)
7220 {
7221 MS_U64 u64CMAAddr = 0;
7222 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7223 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7224 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7225 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7226
7227 if (u32GetCMASize == 0)
7228 {
7229 return u64CMAAddr;
7230 }
7231
7232 struct CMA_Pool_Alloc_Param CMA_Pool_GetMem;
7233 CMA_Pool_GetMem.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].pool_handle_id;
7234 CMA_Pool_GetMem.offset_in_pool = gSrcInfo[eWindow].Status2.stXCConfigCMA[enCmaClient].u64AddrHeapOffset;
7235 CMA_Pool_GetMem.flags = CMA_FLAG_VIRT_ADDR;
7236 if(CMA_Pool_Init_PARAM[enCmaClient].heap_length >= u32GetCMASize)
7237 {
7238 CMA_Pool_GetMem.length = u32GetCMASize;
7239 }
7240 else
7241 {
7242 printf("\033[35m Function = %s, Line = %d, CMA_POOL_INIT GetMem ERROR!!\033[m\n", __PRETTY_FUNCTION__, __LINE__);
7243 //assert(0);
7244 }
7245
7246 MApi_CMA_Pool_GetMem(&CMA_Pool_GetMem);
7247 u64CMAAddr = CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset;
7248 if(CMA_Pool_Init_PARAM[enCmaClient].miu==E_CHIP_MIU_1)
7249 {
7250 u64CMAAddr= CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset+HAL_MIU1_BASE;
7251 }
7252 else if(CMA_Pool_Init_PARAM[enCmaClient].miu==E_CHIP_MIU_2)
7253 {
7254 u64CMAAddr= CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset+HAL_MIU2_BASE;
7255 }
7256
7257 return u64CMAAddr;
7258 }
7259
_Hal_SC_Limit_WriteMem(void * pInstance,SCALER_WIN eWindow)7260 static void _Hal_SC_Limit_WriteMem(void *pInstance, SCALER_WIN eWindow)
7261 {
7262 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7263 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7264 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7265 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7266 MS_PHY u32WriteLimitAddr = pXCResourcePrivate->stdrvXC_3D._u32HW2DTO3D_DD_Buf;
7267 MS_BOOL bNeedRestore = FALSE;
7268
7269 if (Hal_SC_Is_InputSource_Disable(pInstance, eWindow)==0)
7270 {
7271 bNeedRestore = TRUE;
7272 MDrv_XC_DisableInputSource(pInstance, TRUE, eWindow);
7273 }
7274
7275 MDrv_XC_SetFrameBufferAddress(pInstance, u32WriteLimitAddr, 0, eWindow);
7276
7277 if (bNeedRestore == TRUE)
7278 {
7279 bNeedRestore = FALSE;
7280 MDrv_XC_DisableInputSource(pInstance, FALSE, eWindow);
7281 }
7282 }
7283
_Hal_SC_Limit_Dual_WriteMem(void * pInstance,SCALER_WIN eWindow)7284 static void _Hal_SC_Limit_Dual_WriteMem(void *pInstance, SCALER_WIN eWindow)
7285 {
7286 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7287 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7288 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7289 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7290 MS_BOOL bNeedRestore = FALSE;
7291
7292 if (Hal_SC_Is_InputSource_Disable(pInstance, eWindow)==0)
7293 {
7294 bNeedRestore = TRUE;
7295 MDrv_XC_DisableInputSource(pInstance, TRUE, eWindow);
7296 }
7297
7298 if(eWindow == MAIN_WINDOW)
7299 {
7300 /// need to disable the r/w request, when change the write limit base
7301 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
7302 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, BIT(4),BIT(4)); //F2 memory address limit enable
7303 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, 0, BIT(15)); // disable dual to defect xc dual write miu
7304 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, 0x00); //F2 memory min address
7305 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, 0x00); //F2 memory max address
7306 }
7307 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[eWindow] = 0;
7308 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBSize[eWindow] = 0;
7309
7310 if (bNeedRestore == TRUE)
7311 {
7312 bNeedRestore = FALSE;
7313 MDrv_XC_DisableInputSource(pInstance, FALSE, eWindow);
7314 }
7315 }
7316
MHal_XC_Release_CMA(void * pInstance,XC_CMA_CLIENT enCmaClient,SCALER_WIN eWindow)7317 MS_BOOL MHal_XC_Release_CMA(void *pInstance, XC_CMA_CLIENT enCmaClient, SCALER_WIN eWindow)
7318 {
7319 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7320 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7321 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7322 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7323
7324 struct CMA_Pool_Free_Param stCMAFreeParam;
7325 if ((gSrcInfo[eWindow].u32PreCMAMemSCMSize[enCmaClient]+gSrcInfo[eWindow].u32PreCMAMemFRCMSize[enCmaClient])!=0)
7326 {
7327 _Hal_SC_Limit_WriteMem(pInstance, eWindow);
7328 stCMAFreeParam.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].heap_id; //in: pool handle id, when pool init, returned by kernel
7329 stCMAFreeParam.offset_in_pool = gSrcInfo[eWindow].Status2.stXCConfigCMA[enCmaClient].u64AddrHeapOffset;
7330 stCMAFreeParam.length = gSrcInfo[eWindow].u32PreCMAMemSCMSize[enCmaClient]+gSrcInfo[eWindow].u32PreCMAMemFRCMSize[enCmaClient];
7331 MApi_CMA_Pool_PutMem(&stCMAFreeParam);
7332
7333 gSrcInfo[eWindow].u32PreCMAMemSCMSize[enCmaClient] = 0;
7334 gSrcInfo[eWindow].u32PreCMAMemFRCMSize[enCmaClient] = 0;
7335 }
7336
7337 if ((gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize != 0) && (enCmaClient == CMA_XC_COBUFF_MEM))
7338 {
7339 _Hal_SC_Limit_Dual_WriteMem(pInstance, eWindow);
7340 stCMAFreeParam.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].heap_id; //in: pool handle id, when pool init, returned by kernel
7341 stCMAFreeParam.offset_in_pool = gSrcInfo[eWindow].Status2.stXCConfigCMA[enCmaClient].u64AddrHeapOffset;
7342 stCMAFreeParam.length = gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize;
7343 MApi_CMA_Pool_PutMem(&stCMAFreeParam);
7344
7345 gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize = 0;
7346 }
7347
7348 return TRUE;
7349 }
7350
_getDualModeMemorySize(void * pInstance,MS_U32 * pu32LeftSize,MS_U32 * pu32RightSize,SCALER_WIN eWindow)7351 static MS_BOOL _getDualModeMemorySize(void *pInstance, MS_U32 *pu32LeftSize, MS_U32 *pu32RightSize, SCALER_WIN eWindow)
7352 {
7353 MS_U32 u32TotalSize = 0;
7354
7355 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7356 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7357 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7358 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7359 if (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID && ((gSrcInfo[eWindow].enInputSourceType >= INPUT_SOURCE_HDMI)&&(gSrcInfo[eWindow].enInputSourceType <= INPUT_SOURCE_HDMI_MAX)))
7360 {
7361 if(pXCResourcePrivate->stdrvXC_MVideo.bUseDdr4DramForXc)
7362 u32TotalSize = XC_CMA_96MB + XC_CMA_24MB;
7363 else
7364 u32TotalSize = XC_CMA_96MB;
7365 }
7366 *pu32LeftSize = u32TotalSize * gSrcInfo[eWindow].Status2.stMiuDualModCfg.u32LeftFactor/(gSrcInfo[eWindow].Status2.stMiuDualModCfg.u32LeftFactor + gSrcInfo[eWindow].Status2.stMiuDualModCfg.u32RightFactor);
7367 *pu32RightSize = u32TotalSize - *pu32LeftSize;
7368 return TRUE;
7369 }
7370
MHal_XC_Get_CMA_UsingCondition(void * pInstance,MS_BOOL bIsGetCMABuff[],MS_U32 au32CMAMemSCMSize[],MS_U32 au32CMAMemFRCMSize[],MS_U32 * pu32DualMiuMemSize,MS_U32 u32DataSize,SCALER_WIN eWindow)7371 MS_BOOL MHal_XC_Get_CMA_UsingCondition(void *pInstance, MS_BOOL bIsGetCMABuff[], MS_U32 au32CMAMemSCMSize[],MS_U32 au32CMAMemFRCMSize[], MS_U32* pu32DualMiuMemSize, MS_U32 u32DataSize, SCALER_WIN eWindow)
7372 {
7373 MS_U32 u32CMAMemSCMSize = 0;
7374 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7375 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7376 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7377 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7378
7379 if (u32DataSize < CMA_XC_MEM_NUM)
7380 {
7381 return FALSE;
7382 }
7383
7384 if ((MDrv_XC_Is_DSForceIndexEnabled(pInstance, MAIN_WINDOW)||MDrv_XC_GetDynamicScalingStatus(pInstance))
7385 && IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType))
7386 {
7387 // MM source and DS on 4K2K case, interlace also using 4k2k virtualbox because some streams is i/p change
7388 u32CMAMemSCMSize = XC_CMA_96MB;
7389 }
7390 else if (IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType))
7391 {
7392 u32CMAMemSCMSize = XC_CMA_96MB;
7393 }
7394 else if ( (IsSrcTypeAV(gSrcInfo[eWindow].enInputSourceType))
7395 ||(IsSrcTypeSV(gSrcInfo[eWindow].enInputSourceType))
7396 ||(IsSrcTypeATV(gSrcInfo[eWindow].enInputSourceType))
7397 ||(IsSrcTypeScart(gSrcInfo[eWindow].enInputSourceType)))
7398 {
7399 u32CMAMemSCMSize = XC_CMA_19MB;
7400 }
7401 else
7402 {
7403 if ((gSrcInfo[(eWindow)].stCapWin.width>= 3840) && (gSrcInfo[(eWindow)].stCapWin.height>= 2160))
7404 {
7405 if (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID && IsEnableDualMode(eWindow))
7406 {
7407 // HDMI dual miu
7408 u32CMAMemSCMSize = XC_CMA_48MB;
7409 }
7410 else
7411 {
7412 // 4K2K DTV
7413 u32CMAMemSCMSize = XC_CMA_96MB;
7414 }
7415 }
7416 else
7417 {
7418 u32CMAMemSCMSize = XC_CMA_48MB;
7419 }
7420 }
7421
7422 if (
7423 #ifdef UFO_XC_SUPPORT_DUAL_MIU
7424 (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID)
7425 && IsEnableDualMode(eWindow)
7426 #else
7427 0
7428 #endif
7429 )
7430 {
7431 bIsGetCMABuff[CMA_XC_SELF_MEM] = TRUE;
7432 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = TRUE;
7433 //*pu32DualMiuMemSize = XC_CMA_48MB;
7434 //au32CMAMemSCMSize[CMA_XC_SELF_MEM] = u32CMAMemSCMSize;
7435 _getDualModeMemorySize(pInstance, &au32CMAMemSCMSize[CMA_XC_SELF_MEM], pu32DualMiuMemSize, eWindow);
7436 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = 0;
7437 }
7438 else
7439 {
7440 if (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID == XC_INVALID_HEAP_ID || IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType) || IsSrcTypeDTV(gSrcInfo[eWindow].enInputSourceType))
7441 {
7442 bIsGetCMABuff[CMA_XC_SELF_MEM] = TRUE;
7443 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = FALSE;
7444 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = u32CMAMemSCMSize;
7445 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = 0;
7446 }
7447 else
7448 {
7449 bIsGetCMABuff[CMA_XC_SELF_MEM] = FALSE;
7450 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = TRUE;
7451 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = 0;
7452 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = u32CMAMemSCMSize;
7453 }
7454 *pu32DualMiuMemSize = 0;
7455 }
7456
7457 au32CMAMemFRCMSize[CMA_XC_SELF_MEM] = 0;
7458 au32CMAMemFRCMSize[CMA_XC_COBUFF_MEM] = 0;
7459
7460 return TRUE;
7461 }
7462 #if 0
7463 static void MHal_XC_CMAPatchISR(SC_INT_SRC eIntNum, void * pParam)
7464 {
7465 void *pInstance = pu32XCInst_private;
7466 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7467 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7468 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7469 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7470
7471
7472 if(((MsOS_GetSystemTime()- u32CMAPatchTimer_Main)>6000))
7473 {
7474 u32CMAPatchTimer_Main = MsOS_GetSystemTime();
7475 }
7476
7477 if((MDrv_XC_IsInputSourceDisabled(pInstance, MAIN_WINDOW)==TRUE)
7478 &&( ((gSrcInfo[MAIN_WINDOW].u32PreCMAMemSCMSize[CMA_XC_SELF_MEM]+gSrcInfo[MAIN_WINDOW].u32PreCMAMemFRCMSize[CMA_XC_SELF_MEM])!=0)
7479 ||((gSrcInfo[MAIN_WINDOW].u32PreCMAMemSCMSize[CMA_XC_COBUFF_MEM]+gSrcInfo[MAIN_WINDOW].u32PreCMAMemFRCMSize[CMA_XC_COBUFF_MEM])!=0)
7480 #ifdef UFO_XC_SUPPORT_DUAL_MIU
7481 ||(gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize!=0)
7482 #endif
7483 )
7484 )
7485 {
7486 //Check timing 5s
7487 if(((MsOS_GetSystemTime()- u32CMAPatchTimer_Main)>5000))
7488 {
7489 u32CMAPatchTimer_Main = MsOS_GetSystemTime();
7490
7491 MHal_XC_Release_CMA(pInstance, CMA_XC_SELF_MEM, MAIN_WINDOW);
7492 MHal_XC_Release_CMA(pInstance, CMA_XC_COBUFF_MEM, MAIN_WINDOW);
7493
7494 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7495 // For FRC case, if no input source, need to disable FRC for power saving
7496 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
7497 {
7498 MHal_FRC_ByPass_Enable(pInstance, TRUE);
7499 }
7500 #endif
7501 }
7502 }
7503 else
7504 {
7505 u32CMAPatchTimer_Main = MsOS_GetSystemTime();
7506 }
7507 }
7508 #endif
MHal_XC_CMAPatch(void * pInstance,SCALER_WIN eWindow)7509 void MHal_XC_CMAPatch(void *pInstance, SCALER_WIN eWindow)
7510 {
7511 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7512 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7513 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7514 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7515
7516 //if(eWindow ==MAIN_WINDOW)
7517 //{
7518 // if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT,MHal_XC_CMAPatchISR, (void *)NULL))
7519 // {
7520 // //Start CMA patch, enable ISR
7521 // //FIXME: PATCH
7522 // MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT,MHal_XC_CMAPatchISR, (void *)NULL);
7523 // }
7524 //}
7525 }
7526
MHal_XC_CMAPatchClose(void * pInstance,SCALER_WIN eWindow)7527 void MHal_XC_CMAPatchClose(void *pInstance, SCALER_WIN eWindow)
7528 {
7529 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7530 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7531 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7532 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7533
7534 //if(eWindow ==MAIN_WINDOW)
7535 //{
7536 // if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_CMAPatchISR, (void *)NULL))
7537 // {
7538 // //Disable ISR
7539 // MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_CMAPatchISR, (void *)NULL);
7540 // }
7541 //}
7542 }
7543 #endif
7544 #endif
7545
MHAL_SC_set_r2y_en(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7546 void MHAL_SC_set_r2y_en(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7547 {
7548 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7549 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7550 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7551 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7552
7553 if(eWindow == MAIN_WINDOW)
7554 {
7555 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_06_L, bEnable?BIT(0):0x00, BIT(0));
7556 }
7557 else if(eWindow == SUB_WINDOW)
7558 {
7559 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_76_L, bEnable?BIT(0):0x00, BIT(0));
7560 }
7561 }
7562
MHAL_SC_get_r2y_en_status(void * pInstance,SCALER_WIN eWindow)7563 MS_BOOL MHAL_SC_get_r2y_en_status(void *pInstance, SCALER_WIN eWindow)
7564 {
7565 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7566 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7567 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7568 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7569
7570 MS_BOOL bstatus = FALSE;
7571
7572 if(eWindow == MAIN_WINDOW)
7573 {
7574 bstatus = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_06_L, BIT(0));
7575 }
7576 else if(eWindow == SUB_WINDOW)
7577 {
7578 bstatus = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_76_L, BIT(0));
7579 }
7580
7581 return bstatus;
7582 }
7583
Hal_SC_set_T3D_setting(void * pInstance,MS_BOOL bEnable)7584 void Hal_SC_set_T3D_setting(void *pInstance, MS_BOOL bEnable)
7585 {
7586 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7587 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7588
7589 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
7590 {
7591 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
7592 }
7593 else
7594 {
7595 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
7596 }
7597
7598 }
7599
Hal_SC_set_T3D_H_size(void * pInstance,MS_U16 u16Hsize)7600 void Hal_SC_set_T3D_H_size(void *pInstance, MS_U16 u16Hsize)
7601 {
7602 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7603 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7604
7605 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_55_L, u16Hsize, 0x1FFF); //horizontal pixel number
7606 }
7607
Hal_SC_3D_Is_LR_Sbs2Line(void * pInstance)7608 MS_BOOL Hal_SC_3D_Is_LR_Sbs2Line(void *pInstance)
7609 {
7610 if(SC_R2BYTEMSK(0, REG_SC_BK23_53_L, BIT(15)))
7611 {
7612 return TRUE;
7613 }
7614 else
7615 {
7616 return FALSE;
7617 }
7618 }
7619
Hal_SC_3D_SetLRChgMode(void * pInstance,HAL_SC_3D_LRCHGMODE eLRChgMode)7620 void Hal_SC_3D_SetLRChgMode(void *pInstance, HAL_SC_3D_LRCHGMODE eLRChgMode)
7621 {
7622 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7623 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7624 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, eLRChgMode, BIT(1)|BIT(0));
7625 }
7626
7627 // 0: L is the first frame, 1: R is the first frame
Hal_SC_3D_SetInitialLRIndex(void * pInstance,MS_BOOL bRFirst)7628 void Hal_SC_3D_SetInitialLRIndex(void *pInstance, MS_BOOL bRFirst)
7629 {
7630 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7631 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7632 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, (bRFirst==TRUE)?BIT(4):0, BIT(4));
7633 }
7634
7635 // Split 1 frame into 2 frames
Hal_SC_3D_SetSplitHalf(void * pInstance,MS_BOOL bEnable)7636 void Hal_SC_3D_SetSplitHalf(void *pInstance, MS_BOOL bEnable)
7637 {
7638 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7639 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7640 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, (bEnable==TRUE)?BIT(8):0, BIT(8));
7641 }
7642
Hal_SC_set_frcm_to_FD_mask(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7643 void Hal_SC_set_frcm_to_FD_mask(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7644 {
7645 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7646 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7647 if (eWindow == MAIN_WINDOW)
7648 {
7649 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(2):0, BIT(2));
7650 }
7651 else
7652 {
7653 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(10):0, BIT(10));
7654 }
7655 }
7656
Hal_SC_3D_set_top_win_6Tap(void * pInstance,MS_BOOL bEnable)7657 void Hal_SC_3D_set_top_win_6Tap(void *pInstance, MS_BOOL bEnable)
7658 {
7659 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7660 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7661 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_23_L, (bEnable==TRUE)?BIT(10):0, BIT(10)); //force top window using 6line
7662 }
7663
Hal_SC_3D_SetActiveVideoHeight(void * pInstance,MS_U16 u16VideoSize)7664 void Hal_SC_3D_SetActiveVideoHeight(void *pInstance, MS_U16 u16VideoSize)
7665 {
7666 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7667 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7668
7669 #if _ENABLE_SW_DS
7670 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7671 {
7672 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_65_L,u16VideoSize,DS_IP);
7673 }
7674 else
7675 #endif
7676 {
7677 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_65_L, u16VideoSize, 0x1FFF);//v_active region
7678 }
7679 }
7680
7681 // 0 for blank area 0
7682 //v blanking between field1&field2 or field3&field4
Hal_SC_3D_SetActiveBlankSize0(void * pInstance,MS_U16 u16BlankSize)7683 void Hal_SC_3D_SetActiveBlankSize0(void *pInstance, MS_U16 u16BlankSize)
7684 {
7685 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7686 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7687 #if _ENABLE_SW_DS
7688 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7689 {
7690 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_66_L,u16BlankSize,DS_IP);
7691 }
7692 else
7693 #endif
7694 {
7695 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_66_L, u16BlankSize, 0x1FFF);
7696 }
7697 }
7698
7699 // 1 for blank area 1
7700 //v blanking between field2&field3
Hal_SC_3D_SetActiveBlankSize1(void * pInstance,MS_U16 u16BlankSize)7701 void Hal_SC_3D_SetActiveBlankSize1(void *pInstance, MS_U16 u16BlankSize)
7702 {
7703 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7704 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7705 #if _ENABLE_SW_DS
7706 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7707 {
7708 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_67_L,u16BlankSize,DS_IP);
7709 }
7710 else
7711 #endif
7712 {
7713 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_67_L, u16BlankSize, 0x1FFF);//v blanking between field1&field2 or field3&field4
7714 }
7715 }
7716
Hal_SC_3D_SetActiveVideoWidth(void * pInstance,MS_U16 u16VideoSize)7717 void Hal_SC_3D_SetActiveVideoWidth(void *pInstance, MS_U16 u16VideoSize)
7718 {
7719 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7720 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7721
7722 MS_U16 u16ActiveWidthUsrEnable = 0;
7723 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, BIT(15)) == BIT(15))
7724 {
7725 u16ActiveWidthUsrEnable = BIT(15);
7726 }
7727
7728 #if _ENABLE_SW_DS
7729 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7730 {
7731 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_7F_L,u16VideoSize | u16ActiveWidthUsrEnable,DS_IP);
7732 }
7733 else
7734 #endif
7735 {
7736 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_7F_L, u16VideoSize | u16ActiveWidthUsrEnable, 0x9FFF);//v_active region
7737 }
7738 }
7739
7740
Hal_SC_3D_SetActiveVideoHeightAfterVSD(void * pInstance,MS_U16 u16VideoSize)7741 void Hal_SC_3D_SetActiveVideoHeightAfterVSD(void *pInstance, MS_U16 u16VideoSize)
7742 {
7743 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7744 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7745
7746 MS_U16 u16Enable = BIT(15);
7747
7748 #if _ENABLE_SW_DS
7749 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7750 {
7751 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_38_L,u16VideoSize | u16Enable,DS_IP);
7752 }
7753 else
7754 #endif
7755 {
7756 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_38_L, u16VideoSize | u16Enable, 0x9FFF);
7757 }
7758 }
7759
Hal_SC_3D_SetFRCMActiveVideoHeightAfterVSD(void * pInstance,MS_U16 u16VideoSize)7760 void Hal_SC_3D_SetFRCMActiveVideoHeightAfterVSD(void *pInstance, MS_U16 u16VideoSize)
7761 {
7762 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7763 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7764
7765 MS_U16 u16Enable = BIT(15);
7766
7767 #if _ENABLE_SW_DS
7768 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7769 {
7770 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK48_38_L,u16VideoSize | u16Enable,DS_IP);
7771 }
7772 else
7773 #endif
7774 {
7775 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK48_38_L, u16VideoSize | u16Enable, 0x9FFF);
7776 }
7777 }
7778
Hal_SC_3D_SetPixelSeparationWidth(void * pInstance,MS_U16 u16VideoSize)7779 void Hal_SC_3D_SetPixelSeparationWidth(void *pInstance, MS_U16 u16VideoSize)
7780 {
7781 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7782 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7783
7784 MS_U16 u16ActiveWidthUsrEnable = 0;
7785 #if (HW_DESIGN_3D_VER >= 3)
7786 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, BIT(15)) == BIT(15))
7787 {
7788 u16ActiveWidthUsrEnable = BIT(15);
7789 }
7790 #endif
7791
7792 #if _ENABLE_SW_DS
7793 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7794 {
7795 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_6C_L,u16VideoSize | u16ActiveWidthUsrEnable,DS_IP);
7796 }
7797 else
7798 #endif
7799 {
7800 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_6C_L, u16VideoSize | u16ActiveWidthUsrEnable, 0x87FF);
7801 }
7802 }
7803
Hal_SC_3D_SetSoftware_F1VBottomEndPosition(void * pInstance,MS_U16 u16VideoSize)7804 void Hal_SC_3D_SetSoftware_F1VBottomEndPosition(void *pInstance, MS_U16 u16VideoSize)
7805 {
7806 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7807 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7808
7809 #if _ENABLE_SW_DS
7810 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7811 {
7812 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4F_L,u16VideoSize,DS_IP);
7813 }
7814 else
7815 #endif
7816 {
7817 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4F_L, u16VideoSize, 0x0FFF);
7818 }
7819 }
7820
Hal_SC_3D_SetSoftware_F2VBottomEndPosition(void * pInstance,MS_U16 u16VideoSize)7821 void Hal_SC_3D_SetSoftware_F2VBottomEndPosition(void *pInstance, MS_U16 u16VideoSize)
7822 {
7823 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7824 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7825
7826 #if _ENABLE_SW_DS
7827 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7828 {
7829 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4D_L,u16VideoSize,DS_IP);
7830 }
7831 else
7832 #endif
7833 {
7834 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4D_L, u16VideoSize, 0x0FFF);
7835 }
7836 }
7837
Hal_SC_3D_SetSoftware_F1VBottomStartPosition(void * pInstance,MS_U16 u16VideoSize)7838 void Hal_SC_3D_SetSoftware_F1VBottomStartPosition(void *pInstance, MS_U16 u16VideoSize)
7839 {
7840 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7841 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7842
7843 #if _ENABLE_SW_DS
7844 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7845 {
7846 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4E_L,u16VideoSize,DS_IP);
7847 }
7848 else
7849 #endif
7850 {
7851 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4E_L, u16VideoSize, 0x0FFF);
7852 }
7853 }
7854
Hal_SC_set_frcm_to_freeze(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7855 void Hal_SC_set_frcm_to_freeze(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7856 {
7857 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7858 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7859 if (eWindow == MAIN_WINDOW)
7860 {
7861 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(0):0, BIT(0));
7862 }
7863 else
7864 {
7865 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(8):0, BIT(8));
7866 }
7867 }
7868
Hal_SC_SetOSDDetect(void * pInstance,MS_BOOL bEnable,MS_U32 Threhold)7869 E_APIXC_ReturnValue Hal_SC_SetOSDDetect(void *pInstance, MS_BOOL bEnable, MS_U32 Threhold)
7870 {
7871 MS_U16 u16Reg = 0;
7872 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7873 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7874 if(Threhold == 0)
7875 {
7876 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L, 0x0, (BIT(15)+BMASK(11:0)));
7877 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, BIT(1), BIT(1));
7878
7879 }
7880 else
7881 {
7882 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, 0x0, BIT(1));
7883 u16Reg = ((MS_U16)Threhold*2)|(bEnable << 15);
7884 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L, u16Reg, (BIT(15)+BMASK(11:0)));
7885 }
7886 return E_APIXC_RET_OK;
7887 }
7888
Hal_SC_GetOSDDetect(void * pInstance,MS_BOOL * pbOSD)7889 E_APIXC_ReturnValue Hal_SC_GetOSDDetect(void *pInstance, MS_BOOL *pbOSD)
7890 {
7891 MS_U16 u16Reg = 0;
7892 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7893 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7894
7895 u16Reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L);
7896 *pbOSD = ((u16Reg&BIT(14))>>14);
7897 return E_APIXC_RET_OK;
7898 }
7899
Hal_SC_SetHDMI_Spliter(void * pInstance,XC_IP_SYNC_STATUS * sXC_Sync_Status,E_MUX_INPUTPORT enInputPort,SCALER_WIN eWindow)7900 void Hal_SC_SetHDMI_Spliter(void *pInstance,XC_IP_SYNC_STATUS *sXC_Sync_Status,E_MUX_INPUTPORT enInputPort ,SCALER_WIN eWindow)
7901 {
7902
7903 #if 0//SUPPORT_HDMI20
7904 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7905 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7906
7907 MS_U16 u16HDE_temp_size,u16HDE_size =0;
7908
7909 if((sXC_Sync_Status->u8SyncStatus & XC_MD_SYNC_LOSS) != XC_MD_SYNC_LOSS)
7910 {
7911 if(MDrv_HDMI_CheckHDMI20_Setting(enInputPort))
7912 {
7913 //printf("[%s][%d]HDMI 4K2K 2P mode\n", __FUNCTION__, __LINE__);
7914 if(eWindow == MAIN_WINDOW)
7915 W2BYTEMSK(0x102e02,0x0010,BMASK(7:4)); // ipmux sel=0xb
7916 else if(eWindow == SUB_WINDOW)
7917 W2BYTEMSK(0x102e02,0x0001,BMASK(3:0)); // ipmux sel=0xb
7918
7919 }
7920 else
7921 {
7922 //SUPPORT_HDMI20_420
7923 //printf("[%s][%d]HDMI 4K2K 2P mode\n", __FUNCTION__, __LINE__);
7924 //printf("[%s][%d]sXC_Sync_Status->u16Vtotal=%x, sXC_Sync_Status->u16Hperiod=%x\n",
7925 // __FUNCTION__, __LINE__, sXC_Sync_Status->u16Vtotal, sXC_Sync_Status->u16Hperiod);
7926 if((sXC_Sync_Status->u16Vtotal >= 0x8C0)
7927 &&(sXC_Sync_Status->u16Hperiod>= 0x50))
7928 {
7929 if((MDrv_HDMI_avi_infoframe_info(_BYTE_1)& 0x60) == 0x60)
7930 {
7931 //printf("@@#@@4K2K@60 420\n");
7932 // clkgen2
7933 W2BYTE(0x100a80,0x0004); // spt_l0 1: hdmi d: mhl
7934 // ipmux
7935 if(eWindow == MAIN_WINDOW)
7936 {
7937 W2BYTEMSK(0x102e02,0x00b0,BMASK(7:4)); // ipmux sel=0xb
7938 }
7939 else if(eWindow == SUB_WINDOW)
7940 {
7941 W2BYTEMSK(0x102e02,0x000b,BMASK(3:0)); // ipmux sel=0xb
7942 }
7943
7944 //BK40_SPT4k
7945 SC_W2BYTE(0, REG_SC_BK40_01_L,0x0000); // [3:0] reg_spt_ipmux_sel0
7946 // [11:8] reg_spt_ipmux_sel1
7947 SC_W2BYTE(0, REG_SC_BK40_03_L,0x0001); // [7] reg_spt_2p_oe_en [0] reg_spt_420_en
7948 SC_W2BYTE(0, REG_SC_BK40_04_L,0x0180); // [7] reg_spt_2p_oe_out_en [9] hsd_en
7949 // [8] reg_spt_2poe_out_sel 1'b0: dual ch eo in
7950 // 1'b1: dual ch LR in or 420
7951 SC_W2BYTE(0, REG_SC_BK40_30_L, 0x0003); // de_only
7952 SC_W2BYTE(0, REG_SC_BK40_0B_L, 0x0000); // gb_size
7953
7954 u16HDE_temp_size = MDrv_HDMI_GetHDE();
7955 //printf("[%s][%d]u16HDE_size=%u\n", __FUNCTION__, __LINE__,u16HDE_temp_size);
7956 if((u16HDE_temp_size >= 2028)&&(u16HDE_temp_size<= 2068))
7957 {
7958 u16HDE_size = 2048;
7959 }
7960 else //if((u16HDE_temp_size >= 1900)&&(u16HDE_temp_size<= 1940))
7961 {
7962 u16HDE_size = 1920;
7963 }
7964 SC_W2BYTE(0, REG_SC_BK40_08_L, u16HDE_size); // de_in_size
7965 SC_W2BYTE(0, REG_SC_BK40_0A_L, u16HDE_size); // de_out_with_gb_size
7966
7967 SC_W2BYTE(0, REG_SC_BK40_20_L, 0x0000); // ra
7968 SC_W2BYTE(0, REG_SC_BK40_21_L, u16HDE_size/2-2); //
7969 SC_W2BYTE(0, REG_SC_BK40_22_L, 0x0001);
7970 SC_W2BYTE(0, REG_SC_BK40_23_L, u16HDE_size/2-1);
7971
7972 SC_W2BYTE(0, REG_SC_BK40_24_L, 0x0000); // wa
7973 SC_W2BYTE(0, REG_SC_BK40_25_L, u16HDE_size/2-2);
7974 SC_W2BYTE(0, REG_SC_BK40_26_L, 0x0001);
7975 SC_W2BYTE(0, REG_SC_BK40_27_L, u16HDE_size/2-1);
7976 }
7977 else
7978 {
7979 //printf("@@#@@4K2K@30\n");
7980 /// for 4K2K@30Hz
7981 if(eWindow == MAIN_WINDOW)
7982 {
7983 W2BYTEMSK(0x102e02,0x0010,BMASK(7:4)); // ipmux sel=0xb
7984 }
7985 else if(eWindow == SUB_WINDOW)
7986 {
7987 W2BYTEMSK(0x102e02,0x0001,BMASK(3:0)); // ipmux sel=0xb
7988 }
7989 }
7990 }
7991 }
7992 }
7993 #endif
7994 }
7995
Hal_SC_Set_2pmode(void * pInstance,MS_BOOL benable_IP2p,MS_BOOL benable_OP2p,MS_BOOL benable_bypass_all_2p,SCALER_WIN eWindow)7996 void Hal_SC_Set_2pmode(void *pInstance,MS_BOOL benable_IP2p,MS_BOOL benable_OP2p,MS_BOOL benable_bypass_all_2p,SCALER_WIN eWindow)
7997 {
7998 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7999 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8000
8001 if (eWindow == MAIN_WINDOW)
8002 {
8003 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L,(benable_IP2p ? BIT(15):0), BIT(15));//reg_sprange_hdc_2p
8004 if (psXCInstPri->u32DeviceID == 0)
8005 {
8006 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_01_L,(benable_OP2p ? BIT(1):0), BIT(1));//reg_opm_2p_mode
8007 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_04_L,(benable_bypass_all_2p ? BIT(6):0), BIT(6));//reg_bypass_all_2p_f2
8008 }
8009 }
8010 }
8011
MHal_SC_set_manual_rbank_switch_cnt(void * pInstance,MS_BOOL bEnable,MS_U16 u16SwitchCnt,SCALER_WIN eWindow)8012 void MHal_SC_set_manual_rbank_switch_cnt(void *pInstance, MS_BOOL bEnable, MS_U16 u16SwitchCnt, SCALER_WIN eWindow)
8013 {
8014 if (eWindow >= MAX_WINDOW)
8015 {
8016 printf("unsupported eWindow, return!\n");
8017 return;
8018 }
8019
8020 if( eWindow == MAIN_WINDOW)
8021 {
8022 // these two registers must be set simultaneously for this feature to work
8023 // frame rate convert dependence with IP write line count
8024 SC_W2BYTEMSK(0,REG_SC_BK12_05_L, bEnable? BIT(3):0, BIT(3));
8025 // frame rate convert dependence with IP write line count FULL
8026 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15));
8027
8028 // set specific line count according to when you will change rbank switch
8029 // this line count starts at VDE rising edge, ends at u16SwitchCnt
8030 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF);
8031 }
8032 else
8033 {
8034 // these two registers must be set simultaneously for this feature to work
8035 // frame rate convert dependence with IP write line count
8036 SC_W2BYTEMSK(0,REG_SC_BK12_45_L, bEnable? BIT(3):0, BIT(3));
8037 // frame rate convert dependence with IP write line count FULL
8038 SC_W2BYTEMSK(0,REG_SC_BK11_58_L, bEnable? BIT(15):0, BIT(15));
8039
8040 // set specific line count according to when you will change rbank switch
8041 // this line count starts at VDE rising edge, ends at u16SwitchCnt
8042 SC_W2BYTEMSK(0,REG_SC_BK11_58_L, u16SwitchCnt, 0x1FFF);
8043 }
8044 }
8045
8046 #ifdef SUPPORT_BWD
_HAL_SC_BWR_set_base_address(void * pInstance,MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex,SCALER_WIN eWindow)8047 static void _HAL_SC_BWR_set_base_address(void *pInstance, MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex, SCALER_WIN eWindow)
8048 {
8049 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8050 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8051 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8052 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8053
8054 E_XC_BWR_MEM_CONFIG u8Memtype = E_XC_BWR_MEM_CONFIG_1;
8055 E_XC_BWR_MEM_CFG_BPP_TYPE eBPPType = E_XC_BWR_MEM_CFG_BPP_24;
8056 for(u8Memtype=E_XC_BWR_MEM_CONFIG_1;u8Memtype<E_XC_BWR_MEM_CONFIG_Max;u8Memtype++)
8057 {
8058 if(u16MemCfgValue == gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].u16BWR_MEM_CFG_VALUE)
8059 {
8060 eBPPType = gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].eBitPerPixelType;
8061 break;
8062 }
8063 }
8064
8065 #ifdef UFO_XC_SUPPORT_DUAL_MIU
8066 if (IsEnableDualMode(eWindow))
8067 {
8068 //SCMI: IPM address 0
8069 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
8070 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
8071 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x48 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>00), 0xFFFF);
8072 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x49 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>16), 0x03FF);
8073 //SCMI: IPM address 1
8074 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
8075 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
8076 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x58 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>00), 0xFFFF);
8077 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x59 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>16), 0x03FF);
8078 //SCMI: OPM address 0
8079 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
8080 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
8081 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x68 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>00), 0xFFFF);
8082 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x69 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>16), 0x03FF);
8083 //SCMI: OPM address 1
8084 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
8085 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
8086 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x78 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0xFFFF);
8087 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x79 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x03FF);
8088 }
8089 else
8090 #endif
8091 {
8092 //SCMI: IPM address 0
8093 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
8094 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
8095 //SCMI: IPM address 1
8096 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
8097 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
8098 //SCMI: OPM address 0
8099 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
8100 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
8101 //SCMI: OPM address 1
8102 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
8103 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
8104 }
8105 }
8106
_HAL_SC_BWR_set_vlen(void * pInstance,SCALER_WIN eWindow)8107 void _HAL_SC_BWR_set_vlen(void * pInstance, SCALER_WIN eWindow)
8108 {
8109 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8110 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8111
8112 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8113 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8114 //update BWR Configuration vlen,IP 3D source: LA
8115 if(MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE)
8116 {
8117 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
8118 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_36_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
8119 }
8120 else
8121 {
8122 //update BWR Configuration vlen, VSD
8123 if(gSrcInfo[eWindow].bPreV_ScalingDown)
8124 {
8125 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
8126 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_36_L, gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
8127 }
8128 else
8129 {
8130 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, 0, BIT(15));
8131 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_36_L, 0, BIT(15));
8132 }
8133 }
8134 //update BWR Configuration vlen,OP 3D output: LA
8135 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8136 {
8137 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3E_L, BIT(15) | (gSrcInfo[eWindow].u16V_Length*2), BIT(15) | 0x1FFF);
8138 }
8139 else
8140 {
8141 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3E_L, 0, BIT(15));
8142 }
8143
8144 }
8145
_HAL_SC_BWR_set_3d_mode(void * pInstance,SCALER_WIN eWindow)8146 static void _HAL_SC_BWR_set_3d_mode(void * pInstance, SCALER_WIN eWindow)
8147 {
8148 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8149
8150 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8151 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8152 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8153 //BWR 422 to 420 set drop mode register
8154 if((MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE) && (gSrcInfo[eWindow].stCapWin.width > 1920))
8155 {
8156 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_38_L, BIT(7), BIT(7));
8157 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3A_L, 0, BIT(2));
8158 }
8159
8160 //BWR 422 to 420 set TB mode register
8161 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM)
8162 {
8163 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3A_L, BIT(4), BIT(4));
8164 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(11));
8165 }
8166
8167 //OP1 must turn off initial process
8168 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8169 {
8170 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,BIT(12) ,BIT(12));
8171 }
8172 else
8173 {
8174 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,0 ,BIT(12));
8175 }
8176 }
8177
_HAL_SC_BWR_set_base_address_burst(void * pInstance,MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex,SCALER_WIN eWindow)8178 static void _HAL_SC_BWR_set_base_address_burst(void *pInstance, MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex, SCALER_WIN eWindow)
8179 {
8180 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8181 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8182 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8183 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8184
8185 E_XC_BWR_MEM_CONFIG u8Memtype = E_XC_BWR_MEM_CONFIG_1;
8186 E_XC_BWR_MEM_CFG_BPP_TYPE eBPPType = E_XC_BWR_MEM_CFG_BPP_24;
8187 for(u8Memtype=E_XC_BWR_MEM_CONFIG_1;u8Memtype<E_XC_BWR_MEM_CONFIG_Max;u8Memtype++)
8188 {
8189 if(u16MemCfgValue == gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].u16BWR_MEM_CFG_VALUE)
8190 {
8191 eBPPType = gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].eBitPerPixelType;
8192 break;
8193 }
8194 }
8195
8196 #ifdef UFO_XC_SUPPORT_DUAL_MIU
8197 if (IsEnableDualMode(eWindow))
8198 {
8199 //SCMI: IPM address 0
8200 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
8201 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
8202
8203 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x48 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>00), 0xFFFF);
8204 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x49 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>16), 0x03FF);
8205
8206 //SCMI: IPM address 1
8207 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
8208 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
8209
8210 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x58 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>00), 0xFFFF);
8211 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x59 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>16), 0x03FF);
8212
8213 //SCMI: OPM address 0
8214 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
8215 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
8216
8217 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x68 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>00), 0xFFFF);
8218 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x69 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>16), 0x03FF);
8219
8220 //SCMI: OPM address 1
8221 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
8222 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
8223
8224 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x78 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0xFFFF);
8225 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x79 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x03FF);
8226 }
8227 else // Disbale dual
8228 #endif
8229 {
8230 //SCMI: IPM address 0
8231 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
8232 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
8233
8234 //SCMI: IPM address 1
8235 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
8236 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
8237
8238 //SCMI: OPM address 0
8239 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
8240 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
8241
8242 //SCMI: OPM address 1
8243 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
8244 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
8245 }
8246 }
8247
_HAL_SC_BWR_set_vlen_burst(void * pInstance,SCALER_WIN eWindow)8248 static void _HAL_SC_BWR_set_vlen_burst(void * pInstance, SCALER_WIN eWindow)
8249 {
8250 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8251 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8252
8253 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8254 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8255 //update BWR Configuration vlen,IP 3D source: LA
8256 if(MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE)
8257 {
8258 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
8259 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_36_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
8260 }
8261 else
8262 {
8263 //update BWR Configuration vlen, VSD
8264 if(gSrcInfo[eWindow].bPreV_ScalingDown)
8265 {
8266 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
8267 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_36_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
8268 }
8269 else
8270 {
8271 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, 0, BIT(15));
8272 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_36_L, 0, BIT(15));
8273 }
8274 }
8275 //update BWR Configuration vlen,OP 3D output: LA
8276 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8277 {
8278 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3E_L, BIT(15) | (gSrcInfo[eWindow].u16V_Length*2), BIT(15) | 0x1FFF);
8279 }
8280 else
8281 {
8282 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3E_L, 0, BIT(15));
8283 }
8284 }
8285
_HAL_SC_BWR_set_3d_mode_burst(void * pInstance,SCALER_WIN eWindow)8286 static void _HAL_SC_BWR_set_3d_mode_burst(void * pInstance, SCALER_WIN eWindow)
8287 {
8288 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8289
8290 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8291
8292 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8293 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8294
8295 //BWR 422 to 420 set drop mode register
8296 if((MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE) && (gSrcInfo[eWindow].stCapWin.width > 1920))
8297 {
8298 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_38_L, BIT(7), BIT(7));
8299 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3A_L, 0, BIT(2));
8300 }
8301
8302 //BWR 422 to 420 set TB mode register
8303 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM)
8304 {
8305 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3A_L, BIT(4),BIT(4));
8306 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, 0, BIT(11));
8307 }
8308
8309 //OP1 must turn off initial process
8310 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
8311 {
8312 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(12), BIT(12));
8313 }
8314 else
8315 {
8316 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(12));
8317 }
8318 }
8319 #endif
8320
HAL_SC_set_bwr_config_burst(void * pInstance,void * pstParam,SCALER_WIN eWindow)8321 MS_BOOL HAL_SC_set_bwr_config_burst(void *pInstance, void *pstParam, SCALER_WIN eWindow)
8322 {
8323 #ifdef SUPPORT_BWD
8324 MS_U16 u16BwrMemCfgTmp = 0;
8325 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8326 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8327 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8328 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8329
8330 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_17_L, 0xFFFF);
8331 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x000F) >> 0, E_XC_BWR_MME_CFG_INDEX_0, eWindow);
8332 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x00F0) >> 4, E_XC_BWR_MME_CFG_INDEX_1, eWindow);
8333 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x0F00) >> 8, E_XC_BWR_MME_CFG_INDEX_2, eWindow);
8334 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0xF000) >> 12, E_XC_BWR_MME_CFG_INDEX_3, eWindow);
8335 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_16_L, 0xF);
8336 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_28_L, u16BwrMemCfgTmp, 0x0F);
8337 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_29_L, u16BwrMemCfgTmp, 0x0F);
8338
8339 _HAL_SC_BWR_set_vlen_burst(pInstance, eWindow);
8340 _HAL_SC_BWR_set_3d_mode_burst(pInstance, eWindow);
8341
8342 MDrv_XC_MLoad_Fire(pInstance, TRUE);
8343 return TRUE;
8344 #else
8345 return FALSE;
8346 #endif
8347 }
8348
HAL_SC_set_bwr_config(void * pInstance,void * pstParam,SCALER_WIN eWindow)8349 MS_BOOL HAL_SC_set_bwr_config(void *pInstance, void *pstParam, SCALER_WIN eWindow)
8350 {
8351 #ifdef SUPPORT_BWD
8352 MS_U16 u16BwrMemCfgTmp = 0;
8353 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8354 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8355 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8356 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8357
8358 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_17_L, 0xFFFF);
8359 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x000F) >> 0, E_XC_BWR_MME_CFG_INDEX_0, eWindow);
8360 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x00F0) >> 4, E_XC_BWR_MME_CFG_INDEX_1, eWindow);
8361 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x0F00) >> 8, E_XC_BWR_MME_CFG_INDEX_2, eWindow);
8362 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0xF000) >> 12, E_XC_BWR_MME_CFG_INDEX_3, eWindow);
8363 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_16_L, 0xF);
8364 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_28_L, u16BwrMemCfgTmp, 0x0F);
8365 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_29_L, u16BwrMemCfgTmp, 0x0F);
8366
8367 _HAL_SC_BWR_set_vlen(pInstance, eWindow);
8368 _HAL_SC_BWR_set_3d_mode(pInstance, eWindow);
8369 return TRUE;
8370 #else
8371 return FALSE;
8372 #endif
8373 }
8374
Hal_SC_AdjustIpmWriteLimite(void * pInstance,MS_BOOL bIsLeft,MS_BOOL bNeedSwap,SCALER_WIN eWindow)8375 MS_BOOL Hal_SC_AdjustIpmWriteLimite(void *pInstance, MS_BOOL bIsLeft, MS_BOOL bNeedSwap, SCALER_WIN eWindow)
8376 {
8377 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8378 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8379 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8380 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8381 MS_PHY u32WLimitBase = 0x00;
8382 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
8383 {
8384 return FALSE;
8385 }
8386
8387 if (bIsLeft == TRUE)
8388 {
8389 if (bNeedSwap == TRUE)
8390 {
8391 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[eWindow]) / BYTE_PER_WORD - 1) | F2_WRITE_LIMIT_EN;;
8392 MDrv_SC_set_dual_write_limit(pInstance, u32WLimitBase , eWindow);
8393 }
8394 else
8395 {
8396 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[eWindow]) / BYTE_PER_WORD - 1) | F2_WRITE_LIMIT_EN;
8397 MDrv_SC_set_write_limit(pInstance, u32WLimitBase , eWindow);
8398 }
8399 }
8400 else
8401 {
8402 if (bNeedSwap == TRUE)
8403 {
8404 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBufSize[eWindow]) / BYTE_PER_WORD - 1) ;
8405 MDrv_SC_set_write_limit(pInstance, u32WLimitBase , eWindow);
8406 }
8407 else
8408 {
8409 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBufSize[eWindow]) / BYTE_PER_WORD - 1) ;
8410 MDrv_SC_set_dual_write_limit(pInstance, u32WLimitBase , eWindow);
8411 }
8412 }
8413 return TRUE;
8414 }
8415
Hal_SC_3D_enable_black_edge(void * pInstance,MS_BOOL b2DTo3D)8416 void Hal_SC_3D_enable_black_edge(void *pInstance, MS_BOOL b2DTo3D)
8417 {
8418 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8419 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8420 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8421 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8422
8423 MS_U16 u16GarbageWidth = 0;
8424 MS_U16 u16BlackBarEnd_L = 0;
8425 MS_U16 u16BlackBarStart_R = 0;
8426 MS_U16 u16FrameColorWidth = pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16H_DisStart - SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L);
8427 MS_U16 u16DispWinWidth = pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16H_DisEnd - pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16H_DisStart + 1;
8428
8429 if(b2DTo3D)
8430 {
8431 u16GarbageWidth = pXCResourcePrivate->stdrvXC_3D._st3DHw2DTo3DPara.u16Offset>>3; //offset
8432 u16GarbageWidth = (u16GarbageWidth > 16)?(u16GarbageWidth - 16):(16 - u16GarbageWidth);
8433 u16GarbageWidth = u16GarbageWidth + (pXCResourcePrivate->stdrvXC_3D._st3DHw2DTo3DPara.u16Gain + 1) / 2;//gain
8434 }
8435 else
8436 {
8437 if(0 == pXCResourcePrivate->stdrvXC_3D._u163DHShift)
8438 {
8439 u16GarbageWidth = pXCResourcePrivate->stdrvXC_3D._u163DHShift;
8440 }
8441 else if(pXCResourcePrivate->stdrvXC_3D._u163DHShift > 112)
8442 {
8443 u16GarbageWidth = pXCResourcePrivate->stdrvXC_3D._u163DHShift - 112;//_u163DHShift = value on UI + 112
8444 }
8445 else
8446 {
8447 u16GarbageWidth = 0;
8448 printf("[%s,%5d] ERROR: invalid value of gain\n",__FUNCTION__,__LINE__);
8449 }
8450
8451 if((0 == u16GarbageWidth) || (16 == u16GarbageWidth))
8452 {
8453 u16GarbageWidth = 0;
8454 }
8455 else
8456 {
8457 u16GarbageWidth = (u16GarbageWidth > 16)?(u16GarbageWidth - 16):(16 - u16GarbageWidth);
8458 }
8459
8460 }
8461
8462 if(u16DispWinWidth > 1920)
8463 {
8464 u16GarbageWidth = u16GarbageWidth* 2;
8465 }
8466 else if(u16DispWinWidth > 960)
8467 {
8468 u16GarbageWidth = u16GarbageWidth;
8469 }
8470 else if(u16DispWinWidth > 480)
8471 {
8472 u16GarbageWidth = u16GarbageWidth / 2;
8473 }
8474 else
8475 {
8476 u16GarbageWidth = u16GarbageWidth / 4;
8477 }
8478
8479 u16BlackBarEnd_L = (u16FrameColorWidth + u16GarbageWidth) /2;//manhattan 2P mode
8480 u16BlackBarStart_R = (u16FrameColorWidth + u16DispWinWidth - u16GarbageWidth) / 2;//manhattan 2P mode
8481
8482 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_65_L, 0x8000, 0x8000);//enable principal black-bar
8483 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_4B_L, 0x0002, 0x0002);//enable left Right black-bar
8484 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_63_L, u16BlackBarEnd_L, 0xFFF);//Left black-bar end
8485 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_62_L, u16BlackBarStart_R, 0xFFF);//Right black-bar start
8486 }
8487
8488 #if FRC_INSIDE
MHal_XC_FRCR2_IP_PatchISR(SC_INT_SRC eIntNum,void * pParam)8489 static void MHal_XC_FRCR2_IP_PatchISR(SC_INT_SRC eIntNum, void * pParam)
8490 {
8491 void *pInstance = pu32XCInst_private;
8492 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8493 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8494 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8495 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8496
8497 MDrv_WriteByteMask(0x400640, 0x02, 0x02);
8498 MsOS_DelayTaskUs(10);
8499 MDrv_WriteByteMask(0x400640, 0x00, 0x02);
8500 }
8501
MHal_XC_FRCR2_IP_Patch(void * pInstance,SCALER_WIN eWindow)8502 void MHal_XC_FRCR2_IP_Patch(void *pInstance, SCALER_WIN eWindow)
8503 {
8504 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8505 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8506 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8507 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8508
8509 if(eWindow ==MAIN_WINDOW)
8510 {
8511 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL))
8512 {
8513 //enable ISR
8514 //FIXME: PATCH
8515 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL);
8516 }
8517 }
8518
8519 }
MHal_XC_FRCR2_IP_PatchClose(void * pInstance,SCALER_WIN eWindow)8520 void MHal_XC_FRCR2_IP_PatchClose(void *pInstance, SCALER_WIN eWindow)
8521 {
8522 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8523 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8524 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8525 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8526
8527 if(eWindow ==MAIN_WINDOW)
8528 {
8529 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_F2_IPVS_SB, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL))
8530 {
8531 //Disable ISR
8532 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_F2_IPVS_SB, MHal_XC_FRCR2_IP_PatchISR, (void *)NULL);
8533 }
8534 }
8535
8536 }
8537
MHal_XC_FRCR2_OP_PatchISR(SC_INT_SRC eIntNum,void * pParam)8538 static void MHal_XC_FRCR2_OP_PatchISR(SC_INT_SRC eIntNum, void * pParam)
8539 {
8540 void *pInstance = pu32XCInst_private;
8541 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8542 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8543 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8544 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8545
8546 MDrv_WriteByteMask(0x400640, 0x04, 0x04);
8547 MsOS_DelayTaskUs(10);
8548 MDrv_WriteByteMask(0x400640, 0x00, 0x04);
8549 }
8550
MHal_XC_FRCR2_OP_Patch(void * pInstance,SCALER_WIN eWindow)8551 void MHal_XC_FRCR2_OP_Patch(void *pInstance, SCALER_WIN eWindow)
8552 {
8553 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8554 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8555 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8556 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8557
8558 if(eWindow ==MAIN_WINDOW)
8559 {
8560 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL))
8561 {
8562 //enable ISR
8563 //FIXME: PATCH
8564 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL);
8565 }
8566 }
8567
8568 }
MHal_XC_FRCR2_OP_PatchClose(void * pInstance,SCALER_WIN eWindow)8569 void MHal_XC_FRCR2_OP_PatchClose(void *pInstance, SCALER_WIN eWindow)
8570 {
8571 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8572 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8573 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8574 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8575
8576 if(eWindow ==MAIN_WINDOW)
8577 {
8578 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL))
8579 {
8580 //Disable ISR
8581 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_FRCR2_OP_PatchISR, (void *)NULL);
8582 }
8583 }
8584 }
8585
Hal_SC_3D_enable_FALLRR_out(void * pInstance,MS_BOOL bEnable)8586 void Hal_SC_3D_enable_FALLRR_out(void *pInstance, MS_BOOL bEnable)
8587 {
8588 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8589 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8590
8591 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_33_L, (bEnable==TRUE)?BIT(8):0, BIT(8));//OPM LLRR
8592 }
8593 #endif
8594
Hal_SC_3D_Adjust_PreHVscaling_SaveBW(void * pInstance,XC_InternalStatus * pSrcInfo,MS_BOOL * pb3DPreHScaling,MS_BOOL * pb3DPreVScaling,MS_BOOL bForcePreHScalingDown,MS_BOOL bForcePreVScalingDown,SCALER_WIN eWindow)8595 void Hal_SC_3D_Adjust_PreHVscaling_SaveBW(void *pInstance, XC_InternalStatus *pSrcInfo, MS_BOOL *pb3DPreHScaling,MS_BOOL *pb3DPreVScaling,MS_BOOL bForcePreHScalingDown,MS_BOOL bForcePreVScalingDown,SCALER_WIN eWindow)
8596 {
8597 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8598 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8599 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8600 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8601
8602 if((pXCResourcePrivate->stdrvXC_3D._eInput3DMode[eWindow] == E_XC_3D_INPUT_FRAME_PACKING))
8603 {
8604 if(pXCResourcePrivate->stdrvXC_3D._eOutput3DMode != E_XC_3D_OUTPUT_FRAME_ALTERNATIVE)
8605 {
8606 *pb3DPreHScaling = TRUE;
8607 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8608 if((pSrcInfo->stDispWin.width >= 1920)
8609 && (pSrcInfo->stDispWin.height >= 1080))
8610 {
8611 pSrcInfo->Status2.u16PreHCusScalingDst = MAX(640, (MS_U32)MIN(1920, pSrcInfo->stDispWin.width) * 2 / 3);
8612 }
8613 else
8614 {
8615 pSrcInfo->Status2.u16PreHCusScalingDst = MAX(640, (MS_U32)MIN(1920, pSrcInfo->stDispWin.width) / 2);
8616 }
8617 }
8618 else// FA out
8619 {
8620 if((pXCResourcePrivate->stdrvXC_3D._bFALLRRToFA) && (pSrcInfo->stCapWin.width == DOUBLEHD_1080X2P_HSIZE))//output FA_LLRR for 4k0.5k@240Hz
8621 {
8622 *pb3DPreHScaling = TRUE;
8623 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8624 pSrcInfo->Status2.u16PreHCusScalingDst = MAX(640, (MS_U32)MIN(1920, pSrcInfo->stDispWin.width) / 2);
8625 }
8626 }
8627 }
8628 else if((pXCResourcePrivate->stdrvXC_3D._eInput3DMode[eWindow] == E_XC_3D_INPUT_FRAME_ALTERNATIVE) && (pXCResourcePrivate->stdrvXC_3D._eOutput3DMode != E_XC_3D_OUTPUT_FRAME_ALTERNATIVE) &&(pSrcInfo->stCapWin.width >= 1280)
8629 && (MDrv_ReadRegBit(REG_CKG_FCLK, CKG_FCLK_MASK) < 24))//fclk < 320MHz may have fclk issue for fi
8630 {
8631 *pb3DPreHScaling = TRUE;
8632 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8633 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width >= 2 * pSrcInfo->stDispWin.width)
8634 {
8635 pSrcInfo->Status2.u16PreHCusScalingDst = MIN(960, pSrcInfo->stDispWin.width);
8636 }
8637 else
8638 {
8639 pSrcInfo->Status2.u16PreHCusScalingDst = MIN(1280, pSrcInfo->stDispWin.width);
8640 }
8641 }
8642 else
8643 {
8644 if(bForcePreHScalingDown)
8645 {
8646 *pb3DPreHScaling = FALSE;
8647 pSrcInfo->Status2.u16PreHCusScalingSrc = pSrcInfo->stCapWin.width;
8648 pSrcInfo->Status2.u16PreHCusScalingDst = pSrcInfo->u16H_SizeAfterPreScaling;
8649 }
8650
8651 if(bForcePreVScalingDown)
8652 {
8653 pb3DPreVScaling = FALSE;
8654 pSrcInfo->Status2.u16PreVCusScalingSrc = pSrcInfo->stCapWin.height;
8655 pSrcInfo->Status2.u16PreVCusScalingDst = pSrcInfo->u16V_SizeAfterPreScaling;
8656 }
8657 }
8658
8659 }
8660
8661 #ifdef UFO_XC_AUTO_DOWNLOAD
_Hal_XC_Set_Auto_Download_WorkMode(MS_U32 u32DeviceID,MS_U32 u32RegAddr,MS_U8 u8Bit,EN_XC_AUTODOWNLOAD_MODE enMode)8662 static E_APIXC_ReturnValue _Hal_XC_Set_Auto_Download_WorkMode(MS_U32 u32DeviceID, MS_U32 u32RegAddr, MS_U8 u8Bit, EN_XC_AUTODOWNLOAD_MODE enMode)
8663 {
8664 switch (enMode)
8665 {
8666 case E_XC_AUTODOWNLOAD_TRIGGER_MODE:
8667 {
8668 SC_W2BYTEMSK(u32DeviceID, u32RegAddr, 0, BIT(u8Bit));
8669 break;
8670 }
8671 case E_XC_AUTODOWNLOAD_ENABLE_MODE:
8672 {
8673 SC_W2BYTEMSK(u32DeviceID, u32RegAddr, 1 << u8Bit, BIT(u8Bit));
8674 break;
8675 }
8676 default:
8677 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8678 }
8679
8680 return E_APIXC_RET_OK;
8681 }
8682
MHal_XC_AutoDownload_Config(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_PHY phyBaseAddr,EN_XC_AUTODOWNLOAD_MODE enMode)8683 E_APIXC_ReturnValue MHal_XC_AutoDownload_Config(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_PHY phyBaseAddr, EN_XC_AUTODOWNLOAD_MODE enMode)
8684 {
8685 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8686 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8687
8688 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8689 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8690
8691 switch(enClient)
8692 {
8693 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
8694 {
8695 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = 0xFFFFFFFF;
8696 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = 0;
8697 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].enMode = enMode;
8698
8699 //set baseaddr
8700 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_29_L, phyBaseAddr & 0x0000FFFF);
8701 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_2A_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8702
8703 //set work mode
8704 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L, 1, enMode);
8705 break;
8706 }
8707 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
8708 {
8709 //set baseaddr
8710 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_02_L, phyBaseAddr & 0x0000FFFF);
8711 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_03_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8712
8713 //set work mode
8714 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 3, enMode);
8715 break;
8716 }
8717 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
8718 {
8719 //set baseaddr
8720 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_12_L, phyBaseAddr & 0x0000FFFF);
8721 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_13_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8722
8723 //set work mode
8724 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 6, enMode);
8725 break;
8726 }
8727 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
8728 {
8729 //set baseaddr
8730 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_16_L, phyBaseAddr & 0x0000FFFF);
8731 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_17_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8732
8733 //set work mode
8734 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 15, enMode);
8735 break;
8736 }
8737 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
8738 {
8739 //set baseaddr
8740 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
8741 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8742
8743 //set work mode
8744 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
8745 break;
8746 }
8747 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
8748 {
8749 //set baseaddr
8750 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
8751 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8752
8753 //set work mode
8754 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
8755 break;
8756 }
8757 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
8758 {
8759 //set baseaddr
8760 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
8761 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8762
8763 //set work mode
8764 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
8765 break;
8766 }
8767 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
8768 {
8769 //set baseaddr
8770 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_06_L, phyBaseAddr & 0x0000FFFF);
8771 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_07_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8772
8773 //set work mode
8774 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 5, enMode);
8775 break;
8776 }
8777 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
8778 {
8779 //set baseaddr
8780 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_23_L, phyBaseAddr & 0x0000FFFF);
8781 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_24_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8782
8783 //set work mode
8784 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_22_L, 1, enMode);
8785 break;
8786 }
8787 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
8788 {
8789 //set baseaddr
8790 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_33_L, phyBaseAddr & 0x0000FFFF);
8791 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_34_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
8792
8793 //set work mode
8794 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_32_L, 1, enMode);
8795 break;
8796 }
8797 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
8798 {
8799 return E_APIXC_RET_FAIL;
8800 }
8801 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
8802 {
8803 return E_APIXC_RET_FAIL;
8804 }
8805 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
8806 {
8807 return E_APIXC_RET_FAIL;
8808 }
8809 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
8810 default:
8811 {
8812 return E_APIXC_RET_FAIL;
8813 }
8814
8815 }
8816
8817 return E_APIXC_RET_OK;
8818 }
8819
MHal_XC_AutoDownload_Fire(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient)8820 E_APIXC_ReturnValue MHal_XC_AutoDownload_Fire(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient)
8821 {
8822 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8823 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8824
8825 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8826 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8827
8828 switch(enClient)
8829 {
8830 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
8831 {
8832 MS_PHY phyBaseAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].phyBaseAddr;
8833 MS_U32 u32Depth = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth;
8834 MS_VIRT* pVirtBaseAddr = (MS_VIRT *)MS_PA2KSEG1(phyBaseAddr);
8835 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
8836 MS_U32 u32StartAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr;
8837 pu8BaseAddr += 16 * u32StartAddr;
8838
8839 // set baseaddr
8840 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_29_L, (MS_PHY)MS_VA2PA((MS_VIRT)pu8BaseAddr) & 0x0000FFFF);
8841 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_2A_L, (MS_PHY)(MS_VA2PA((MS_VIRT)pu8BaseAddr) >> 16 & 0x0000FFFF), 0x07FF);
8842
8843 // set depth
8844 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_2B_L, u32Depth);
8845 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_2C_L, u32Depth);
8846
8847 // enable auto download
8848 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L, 1, BIT(0));
8849
8850 EN_XC_AUTODOWNLOAD_MODE enMode = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].enMode;
8851 if (enMode == E_XC_AUTODOWNLOAD_TRIGGER_MODE)
8852 {
8853 //check auto download done
8854 MS_U32 u32Delayms = 0;
8855 while(((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L) & 0x0001) != 0) && u32Delayms < 500)
8856 {
8857 MsOS_DelayTask(1);
8858 u32Delayms++;
8859 }
8860
8861 // clear buffer
8862 unsigned int i = 0;
8863 for (i = 0; i < u32Depth; i++)
8864 {
8865 CLEAR_HDR_DATA_FORMAT_1(pu8BaseAddr + i * 16);
8866 }
8867 if (u32Delayms >= 500)
8868 {
8869 printf("Check auto download done timeout.\n");
8870 }
8871 }
8872
8873 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = 0xFFFFFFFF;
8874 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = 0;
8875 break;
8876 }
8877 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
8878 {
8879 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1, BIT(0));
8880 break;
8881 }
8882 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
8883 {
8884 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_11_L, 1, BIT(0));
8885 break;
8886 }
8887 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
8888 {
8889 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_11_L, 1 << 2, BIT(2));
8890 break;
8891 }
8892 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
8893 {
8894 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1 << 1, BIT(1));
8895 break;
8896 }
8897 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
8898 {
8899 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_21_L, 1, BIT(0));
8900 break;
8901 }
8902 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
8903 {
8904 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_21_L, 1 << 1, BIT(1));
8905 break;
8906 }
8907 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
8908 {
8909 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1 << 2, BIT(2));
8910 break;
8911 }
8912 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
8913 {
8914 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_22_L, 1, BIT(0));
8915 break;
8916 }
8917 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
8918 {
8919 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_32_L, 1, BIT(0));
8920 break;
8921 }
8922 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
8923 {
8924 return E_APIXC_RET_FAIL;
8925 }
8926 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
8927 {
8928 return E_APIXC_RET_FAIL;
8929 }
8930 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
8931 {
8932 return E_APIXC_RET_FAIL;
8933 }
8934 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
8935 default:
8936 {
8937 return E_APIXC_RET_FAIL;
8938 }
8939
8940 }
8941
8942 return E_APIXC_RET_OK;
8943 }
8944
_Hal_XC_Auto_Download_Format_Hdr_Data(void * pInstance,EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient,MS_U8 * pu8Data,MS_U32 u32Size,MS_PHY u16StartAddr)8945 static E_APIXC_ReturnValue _Hal_XC_Auto_Download_Format_Hdr_Data(void* pInstance,
8946 EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient, MS_U8* pu8Data, MS_U32 u32Size, MS_PHY u16StartAddr)
8947 {
8948 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8949 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8950
8951 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8952 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8953
8954 MS_PHY phyBaseAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].phyBaseAddr;
8955 MS_U32 u32Depth = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth;
8956 MS_VIRT* pVirtBaseAddr = (MS_VIRT *)MS_PA2KSEG1(phyBaseAddr);
8957 unsigned int i = 0;
8958 MS_PHY u32Index = u16StartAddr;
8959 MS_U32 u32WriteNum = 0;
8960 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
8961 pu8BaseAddr += 16 * u16StartAddr;
8962
8963 // update start addr of DRAM
8964 MS_PHY u32StartAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr;
8965 if (u32StartAddr == 0xFFFFFFFF)
8966 {
8967 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = u16StartAddr;
8968 }
8969 else
8970 {
8971 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = u32StartAddr > u16StartAddr ? u16StartAddr : u32StartAddr;
8972 }
8973
8974 //format&write datas into DRAM
8975 for (i = 0; i < u32Size; )
8976 {
8977 switch (enSubClient)
8978 {
8979 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
8980 {
8981 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + i);
8982 if (u16Value & 0xF000)
8983 {
8984 printf("The %dth data is 0x%x, exceed max value, please check!!!\n", i + 1, u16Value);
8985 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8986 }
8987 WRITE_TMO_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Value);
8988 i++;
8989 break;
8990 }
8991 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
8992 {
8993 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + i);
8994 WRITE_GAMMA_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Value);
8995 i++;
8996 break;
8997 }
8998 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
8999 {
9000 MS_U32 u32Value = *(((MS_U32 *)pu8Data) + i);
9001 if (u32Value & 0xFFF80000)
9002 {
9003 printf("The %dth data is 0x%x, exceed max value, please check!!!\n", i + 1, (unsigned int)u32Value);
9004 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9005 }
9006 WRITE_DEGAMMA_DATA_FORMAT_1(pu8BaseAddr, u32Index, u32Value);
9007 i++;
9008 break;
9009 }
9010 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9011 {
9012 MS_U16 u16RVal = *(((MS_U16 *)pu8Data) + i);
9013 MS_U16 u16GVal = *(((MS_U16 *)pu8Data) + i + 1);
9014 MS_U16 u16BVal = *(((MS_U16 *)pu8Data) + i + 2);
9015 MS_U16 u16Subindex = 0;
9016 if(i < _au32_3dlut_entry_num[0])
9017 {
9018 u16Subindex = 0;
9019 }
9020 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1]))
9021 {
9022 u16Subindex = 1;
9023 }
9024 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2]))
9025 {
9026 u16Subindex = 2;
9027 }
9028 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3]))
9029 {
9030 u16Subindex = 3;
9031 }
9032 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4]))
9033 {
9034 u16Subindex = 4;
9035 }
9036 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5]))
9037 {
9038 u16Subindex = 5;
9039 }
9040 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5] + _au32_3dlut_entry_num[6]))
9041 {
9042 u16Subindex = 6;
9043 }
9044 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5] + _au32_3dlut_entry_num[6] + _au32_3dlut_entry_num[7]))
9045 {
9046 u16Subindex = 7;
9047 }
9048 WRITE_3DLUT_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Subindex, u16RVal, u16GVal, u16BVal);
9049 i += 3;
9050 break;
9051 }
9052 }
9053 pu8BaseAddr += 16;
9054 u32WriteNum++;
9055 u32Index++;
9056 }
9057
9058 u32Depth = u32Depth > u32WriteNum ? u32Depth : u32WriteNum;
9059 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = u32Depth;
9060
9061 #if DEBUG_HDR
9062 int j = 0;
9063 int l = 0;
9064
9065 printf("\n#####################Dump Input Data####################\n");
9066 for (j = 0; j < u32Size;)
9067 {
9068 printf("The %04dth row: ", u16StartAddr++);
9069 switch (enSubClient)
9070 {
9071 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9072 {
9073 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + j);
9074 printf("%02X \n", u16Value);
9075 j++;
9076 break;
9077 }
9078 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9079 {
9080 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + j);
9081 printf("%02X \n", u16Value);
9082 j++;
9083 break;
9084 }
9085 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9086 {
9087 MS_U32 u32Value = *(((MS_U32 *)pu8Data) + j);
9088 printf("%04X \n", u32Value);
9089 j++;
9090 break;
9091 }
9092 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9093 {
9094 MS_U16 u16RVal = *(((MS_U16 *)pu8Data) + j);
9095 MS_U16 u16GVal = *(((MS_U16 *)pu8Data) + j + 1);
9096 MS_U16 u16BVal = *(((MS_U16 *)pu8Data) + j + 2);
9097 printf("%02X %02X %02X \n", u16RVal, u16GVal, u16BVal);
9098 j += 3;
9099 break;
9100 }
9101 }
9102 printf("\n");
9103 }
9104 printf("\n#####################Dump End####################\n\n");
9105
9106 int k = AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR;
9107 printf("\n#####################Dump DRAM Buffer####################\n");
9108 for (j = 0; j < k; j++)
9109 {
9110 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
9111 printf("\nThe %04dth row: ", j);
9112 for (l = 0; l < 16; l++)
9113 {
9114 switch (enSubClient)
9115 {
9116 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9117 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9118 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9119 {
9120 printf("%02X ", *(pu8BaseAddr + 16 * j + l));
9121 break;
9122 }
9123 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9124 {
9125 printf("%02X ", *(pu8BaseAddr + 16 * j + l));
9126 k = AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR;
9127 break;
9128 }
9129 }
9130 }
9131 }
9132 printf("\n#####################Dump End####################\n");
9133 #endif
9134
9135 return E_APIXC_RET_OK;
9136 }
9137
MHal_XC_AutoDownload_Write(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_U8 * pu8Data,MS_U32 u32Size,void * pParam)9138 E_APIXC_ReturnValue MHal_XC_AutoDownload_Write(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_U8* pu8Data, MS_U32 u32Size, void* pParam)
9139 {
9140 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9141 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9142
9143 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9144 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9145
9146 switch(enClient)
9147 {
9148 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
9149 {
9150 XC_AUTODOWNLOAD_FORMAT_INFO* pstFormatInfo = (XC_AUTODOWNLOAD_FORMAT_INFO *)pParam;
9151 MS_PHY u16StartAddr = 0;
9152 MS_U32 u32MaxSize = 0;
9153 switch (pstFormatInfo->enSubClient)
9154 {
9155 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9156 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9157 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9158 {
9159 u32MaxSize = AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR;
9160 break;
9161 }
9162 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9163 {
9164 u32MaxSize = AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR * 3;
9165 break;
9166 }
9167 default:
9168 {
9169 printf("Write auto download fail, invaild paramters, subClient: %d\n", pstFormatInfo->enSubClient);
9170 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9171 }
9172 }
9173 if (pstFormatInfo->bEnableRange == TRUE)
9174 {
9175 if (pstFormatInfo->u16StartAddr <= pstFormatInfo->u16EndAddr && pstFormatInfo->u16EndAddr < u32MaxSize
9176 && (pstFormatInfo->u16StartAddr + u32Size - 1) < u32MaxSize)
9177 {
9178 u16StartAddr = pstFormatInfo->u16StartAddr;
9179 }
9180 else
9181 {
9182 printf("Write auto download fail, invaild paramters, size: %d, addr range(enable, start, end) = (%d, %td, %td)\n",
9183 u32Size, pstFormatInfo->bEnableRange, (ptrdiff_t)pstFormatInfo->u16StartAddr, (ptrdiff_t)pstFormatInfo->u16EndAddr);
9184 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9185 }
9186 }
9187 else
9188 {
9189 if (u32Size > u32MaxSize)
9190 {
9191 printf("Write auto download fail, invaild paramters, size: %d\n", u32Size);
9192 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9193 }
9194 }
9195 return _Hal_XC_Auto_Download_Format_Hdr_Data(pInstance, pstFormatInfo->enSubClient, pu8Data, u32Size, u16StartAddr);
9196 }
9197 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
9198 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
9199 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
9200 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
9201 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
9202 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
9203 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
9204 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
9205 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
9206 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
9207 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
9208 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
9209 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
9210 default:
9211 {
9212 return E_APIXC_RET_FAIL;
9213 }
9214
9215 }
9216
9217 return E_APIXC_RET_OK;
9218 }
9219
MHal_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_BOOL * pbSupported)9220 E_APIXC_ReturnValue MHal_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_BOOL *pbSupported)
9221 {
9222 switch(enClient)
9223 {
9224 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
9225 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
9226 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
9227 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
9228 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
9229 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
9230 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
9231 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
9232 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
9233 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
9234 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
9235 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
9236 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
9237 {
9238 *pbSupported = TRUE;
9239 break;
9240 }
9241 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
9242 default:
9243 {
9244 *pbSupported = FALSE;
9245 break;
9246 }
9247
9248 }
9249
9250 return E_APIXC_RET_OK;
9251 }
9252 #endif
9253
9254 #ifdef UFO_XC_HDR
9255 #if (UFO_XC_HDR_VERSION == 2)
_Hal_XC_HDR_UpdateDMAMode(void * pInstance)9256 static E_APIXC_ReturnValue _Hal_XC_HDR_UpdateDMAMode(void* pInstance)
9257 {
9258 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9259 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9260
9261 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9262 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9263
9264 EN_XC_HDR_COLOR_FORMAT enColorFormat = pXCResourcePrivate->stdrvXC_Display._enColorFormat;
9265 EN_XC_HDR_DMA_MODE enMode = pXCResourcePrivate->stdrvXC_Display._stDMAConfigInfo.enMode;
9266
9267 switch (enColorFormat)
9268 {
9269 case E_XC_HDR_COLOR_YUV422:
9270 {
9271 // set dma mode
9272 if (enMode == E_XC_HDR_DMA_MODE_12BIT)
9273 {
9274 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 0, 0x0003);
9275 }
9276 else if (enMode == E_XC_HDR_DMA_MODE_8BIT)
9277 {
9278 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 2, 0x0003);
9279 }
9280 else if (enMode == E_XC_HDR_DMA_MODE_10BIT)
9281 {
9282 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 3, 0x0003);
9283 }
9284 break;
9285 }
9286 case E_XC_HDR_COLOR_YUV444:
9287 {
9288 if (enMode == E_XC_HDR_DMA_MODE_10BIT)
9289 {
9290 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 1, 0x0003);
9291 }
9292 break;
9293 }
9294 case E_XC_HDR_COLOR_YUV420:
9295 case E_XC_HDR_COLOR_RGB:
9296 default:
9297 {
9298 break;
9299 }
9300 }
9301
9302 return E_APIXC_RET_OK;
9303 }
9304
MHal_XC_HDR_Control(void * pInstance,EN_XC_HDR_CTRL_TYPE enCtrlType,void * pParam)9305 E_APIXC_ReturnValue MHal_XC_HDR_Control(void* pInstance, EN_XC_HDR_CTRL_TYPE enCtrlType, void *pParam)
9306 {
9307 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9308 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9309
9310 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9311 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9312
9313 switch(enCtrlType)
9314 {
9315 case E_XC_HDR_CTRL_CONFIG_DMA:
9316 case E_XC_HDR_CTRL_SET_COLOR_FORMAT:
9317 {
9318 _Hal_XC_HDR_UpdateDMAMode(pInstance);
9319 break;
9320 }
9321 case E_XC_HDR_CTRL_INIT_DMA:
9322 {
9323 XC_HDR_DMA_INIT_INFO stDMAInitInfo = *(XC_HDR_DMA_INIT_INFO *)pParam;
9324 if ((stDMAInitInfo.phyBaseAddr != 0) && (stDMAInitInfo.u32Size != 0))
9325 {
9326 // set IPM/OPM addr
9327 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_08_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
9328 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_09_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
9329 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_10_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
9330 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_11_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
9331
9332 // set limit addr
9333 // enable limit
9334 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_50_L, 1, BIT(0));
9335 // min addr
9336 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_52_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
9337 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_53_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
9338 // max addr
9339 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_54_L, (stDMAInitInfo.phyBaseAddr + stDMAInitInfo.u32Size) / BYTE_PER_WORD - 1);
9340 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_55_L, ((stDMAInitInfo.phyBaseAddr + stDMAInitInfo.u32Size) / BYTE_PER_WORD - 1) >> 16, 0x01FF);
9341 }
9342 break;
9343 }
9344 case E_XC_HDR_CTRL_ENABLE:
9345 case E_XC_HDR_CTRL_SET_TYPE:
9346 case E_XC_HDR_CTRL_SET_3DLUT:
9347 case E_XC_HDR_CTRL_SET_OTT_SHARE_MEMORY:
9348 case E_XC_HDR_CTRL_SET_OPEN_METADATA:
9349 default:
9350 {
9351 break;
9352 }
9353 }
9354
9355 return E_APIXC_RET_OK;
9356 }
9357
MHal_XC_HDR_GetCaps(void * pInstance,XC_HDR_SUPPORTED_CAPS * pstHDRCaps)9358 E_APIXC_ReturnValue MHal_XC_HDR_GetCaps(void *pInstance, XC_HDR_SUPPORTED_CAPS *pstHDRCaps)
9359 {
9360 EN_XC_HDR_TYPE enHDRType = pstHDRCaps->enHDRType;
9361
9362 switch (enHDRType)
9363 {
9364 case E_XC_HDR_TYPE_OPEN:
9365 case E_XC_HDR_TYPE_DOLBY:
9366 {
9367 pstHDRCaps->bSupported = FALSE;
9368 break;
9369 }
9370 case E_XC_HDR_TYPE_TECHNICOLOR:
9371 {
9372 pstHDRCaps->bSupported = FALSE;
9373 break;
9374 }
9375 case E_XC_HDR_TYPE_HLG:
9376 {
9377 pstHDRCaps->bSupported = FALSE;
9378 break;
9379 }
9380 default:
9381 {
9382 pstHDRCaps->bSupported = FALSE;
9383 }
9384 }
9385
9386 pstHDRCaps->s32MaxLuminanceData = -1;
9387 pstHDRCaps->s32MinLuminanceData = -1;
9388 pstHDRCaps->s32MaxFrameAveLumiance = -1;
9389
9390 return E_APIXC_RET_OK;
9391 }
9392 #endif
9393 #endif
9394
9395 //T3D MIU select from external
Hal_SC_Set_T3D_MiuSelectExternal(void * pInstance,MS_U8 u8MIUSel)9396 void Hal_SC_Set_T3D_MiuSelectExternal(void *pInstance, MS_U8 u8MIUSel)
9397 {
9398 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9399 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9400 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9401 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9402
9403 if(2 == u8MIUSel)//MIU2 = (10) ==> REG_SC_BK7F_18_[10] = 1 && REG_SC_BK7F_10_[10] = 0
9404 {
9405 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, 0, BIT(10));//Enable T3D select MIU exteral
9406 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, 0, BIT(10));//T3D MIU select low 1 bit
9407 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, BIT(10), BIT(10));//T3D MIU select hight 1 bit
9408 }
9409 else if(1 == u8MIUSel)//MIU1
9410 {
9411 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, 0, BIT(10));//Enable T3D select MIU exteral
9412 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, BIT(10), BIT(10));//T3D MIU select low 1 bit
9413 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, 0, BIT(10));//T3D MIU select hight 1 bit
9414 }
9415 else//MIU0
9416 {
9417 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_11_L, 0, BIT(10));//Enable T3D select MIU exteral
9418 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L,0, BIT(10));// T3D MIU select low 1 bit
9419 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, 0, BIT(10));//T3D MIU select hight 1 bit
9420 }
9421 }
9422
MHal_XC_GetPQPathStatus(void * pInstance,E_XC_PQ_Path_Type ePqPathType,MS_U16 u16Width,MS_U16 u16Height)9423 MS_BOOL MHal_XC_GetPQPathStatus(void* pInstance, E_XC_PQ_Path_Type ePqPathType, MS_U16 u16Width, MS_U16 u16Height)
9424 {
9425 MS_BOOL bRet = FALSE;
9426 switch (ePqPathType)
9427 {
9428 case E_XC_PQ_4K_PATH :
9429 bRet = (IS_4K2K_MODE(u16Width, u16Height)||IS_4K1K_MODE(u16Width, u16Height));
9430 break;
9431 case E_XC_PQ_UFSC_4K_PATH :
9432 if(MHal_FRC_IsFHDToFSC(pInstance, MAIN_WINDOW))
9433 {
9434 bRet = FALSE;
9435 }
9436 else
9437 {
9438 bRet = TRUE;
9439 }
9440 break;
9441 default :
9442 printf("[%s][%d] not path type(%d)!\n", __FUNCTION__, __LINE__, ePqPathType);
9443 break;
9444 }
9445
9446 return bRet;
9447 }
9448 #ifdef CONFIG_MSTAR_SRAMPD
MHal_XC_Set_LD_SRAM_Power_Down(void * pInstance,MS_BOOL bIsSRAMPowerDown)9449 void MHal_XC_Set_LD_SRAM_Power_Down(void* pInstance, MS_BOOL bIsSRAMPowerDown)
9450 {
9451 UNUSED(pInstance);
9452 UNUSED(bIsSRAMPowerDown);
9453 }
9454
MHal_XC_Set_ADC_SRAM_Power_Down(void * pInstance,MS_BOOL bIsSRAMPowerDown)9455 void MHal_XC_Set_ADC_SRAM_Power_Down(void* pInstance, MS_BOOL bIsSRAMPowerDown)
9456 {
9457 UNUSED(pInstance);
9458 UNUSED(bIsSRAMPowerDown);
9459 }
9460 #endif
9461
9462 static XC_VSYNC_VSTART stXCVstart = {0, 0, 0, 0, FALSE};
MHal_XC_PixelShiftStatusChange(void * pInstance,XC_PIXEL_SHIFT_STATUS enStatus)9463 MS_BOOL MHal_XC_PixelShiftStatusChange(void* pInstance, XC_PIXEL_SHIFT_STATUS enStatus)
9464 {
9465 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9466 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9467 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9468 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9469 MS_U8 u8LPLL_Type = 0;
9470 MS_U16 u16Reg = 0;
9471 u8LPLL_Type =(MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type;
9472 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "enStatus: %d.\n", enStatus);
9473
9474 switch (enStatus)
9475 {
9476 case EN_XC_PIXEL_SHIFT_DISABLE:
9477 u16Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L, 0x1FFF);
9478 if ((u16Reg != stXCVstart.u16RegSTGenDeVstart) && (stXCVstart.u16RegSTGenDeVstart != 0))
9479 {
9480 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L, stXCVstart.u16RegSTGenDeVstart, 0x1FFF);
9481 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L, stXCVstart.u16RegSTGenDeVend, 0x1FFF);
9482 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, stXCVstart.u16RegSTGenDeVend, 0x1FFF);
9483
9484 stXCVstart.u16RegSTGenDeVstart = 0;
9485 stXCVstart.u16RegSTGenDeVend = 0;
9486 }
9487 break;
9488 case EN_XC_PIXEL_SHIFT_ENABLE:
9489 if (0 == stXCVstart.u16RegSTGenDeVstart)
9490 {
9491 u16Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L, 0x1FFF);
9492 stXCVstart.u16RegSTGenDeVstart = u16Reg;
9493 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L, (u16Reg + 2), 0x1FFF);
9494
9495 u16Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L, 0x1FFF);
9496 stXCVstart.u16RegSTGenDeVend = u16Reg;
9497 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L, (u16Reg + 2), 0x1FFF);
9498 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, (u16Reg + 2), 0x1FFF);
9499 }
9500 break;
9501 case EN_XC_PIXEL_SHIFT_FORCE_UPDATE:
9502 if ((pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange != 0)
9503 && ((pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW] == E_XC_3D_INPUT_MODE_NONE) && (pXCResourcePrivate->stdrvXC_3D._eOutput3DMode == E_XC_3D_OUTPUT_MODE_NONE))
9504 )
9505 {
9506 u16Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L, 0x1FFF);
9507 stXCVstart.u16RegSTGenDeVstart = u16Reg;
9508 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L, (u16Reg + 2), 0x1FFF);
9509
9510 u16Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L, 0x1FFF);
9511 stXCVstart.u16RegSTGenDeVend = u16Reg;
9512 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L, (u16Reg + 2), 0x1FFF);
9513 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, (u16Reg + 2), 0x1FFF);
9514 }
9515 else
9516 {
9517 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "gu16VPixelShiftRange: %u.\n", pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange);
9518 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "_eInput3DMode: %d.\n", pXCResourcePrivate->stdrvXC_3D._eInput3DMode[MAIN_WINDOW]);
9519 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "_eOutput3DMode: %d.\n", pXCResourcePrivate->stdrvXC_3D._eOutput3DMode);
9520 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "ByPass EN_XC_PIXEL_SHIFT_FORCE_UPDATE.\n");
9521 }
9522 break;
9523 default:
9524 break;
9525 }
9526
9527 return TRUE;
9528 }
9529
Hal_SC_CheckMuteStatusByRegister(void * pInstance,SCALER_WIN eWindow)9530 MS_BOOL Hal_SC_CheckMuteStatusByRegister(void *pInstance, SCALER_WIN eWindow)
9531 {
9532 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9533 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9534 MS_BOOL bRet = FALSE;
9535
9536 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB)
9537 if(((MAIN_WINDOW == eWindow) && (psXCInstPri->u32DeviceID == 1))
9538 || (SUB_WINDOW == eWindow)
9539 )
9540 {
9541 bRet = (SC_R2BYTEMSK(0, REG_SC_BK10_19_L, BIT(5)) ? TRUE: FALSE);
9542 }
9543 #else
9544 if(SUB_WINDOW == eWindow)
9545 {
9546 bRet = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, BIT(5)) ? TRUE: FALSE);
9547 }
9548 #endif
9549 else if(MAIN_WINDOW == eWindow)
9550 {
9551 bRet = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, BIT(1)) ? TRUE: FALSE);
9552 }
9553 return bRet;
9554 }
9555
Hal_SC_add_dram_to_shm(void * pInstance,SCALER_WIN eWindow,MS_PHY u32address,MS_U32 u32length)9556 void Hal_SC_add_dram_to_shm(void *pInstance,SCALER_WIN eWindow,MS_PHY u32address,MS_U32 u32length)
9557 {
9558 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9559 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9560 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9561 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9562
9563 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt].address = u32address;
9564 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt].length = u32length;
9565 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt++;
9566 }
Hal_SC_add_reg_to_shm(void * pInstance,SCALER_WIN eWindow,MS_U32 u32_bk,MS_U16 u16_value,MS_U16 u16_mask)9567 void Hal_SC_add_reg_to_shm(void *pInstance,SCALER_WIN eWindow,MS_U32 u32_bk,MS_U16 u16_value,MS_U16 u16_mask)
9568 {
9569 MS_U32 u32offset = 0;
9570 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9571 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9572 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9573 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9574
9575 u32offset = _XC_Device_Offset[psXCInstPri->u32DeviceID];
9576
9577 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt].bk = REG_SCALER_BASE + u32_bk + (u32offset << 8);
9578 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt].value = u16_value;
9579 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt].mask = u16_mask;
9580 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt ++;
9581 }
9582
Hal_SC_secure_lock(void * pInstance,SCALER_WIN eWindow,MS_U32 u32SecureDMA,MS_U32 u32OperationMode)9583 MS_BOOL Hal_SC_secure_lock(void *pInstance, SCALER_WIN eWindow, MS_U32 u32SecureDMA, MS_U32 u32OperationMode)
9584 {
9585 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9586 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9587 #ifndef MSOS_TYPE_OPTEE
9588 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9589 #else
9590 XC_RESOURCE_PRIVATE_FOR_TEE* pXCResourcePrivate = NULL;
9591 #endif
9592 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9593 #ifdef MSOS_TYPE_OPTEE
9594 if (u32SecureDMA == 1)
9595 {
9596 MDrv_Seal_ChangeIPSecureDMAAbillity(MODULE_XC, 0 , TRUE);
9597 if(MDrv_Seal_SetSecureRange(pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address , pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].length , TRUE) == FALSE)
9598 {
9599 return FALSE;
9600 }
9601 }
9602 else if (u32SecureDMA == 0)
9603 {
9604 MDrv_Seal_ChangeIPSecureDMAAbillity(MODULE_XC, 0 , FALSE);
9605 if(MDrv_Seal_SetSecureRange(pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address , pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].length , FALSE) == FALSE)
9606 {
9607 return FALSE;
9608 }
9609 }
9610 if (u32OperationMode == 1)
9611 {
9612 MDrv_Seal_SecureSlaveSet(E_SEAL_SC0_PROT_NONPM, TRUE);
9613 MDrv_Seal_BufferLock(E_SEAL_SC_WP_SCM_M, TRUE);
9614 }
9615 else if (u32OperationMode == 0)
9616 {
9617 MDrv_Seal_SecureSlaveSet(E_SEAL_SC0_PROT_NONPM, FALSE);
9618 MDrv_Seal_BufferLock(E_SEAL_SC_WP_SCM_M, FALSE);
9619 }
9620 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].isEnable=u32OperationMode;
9621 #endif
9622 return TRUE;
9623 }
9624
Hal_SC_update_to_shm(void * pInstance,SCALER_WIN eWindow)9625 void Hal_SC_update_to_shm(void *pInstance, SCALER_WIN eWindow)
9626 {
9627 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9628 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9629 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9630 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9631 if (eWindow == MAIN_WINDOW)
9632 {
9633 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK0D_38_L, (BIT(0) | BIT(4)), (BIT(0) | BIT(4)));
9634 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_08_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) & 0xFFFF), 0xFFFF);
9635 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_09_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) >> 16), 0xFFFF);
9636 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_1C_L, 0x0000, 0xFFFF);
9637 }
9638 else if (eWindow == SUB_WINDOW)
9639 {
9640 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK0D_38_L, (BIT(1) | BIT(6)), (BIT(1) | BIT(6)));
9641 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_48_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) & 0xFFFF), 0xFFFF);
9642 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_49_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) >> 16), 0xFFFF);
9643 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_5C_L, 0x0000, 0xFFFF);
9644 }
9645 }
9646 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
9647 //-------------------------------------------------------------------------------------------------
9648 /// Set Dual View
9649 //-------------------------------------------------------------------------------------------------
Hal_SC_3D_Set_DualView(void * pInstance,MS_BOOL bEnable)9650 void Hal_SC_3D_Set_DualView(void *pInstance, MS_BOOL bEnable)
9651 {
9652 // manhattan dual view
9653 // clone SC1 main to SC0 sub
9654 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9655 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9656 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9657 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9658
9659 Hal_SC_set_dualview_clone(pInstance,bEnable);
9660
9661 if (bEnable)
9662 {
9663 if (IS_OUTPUT_FRAME_ALTERNATIVE())
9664 {
9665 SC_W2BYTEMSK(0, REG_SC_BK20_24_L, BIT(2), BIT(2)); // reg_op1lr_sel
9666 SC_W2BYTEMSK(0, REG_SC_BK20_24_L, BIT(1), BIT(1)|BIT(0)); // reg_lr2mod_sel
9667 }
9668 else if (IS_OUTPUT_LINE_ALTERNATIVE())
9669 {
9670 SC_W2BYTEMSK(0, REG_SC_BK23_53_L, BIT(15), BIT(15));//dnr offset
9671 SC_W2BYTEMSK(1, REG_SC_BK20_1B_L, 0x0800, 0x0FFF); //FIXME: tmp solution from HW RD for fixing dual view sub window shaking problem
9672 }
9673
9674 SC_W2BYTEMSK(0, REG_SC_BK68_40_L, 0, BIT(4)); // disable sc1 pip
9675 SC_W2BYTEMSK(0, REG_SC_BK20_10_L, 0, BIT(2));
9676 SC_W2BYTEMSK(1, REG_SC_BK20_10_L, BIT(10), BIT(10));
9677 if((SC_R2BYTEMSK(1, REG_SC_BK12_01_L, BIT(5)) == BIT(5)) ||(SC_R2BYTEMSK(1, REG_SC_BK12_01_L, BIT(4)) == BIT(4)))
9678 {
9679 SC_W2BYTEMSK(0, REG_SC_BK23_2C_L, 0, 0xFFFF);
9680 }
9681 else
9682 {
9683 SC_W2BYTEMSK(0, REG_SC_BK23_2C_L, BIT(6) |BIT(7), BIT(6) |BIT(7));
9684 }
9685
9686 #if(HW_DESIGN_3D_VER == 3) //monet mode
9687 if (SC_R2BYTEMSK(0, REG_SC_BK20_03_L, BIT(2)) == BIT(2))
9688 {
9689 SC_W2BYTEMSK(0, REG_SC_BK20_03_L,0, BIT(2));//reg_force_fe2_en
9690 }
9691 #endif
9692 }
9693 else
9694 {
9695 SC_W2BYTEMSK(0, REG_SC_BK20_24_L, 0, BIT(2)); // reg_op1lr_sel
9696 SC_W2BYTEMSK(0, REG_SC_BK20_24_L, 0, BIT(1)|BIT(0)); // reg_lr2mod_sel
9697 SC_W2BYTEMSK(0, REG_SC_BK23_53_L, 0, 0x8000);//dnr offset
9698
9699 SC_W2BYTEMSK(1, REG_SC_BK20_10_L, 0, BIT(10));
9700
9701 if ((SC_R2BYTEMSK(1, REG_SC_BK20_10_L, BIT(0)) == BIT(0))
9702 && (SC_R2BYTEMSK(0, REG_SC_BK20_10_L, BIT(1)) == BIT(1)))
9703 {
9704 //restore sc1 pip setting
9705 SC_W2BYTEMSK(0, REG_SC_BK68_40_L, BIT(4), BIT(4));
9706 }
9707 }
9708 }
9709
Hal_SC_3D_IsDualViewMode(void * pInstance,SCALER_WIN eWindow)9710 MS_BOOL Hal_SC_3D_IsDualViewMode(void* pInstance, SCALER_WIN eWindow) //elaine.chen
9711 {
9712 MS_BOOL ret = FALSE;
9713
9714 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9715 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9716 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9717 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9718 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
9719 if(IS_INPUT_MODE_NONE(eWindow) &&
9720 (IS_OUTPUT_FRAME_ALTERNATIVE() || IS_OUTPUT_LINE_ALTERNATIVE() || IS_OUTPUT_TOP_BOTTOM() ))
9721 {
9722 ret = TRUE;
9723 }
9724 #endif
9725 return ret;
9726 }
9727
9728
9729 // clone SC1 main to SC0 sub
Hal_SC_set_dualview_clone(void * pInstance,MS_BOOL bEnable)9730 void Hal_SC_set_dualview_clone(void *pInstance, MS_BOOL bEnable)
9731 {
9732 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9733 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9734 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9735 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9736 SC_DBG(printf("\33[0;35m [Dual View] %s %d: ,bEnable = %u \33[m \n", __FUNCTION__, __LINE__,bEnable));
9737
9738 if (bEnable)
9739 {
9740 MS_U16 u16value = 0;
9741 MS_U32 u32value = 0;
9742
9743 // memfmt
9744 u16value = SC_R2BYTE(1, REG_SC_BK12_01_L);
9745 SC_W2BYTE(0, REG_SC_BK12_41_L, u16value);
9746
9747 u16value = SC_R2BYTE(1, REG_SC_BK12_02_L);
9748 SC_W2BYTE(0, REG_SC_BK12_42_L, u16value);
9749
9750 u16value = SC_R2BYTE(1, REG_SC_BK12_03_L);
9751 SC_W2BYTE(0, REG_SC_BK12_43_L, u16value);
9752
9753 u16value = SC_R2BYTE(1, REG_SC_BK12_04_L);
9754 SC_W2BYTE(0, REG_SC_BK12_44_L, u16value);
9755
9756 u16value = SC_R2BYTE(1, REG_SC_BK12_05_L);
9757 SC_W2BYTE(0, REG_SC_BK12_45_L, u16value);
9758
9759 u16value = SC_R2BYTE(1, REG_SC_BK12_06_L);
9760 SC_W2BYTE(0, REG_SC_BK12_46_L, u16value);
9761
9762 u16value = SC_R2BYTE(1, REG_SC_BK12_07_L);
9763 SC_W2BYTE(0, REG_SC_BK12_47_L, u16value);
9764
9765 u32value = SC_R4BYTE(1, REG_SC_BK12_08_L); // ipm base
9766 SC_W4BYTE(0, REG_SC_BK12_48_L, u32value);
9767
9768 u32value = SC_R4BYTE(1, REG_SC_BK12_10_L); // opm base
9769 SC_W4BYTE(0, REG_SC_BK12_50_L, u32value);
9770
9771 u16value = SC_R2BYTE(1, REG_SC_BK12_0E_L); //ipm offset
9772 SC_W2BYTE(0, REG_SC_BK12_4E_L, u16value);
9773
9774 u16value = SC_R2BYTE(1, REG_SC_BK12_0F_L); //ipm fetch
9775 SC_W2BYTE(0, REG_SC_BK12_4F_L, u16value);
9776
9777 u16value = SC_R2BYTE(1, REG_SC_BK12_16_L); //opm offset
9778 SC_W2BYTE(0, REG_SC_BK12_56_L, u16value);
9779
9780 u16value = SC_R2BYTE(1, REG_SC_BK12_17_L); //opm fetch
9781 SC_W2BYTE(0, REG_SC_BK12_57_L, u16value);
9782
9783 u16value = SC_R2BYTE(1, REG_SC_BK12_18_L);
9784 SC_W2BYTE(0, REG_SC_BK12_58_L, u16value);
9785
9786 u16value = SC_R2BYTEMSK(1, REG_SC_BK12_19_L, 0x1F); // frame count
9787 SC_W2BYTEMSK(0, REG_SC_BK12_59_L, u16value, 0x1F);
9788
9789 u16value = SC_R2BYTEMSK(1, REG_SC_BK20_15_L, 0x0FFF); // v_length
9790 SC_W2BYTEMSK(0, REG_SC_BK20_16_L, u16value, 0x0FFF);
9791
9792 u16value = SC_R2BYTEMSK(1, REG_SC_BK20_1D_L, 0xFF); // H_offset
9793 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u16value<<8, 0xFF00);
9794
9795 u32value = SC_R4BYTE(1, REG_SC_BK23_07_L); // post H scaling
9796 SC_W4BYTE(0, REG_SC_BK23_27_L, u32value);
9797
9798 u32value = SC_R4BYTE(1, REG_SC_BK23_09_L); // post V scaling
9799 SC_W4BYTE(0, REG_SC_BK23_29_L, u32value);
9800
9801 u16value = SC_R2BYTEMSK(0, REG_SC_BK01_61_L, 0x03);
9802 SC_W2BYTEMSK(1, REG_SC_BK01_61_L, u16value, 0x03); // copy main setting for HDMI Y422 color wrong when dual view on
9803
9804 if (IS_OUTPUT_LINE_ALTERNATIVE())
9805 { //Solution from HW RD cc.yang for fixing dual view sub window shaking problem
9806 u16value = SC_R2BYTEMSK(0, REG_SC_BK20_1A_L, 0x0FFF);//Get the delay line for Auto tune area
9807 SC_W2BYTEMSK(1, REG_SC_BK20_1A_L, u16value - 3, 0x0FFF);//(Value -3) is a empirical value given by cc.yang
9808 u16value = SC_R2BYTEMSK(0, REG_SC_BK20_1B_L, 0x0FFF);//Get the delay line for Display area
9809 SC_W2BYTEMSK(1, REG_SC_BK20_1B_L, u16value - 3, 0x0FFF);//(Value -3) is a empirical value given by cc.yang
9810 }
9811
9812 if(SC_R2BYTEMSK(0, REG_SC_BK7F_11_L, BIT(1)) == BIT(1))//if miu arb or xc internel control miu
9813 {
9814 if(SC_R2BYTEMSK(1, REG_SC_BK12_05_L, BIT(4)) == BIT(4))//if sc1 opm seletect miu1
9815 {
9816 SC_W2BYTEMSK(0, REG_SC_BK12_44_L, BIT(14), BIT(14));
9817 }
9818 else
9819 {
9820 SC_W2BYTEMSK(0, REG_SC_BK12_44_L, 0, BIT(14));
9821 }
9822 }
9823 }
9824 }
9825 #endif
9826
9827 //#define GET_FB_LEVEL_DBG(x) //x
MHal_XC_Get_FB_Level(void * pInstance,MS_WINDOW_TYPE * pstCropWin,MS_WINDOW_TYPE * pstDispWin,MS_BOOL bInterlace,MS_U16 * pu16HSize,MS_U16 * pu16VSize)9828 E_XC_FB_LEVEL MHal_XC_Get_FB_Level(void* pInstance, MS_WINDOW_TYPE* pstCropWin, MS_WINDOW_TYPE* pstDispWin, MS_BOOL bInterlace, MS_U16* pu16HSize, MS_U16* pu16VSize)
9829 {
9830 return E_XC_FB_LEVEL_NUM;//default return E_XC_FB_LEVEL_NUM
9831 }
9832
Hal_SC_get_HDMIpolicy(void * pInstance)9833 MS_U32 Hal_SC_get_HDMIpolicy(void *pInstance)
9834 {
9835 UNUSED(pInstance);
9836 return 0;
9837 }
9838
9839 #undef MHAL_SC_C
9840