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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_PNL_H_ 103 #define _HAL_PNL_H_ 104 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 #ifdef _HAL_PNL_C_ 110 #define HAL_PNL_INTERFACE 111 #else 112 #define HAL_PNL_INTERFACE extern 113 #endif 114 115 // Current platform is DAC out or not 116 #define IS_DAC_OUT FALSE 117 118 // version0: Not support TV chip as HDMITx 119 // version1: Maserati + Raptor 120 // version2: Maxim + inside HDMITx 121 #define HW_DESIGN_HDMITX_VER (2) 122 123 // XC register serpead define 124 #define XC_REGISTER_SPREAD 1 125 #define SUPPORT_FRC 0 126 #define REG_CHIP_REVISION 0x1ECEUL //0x1ECFUL is high byte 127 #define XC_SUPPORT_AUTO_VSYNC 1 128 #define PNL_SUPPORT_DEVICE_NUM 2 129 #define MONACO_SC2 130 #define PNL_SUPPORT_2P_MODE TRUE 131 //------------------------------------------------------------------------------------------------- 132 // Driver Capability 133 //------------------------------------------------------------------------------------------------- 134 #define GAMMA_10BIT BIT(0) ///< gamma value range up to 10 BIt 135 #define GAMMA_12BIT BIT(1) ///< gamma value range up to 12 BIT 136 137 #define GAMMA_8BIT_MAPPING BIT(0) ///< mapping GAMMA value to 256 sampline entries 138 #define GAMMA_10BIT_MAPPING BIT(1) ///< mapping GAMMA value to 1024 sampling entries 139 140 typedef struct 141 { 142 MS_U8 eSupportGammaType; ///< refer to HAL_PNL_GAMMA_TYPE 143 MS_U8 eSupportGammaMapMode; ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE 144 } PNL_HalInfo; 145 146 #define SUPPORT_OVERDRIVE 1 147 #define GAMMA_TYPE (GAMMA_10BIT | GAMMA_12BIT) 148 #define GAMMA_MAPPING (GAMMA_8BIT_MAPPING | GAMMA_10BIT_MAPPING) 149 #define SUPPORT_SYNC_FOR_DUAL_MODE TRUE //New feature after T7 150 #define ENABLE_Auto_ModCurrentCalibration 1 151 152 // MIU Word (Bytes) 153 #define BYTE_PER_WORD (32) 154 155 #define SUPPORT_TCON TRUE 156 157 //#define MOD_TVFRC //for sub bank register change 158 //------------------------------------------------------------------------------------------------- 159 // Macro and Define 160 //------------------------------------------------------------------------------------------------- 161 162 163 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 164 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 165 166 // NONPM 167 #define REG_RVD_BASE 0x100A00UL 168 #define REG_CHIPTOP_BASE 0x100B00UL // 0x1E00 - 0x1EFF 169 #if XC_REGISTER_SPREAD 170 #define REG_SCALER_BASE 0x130000UL 171 #else 172 #define REG_SCALER_BASE 0x102F00UL 173 #endif 174 #define REG_HDGEN_BASE 0x103000UL 175 #define REG_LPLL_BASE 0x103100UL 176 #define REG_MOD_BASE 0x103200UL 177 #define REG_MOD_A_BASE 0x111E00UL 178 #define REG_CLKGEN1_BASE 0x103300UL 179 #define REG_UTMI1_BASE 0x103A00UL 180 181 #define REG_CLKGEN0_BASE 0x100B00UL 182 #define REG_CLKGEN1_BASE 0x103300UL 183 184 #define REG_MFT_BASE 0x123100UL 185 186 #define REG_CHIP_BASE 0x101E00UL 187 188 #define REG_SC2_BASE 0x103000UL 189 190 /* TCON */ 191 #define L_BK_TCON(x) BK_REG_L(REG_HDGEN_BASE, x) 192 #define H_BK_TCON(x) BK_REG_H(REG_HDGEN_BASE, x) 193 194 /* LPLL */ 195 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 196 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 197 198 /* UTMI1 */ 199 #define L_BK_UTMI1(x) BK_REG_L(REG_UTMI1_BASE, x) 200 #define H_BK_UTMI1(x) BK_REG_H(REG_UTMI1_BASE, x) 201 202 203 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 204 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 205 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 206 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 207 #define L_CLKGEN2(x) BK_REG_L(REG_RVD_BASE, x) 208 #define H_CLKGEN2(x) BK_REG_H(REG_RVD_BASE, x) 209 210 #define REG_CLKGEN0_52_L (REG_CHIPTOP_BASE + 0xA4) 211 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) 212 #define REG_CLKGEN0_57_L (REG_CHIPTOP_BASE + 0xAE) 213 #define REG_CLKGEN0_58_L (REG_CHIPTOP_BASE + 0xB0) 214 #define REG_CLKGEN0_5E_L (REG_CHIPTOP_BASE + 0xBC) 215 #define REG_CLKGEN0_63_L (REG_CHIPTOP_BASE + 0xC6) 216 217 #define REG_CLKGEN1_31_L (REG_CLKGEN1_BASE + 0x62) 218 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) 219 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) 220 #define REG_RVD_44_L (REG_RVD_BASE + 0x88) 221 #define REG_RVD_46_L (REG_RVD_BASE + 0x8C) 222 223 #define REG_MFT_00_L (REG_MFT_BASE + 0x00) 224 #define REG_MFT_01_L (REG_MFT_BASE + 0x02) 225 #define REG_MFT_02_L (REG_MFT_BASE + 0x04) 226 #define REG_MFT_03_L (REG_MFT_BASE + 0x06) 227 #define REG_MFT_79_L (REG_MFT_BASE + 0xF2) 228 #define REG_MFT_7E_L (REG_MFT_BASE + 0xFC) 229 230 #define REG_CHIP_25_L (REG_CHIP_BASE + 0x4A) 231 #define REG_CHIP_50_L (REG_CHIP_BASE + 0xA0) 232 233 #define REG_SC2_00_L (REG_SC2_BASE + 0x00) 234 #define REG_SC2_03_L (REG_SC2_BASE + 0x06) 235 236 #define XC_PAFRC_DITH_NOISEDITH_EN (0x00) 237 #define XC_PAFRC_DITH_TAILCUT_DISABLE (0x00) 238 239 #define LVDS_DUAL_OUTPUT 0 240 #define LVDS_DUAL_OUTPUT_SPECIAL 1// only for use with T8 board 241 #define LVDS_SINGLE_OUTPUT_A 2 242 #define LVDS_SINGLE_OUTPUT_B 3 243 #define LVDS_OUTPUT_User 4 244 245 // SCALER CLK select 246 #define REG_CKG_ODCLK REG_CLKGEN0_53_L 247 #define CKG_ODCLK_GATED BIT(0) 248 #define CKG_ODCLK_INVERT BIT(1) 249 #define CKG_ODCLK_SEL_SOURCE BIT(2) 250 #define CKG_ODCLK_SEL_SYNTHETIC (0 << 2) 251 #define CKG_ODCLK_SEL_LPLL (1 << 2) 252 #define CKG_ODCLK_MASK (BIT(3) | BIT(4)) 253 #define CKG_ODCLK_CLK_DIV_2 (0 << 3) 254 #define CKG_ODCLK_XTAL (1 << 3) 255 #define CKG_ODCLK_CLK_DIV_4 (2 << 3) 256 #define CKG_ODCLK_CLK_LPLL (3 << 3) 257 258 259 #define REG_CKG_ODCLK_MFT REG_CLKGEN0_53_L 260 #define CKG_ODCLK_MFT_GATED BIT(8) 261 #define CKG_ODCLK_MFT_INVERT BIT(9) 262 #define CKG_ODCLK_MFT_SEL_SOURCE BIT(10) 263 #define CKG_ODCLK_MFT_SEL_SYNTHETIC (0 << 10) 264 #define CKG_ODCLK_MFT_SEL_LPLL (1 << 10) 265 #define CKG_ODCLK_MFT_MASK (BIT(11) | BIT(12)) 266 #define CKG_ODCLK_MFT_CLK_DIV_2 (0 << 11) 267 #define CKG_ODCLK_MFT_XTAL (1 << 11) 268 #define CKG_ODCLK_MFT_CLK_DIV_4 (2 << 11) 269 #define CKG_ODCLK_MFT_CLK_LPLL (3 << 11) 270 271 272 #define REG_CKG_TX_MOD REG_CLKGEN0_58_L 273 #define CKG_TX_MOD_GATED BIT(0) 274 #define CKG_TX_MOD_INVERT BIT(1) 275 #define CKG_TX_MOD_MASK (BIT(3) | BIT(2)) 276 #define CKG_TX_1X_4XDIGITAL (0 << 2) 277 278 #define PANEL_LPLL_INPUT_DIV_1st 0x00 279 #define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 280 #define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8 281 #define PANEL_LPLL_LOOP_DIV_2nd 0x01 // 282 #define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 283 #define PANEL_LPLL_OUTPUT_DIV_2nd 0x00 284 285 #define LVDS_MPLL_CLOCK_MHZ 432 // For crystal 24Mhz 286 #define LVDS_SPAN_FACTOR 131072 287 288 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 289 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 290 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 291 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 292 293 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 294 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 295 296 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 297 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 298 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 299 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 300 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 301 302 #define SUPPORT_MOD_ADBANK_SEPARATE 303 304 #define SUPPORT_VBY1_HWTRAINING_MODE 305 306 307 //for auto set output config and clk according to pin mapping 308 #define CONFIG_FOR_VBY1_DATA 0x01 309 #define CONFIG_FOR_VBY1_DATA_BIT_NUM 2 310 311 #define VBY1_CLK_TBL_ROW 4 312 313 //------------------------------------------------------------------------------------------------- 314 // Type and Structure 315 //------------------------------------------------------------------------------------------------- 316 typedef enum 317 { 318 E_HALPNL_DEVICE0_XC_BANK_OFFSET = 0, 319 E_HALPNL_DEVICE1_XC_BANK_OFFSET = 0x80 320 }PNL_HAL_DEVICE_XC_BANK_OFFSET; 321 322 typedef enum 323 { 324 E_DRVPNL_ALLIN_MODE = 1, 325 E_DRVPNL_2X_MODE = 2, 326 E_DRVPNL_SEPARATE_MODE = 3, 327 E_DRVPNL_TYPE_NUM 328 }DRVPNL_OUT_SWING_TYPE; 329 330 typedef enum 331 { 332 HAL_TI_10BIT_MODE = 0, 333 HAL_TI_8BIT_MODE = 2, 334 HAL_TI_6BIT_MODE = 3, 335 } PNL_HAL_TIMODES; 336 337 //------------------------------------------------------------------------------------------------- 338 // Function and Variable 339 //------------------------------------------------------------------------------------------------- 340 HAL_PNL_INTERFACE MS_VIRT g_ptr_PnlRiuBaseAddr; 341 HAL_PNL_INTERFACE MS_VIRT g_ptr_PMRiuBaseAddr; 342 343 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 344 void MHal_PNL_TCON_Init(void *pInstance); 345 346 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 347 348 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type); 349 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 350 void MHal_Output_Channel_Order(void *pInstance, MS_U8 Type, MS_U16 u16OutputOrder0_3, MS_U16 u16OutputOrder4_7, MS_U16 u16OutputOrder8_11, MS_U16 u16OutputOrder12_13); 351 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance); 352 353 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 354 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance); 355 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping); 356 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue); 357 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue); 358 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); 359 #ifdef MONACO_SC2 360 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode ); 361 #endif 362 #define Hal_PNL_Get12BitGammaPerChannel(args...) 363 //void _MDrv_PNL_Set_12BIT_Gamma(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab); 364 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src); 365 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz); 366 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 367 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 368 369 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance); 370 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 371 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 372 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_PHY u32OD_LSB_Addr, MS_PHY u32OD_LSB_limit, MS_U8 u8MIUSel); 373 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 374 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]); 375 376 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 377 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance); 378 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 379 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 380 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level); 381 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select); 382 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level); 383 384 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData); 385 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData); 386 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask); 387 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 388 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 389 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance); 390 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); 391 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 392 393 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank); 394 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz); 395 396 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank); 397 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance); 398 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance); 399 400 401 /// Set pair swap for user mode 402 #define MHal_FRC_MOD_PairSwap_UserMode(args...) 403 404 #define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC 405 406 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz); 407 408 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance); 409 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance); 410 411 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable); 412 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance); 413 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat); 414 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 415 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 416 417 void MHal_PNL_Set_T3D_Setting(void *pInstance); 418 419 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance); 420 void MHal_PNL_Init(void *pInstance); 421 void MHal_PNL_Bringup(void *pInstance); 422 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance); 423 424 MS_U16 MHal_PNL_GetPanelVStart(void); 425 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance); 426 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable); 427 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance); 428 void MHal_PNL_TCON_Patch(void); 429 430 431 #ifdef __cplusplus 432 } 433 #endif 434 435 #endif // _HAL_PNL_H_ 436 437