1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _HAL_PNL_C_
79 #define _HAL_PNL_C_
80
81 //-------------------------------------------------------------------------------------------------
82 // Include Files
83 //-------------------------------------------------------------------------------------------------
84
85 #include "MsCommon.h"
86 #include "MsTypes.h"
87 #include "utopia.h"
88 #include "utopia_dapi.h"
89 #include "apiPNL.h"
90 #include "apiPNL_v2.h"
91 #include "drvPNL.h"
92 #include "halPNL.h"
93 #include "PNL_private.h"
94 #include "pnl_hwreg_utility2.h"
95 #include "Manhattan_pnl_lpll_tbl.h"
96 #include "Manhattan_pnl_lpll_ext_tbl.h"
97
98 #ifdef MSOS_TYPE_LINUX_KERNEL
99 #include <linux/string.h>
100 #include <linux/delay.h>
101 #include <asm/div64.h>
102 #else
103 #include "string.h"
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114
115 #define UNUSED(x) (x=x)
116 #if 1
117 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) printf("PNL:"_fmt, ##_args); }
118 #define HAL_MOD_CAL_DBG(x) //x
119 #else
120 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { }
121 #endif
122
123 #define DAC_LPLL_ICTRL 0x0002
124 #define LVDS_LPLL_ICTRL 0x0001
125
126 //Get MOD calibration time
127 #define MOD_CAL_TIMER FALSE
128
129 //-------------------------------------------------------------------------------------------------
130 // Local Structurs
131 //-------------------------------------------------------------------------------------------------
132
133 //-------------------------------------------------------------------------------------------------
134 // Global Variables
135 //-------------------------------------------------------------------------------------------------
136
137 //-------------------------------------------------------------------------------------------------
138 // Local Variables
139 //-------------------------------------------------------------------------------------------------
140
141 //-------------------------------------------------------------------------------------------------
142 // Debug Functions
143 //-------------------------------------------------------------------------------------------------
144
145 //-------------------------------------------------------------------------------------------------
146 // Local Functions
147 //-------------------------------------------------------------------------------------------------
148
149 //-------------------------------------------------------------------------------------------------
150 // Global Function
151 //-------------------------------------------------------------------------------------------------
152 /**
153 * @brief: Power On MOD. but not mutex protected
154 *
155 */
MHal_MOD_PowerOn(void * pInstance,MS_BOOL bEn,MS_U8 u8LPLL_Type,MS_U8 DualModeType,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)156 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
157 {
158 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
159 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
160 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
161 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
162
163 if( bEn )
164 {
165 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8));
166
167 //analog MOD power down. 1: power down, 0: power up
168 // For Mod2 no output signel
169 ///////////////////////////////////////////////////
170
171 //2. Power on MOD (current and regulator)
172 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0));
173 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8));
174
175
176 // 3. 4. 5.
177 MHal_Output_LVDS_Pair_Setting(pInstance, DualModeType, u16OutputCFG0_7, u16OutputCFG8_15, u16OutputCFG16_21);
178
179
180 //enable ib, enable ck
181 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0)));
182
183 // clock gen of dot-mini
184 if(u8LPLL_Type == E_PNL_TYPE_MINILVDS)
185 {
186 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x4400);
187 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x4400);
188 }
189 else if((u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
190 (u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)||
191 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE) ||
192 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_2LANE))
193
194 {
195 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
196 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
197 // [7:4]reg_ckg_dot_mini_pre_osd
198 }
199 //// for osd dedicated output port, 1 port for video and 1 port for osd
200 else if((u8LPLL_Type == E_PNL_TYPE_HS_LVDS)&&
201 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
202 {
203 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
204 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
205 // [7:4]reg_ckg_dot_mini_pre_osd
206 }
207 else if(u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
208 {
209 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); // [11:8]reg_ckg_dot_mini_pre2_osd
210 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
211 }
212 else
213 {
214 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0000);
215 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0000);
216 }
217 }
218 else
219 {
220 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8));
221 if(u8LPLL_Type !=E_PNL_TYPE_MINILVDS)
222 {
223 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: power up
224 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8));
225 }
226
227 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib, enable ck
228
229 // clock gen of dot-mini
230 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x1100);
231 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x1100);
232
233 if((u8LPLL_Type>=E_PNL_LPLL_VBY1_10BIT_4LANE)&&(u8LPLL_Type<=E_PNL_LPLL_VBY1_8BIT_8LANE))
234 {
235 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
236 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
237 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
238 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
239 }
240 }
241 return 1;
242 }
243
244 /**
245 * @brief: Setup the PVDD power 1:2.5V, 0:3.3V
246 *
247 */
MHal_MOD_PVDD_Power_Setting(void * pInstance,MS_BOOL bIs2p5)248 void MHal_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5)
249 {
250 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, ((bIs2p5)? BIT(6):0), BIT(6)); //MOD PVDD=1: 0.9
251 }
252
MHal_PNL_TCON_Init(void * pInstance)253 void MHal_PNL_TCON_Init(void *pInstance)
254 {
255
256 }
257
MHal_Shift_LVDS_Pair(void * pInstance,MS_U8 Type)258 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type)
259 {
260 if(Type == 1)
261 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LVDS Mode3
262 else
263 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6)));
264
265 }
266
MHal_Output_LVDS_Pair_Setting(void * pInstance,MS_U8 Type,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)267 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
268 {
269
270 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
271 {
272 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
273 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x1554);
274 }
275 else if(Type == LVDS_SINGLE_OUTPUT_A)
276 {
277 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
278 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
279 }
280 else if( Type == LVDS_SINGLE_OUTPUT_B)
281 {
282 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
283 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
284 }
285 else if( Type == LVDS_OUTPUT_User)
286 {
287 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16OutputCFG0_7);
288 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16OutputCFG8_15);
289 }
290 else
291 {
292 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
293 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
294 }
295
296 MsOS_DelayTask(2);
297
298
299 }
300
MHal_Output_Channel_Order(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)301 void MHal_Output_Channel_Order(void *pInstance,
302 MS_U8 Type,
303 MS_U16 u16OutputOrder0_3,
304 MS_U16 u16OutputOrder4_7,
305 MS_U16 u16OutputOrder8_11,
306 MS_U16 u16OutputOrder12_13)
307 {
308 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
309 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
310 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
311 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
312
313 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
314 {
315 MOD_W2BYTE(REG_MOD_BK00_08_L, u16OutputOrder0_3);
316 MOD_W2BYTE(REG_MOD_BK00_09_L, u16OutputOrder4_7);
317 MOD_W2BYTE(REG_MOD_BK00_0A_L, u16OutputOrder8_11);
318 MOD_W2BYTE(REG_MOD_BK00_0B_L, u16OutputOrder12_13);
319 }
320 else
321 {
322 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
323 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
324 {
325 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // 2 Divisoin
326 {
327 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x6420);
328 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7531);
329 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
330 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
331 }
332 else
333 {
334 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x3210);
335 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x7654);
336 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0xBA98);
337 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
338 }
339 }
340 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
341 {//LVDS
342 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x10DC);
343 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x5432);
344 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x9876);
345 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x00BA);
346 }
347 else
348 {
349 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x76DC);
350 MOD_W2BYTE(REG_MOD_BK00_09_L, 0xBA98);
351 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x3210);
352 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0054);
353 }
354 }
355
356 }
357
MHal_PQ_Clock_Gen_For_Gamma(void * pInstance)358 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance)
359 {
360 W2BYTEMSK(REG_CLKGEN0_52_L, 0x00, 0x07);
361 }
362
MHal_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)363 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping)
364 {
365 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
366 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
367
368 if(u8Mapping & GAMMA_MAPPING)
369 {
370 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_74_L, (u8Mapping & GAMMA_10BIT_MAPPING)? BIT(15):0, BIT(15));
371 }
372 else
373 {
374 PNL_ASSERT(0, "Invalid eSupportGammaMapMode [%d] Passed to [%s], please make sure the u8Mapping[%d] is valid\n.",
375 u8Mapping, __FUNCTION__, u8Mapping);
376 }
377 }
378
Hal_VOP_Is_GammaMappingMode_enable(void * pInstance)379 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance)
380 {
381 // Only support 1024 entry
382 return TRUE;
383 }
384
385 // After A5, 8 bit mode only support burst write!!!
Hal_VOP_Is_GammaSupportSignalWrite(void * pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)386 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)
387 {
388 if( u8Mapping == E_DRVPNL_GAMMA_10BIT_MAPPING )
389 return TRUE;
390 else
391 return FALSE;
392 }
393
394
hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)395 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
396 {
397 MS_U16 u16Delay = 0xFFFF;
398 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
399 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
400
401 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write SC%tu [ch %d][addr 0x%x]: 0x%x \n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16Addr, u16GammaValue);
402
403 if (!bBurstWrite )
404 {
405 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
406 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
407
408 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6C_L, u16Addr, 0x3FF); // set address port
409 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_6E_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
410
411 // kick off write
412 switch(u8Channel)
413 {
414 case 0: // Red
415 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(5), BIT(5));
416 break;
417
418 case 1: // Green
419 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(6), BIT(6));
420 break;
421
422 case 2: // Blue
423 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(7), BIT(7));
424 break;
425 }
426
427 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
428 }
429 else
430 {
431 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6E_L, u16GammaValue, 0xFFF);
432 }
433
434
435 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
436
437 }
438
439
hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)440 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
441 {
442 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
443 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
444
445 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of SC%tu %d is 0x%x\n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16MaxGammaValue);
446 #ifdef MONACO_SC2
447 if(pPNLInstancePrivate->u32DeviceID == 0)
448 {
449 #endif
450 switch(u8Channel)
451 {
452 case 0: // max. Red
453 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 0
454 break;
455
456 case 1: // max. Green
457 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 1
458 break;
459
460 case 2: //max. Blue
461 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
462 break;
463 }
464 #ifdef MONACO_SC2
465 }else //Nike
466 {
467 switch(u8Channel)
468 {
469 case 0: // max. Red
470 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7A_L , u16MaxGammaValue, 0xFFF); // max. base 0
471 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7B_L , u16MaxGammaValue, 0xFFF); // max. base 1
472 break;
473
474 case 1: // max. Green
475 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7C_L , u16MaxGammaValue, 0xFFF); // max. base 0
476 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 1
477 break;
478
479 case 2: //max. Blue
480 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 0
481 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
482 break;
483 }
484
485 }
486 #endif
487 }
488
489 /////////////////////////////////////////////////////////////////////////////
490 // Gamma format (12 bit LUT)
491 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
492 // 1 set uses 2 bytes of memory.
493 //
494 // [T2 and before ] N = 256
495 // [T3] N = 256 or 1024
496 // ______________________________________________________________________________
497 // Byte | 0 1 2 n-1 n
498 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
499 // 3:0 3:0 11:4 11:4 3:0 11:4
500 //
501
Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)502 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
503 {
504 MS_U16 i , j ;
505 MS_U16 u16Addr = 0;
506 MS_U16 u16GammaValueR[4] = {0, 0, 0, 0};
507 MS_U16 u16GammaDeltaR[3] = {0, 0, 0};
508 MS_U16 u16MaxGammaValue1 = 0;
509 MS_U16 u16MaxGammaValue = 0;
510 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
511 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance, GammaMapMode);
512 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
513 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
514
515 bUsingBurstWrite = bUsingBurstWrite;
516
517 if (u8Channel >= 3 )
518 return;
519
520 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_71_L, 0x00 , 0x00FF); //Initial write address, GAMMA_ADR[7:0]
521 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_72_L, 0x00, 0xFFFF); // Initial GAMMA_DATA[26:0]
522 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_73_L, 0x00, 0x07FF); // Initial GAMMA_DATA[26:0]
523
524 //Select write channel, GAMMA_CH_SEL[1:0] .
525 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L, u8Channel<<5 , BIT(5)| BIT(6));
526
527 if(bUsingBurstWrite)
528 {
529 //Enable burst write mode, GAMMA_BW_EN .
530 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L, BIT(7) , BIT(7));
531 }
532
533 if (( GammaMapMode ==E_DRVPNL_GAMMA_10BIT_MAPPING))//For 1024 Entry Mode
534 {
535 // write ref of one entry of gamma table, WR_R[11:0]
536 for (i = 0; u16Addr < u16NumOfLevel/4; i += 6)
537 {
538 // gamma x of R
539 u16GammaValueR[0] = u8Tab[i] & 0x0F;
540 u16GammaValueR[0] |= (MS_U16)u8Tab[i+1] << 4;
541
542 // gamma x+1 of R
543 u16GammaValueR[1] = (u8Tab[i] & 0xF0) >> 4;
544 u16GammaValueR[1] |= (MS_U16)u8Tab[i+2] << 4;
545
546 // gamma x+2 of R
547 u16GammaValueR[2] = u8Tab[i+3] & 0x0F;
548 u16GammaValueR[2] |= (MS_U16)u8Tab[i+4] << 4;
549
550 // gamma x+3 of R
551 u16GammaValueR[3] = (u8Tab[i+3] & 0xF0) >> 4;
552 u16GammaValueR[3] |= (MS_U16)u8Tab[i+5] << 4;
553
554 for (j = 0; j < 3; j ++)
555 {
556 u16GammaDeltaR[j] = abs(u16GammaValueR[j+1] - u16GammaValueR[j]);
557 }
558
559 u16MaxGammaValue1 = MAX(MAX(u16GammaValueR[0],u16GammaValueR[1]),MAX(u16GammaValueR[2],u16GammaValueR[3]));
560
561 if(u16MaxGammaValue < u16MaxGammaValue1)
562 {
563 u16MaxGammaValue = u16MaxGammaValue1;
564 }
565
566 if(!bUsingBurstWrite) //Normal write mode
567 {
568 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_71_L, u16Addr, 0x00FF); // Set write address, GAMMA_ADR[7:0] .
569 }
570
571 u16GammaDeltaR[0]=(((u16GammaValueR[0]<<15)&0x8000)|((u16GammaDeltaR[0]<<10)&0x7C00)|
572 ((u16GammaDeltaR[1]<<5)&0x03E0)|((u16GammaDeltaR[2]<<0)&0x001F));
573 //write ref of one entry of gamma table, GAMMA_DATA[26:0]
574 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_73_L, u16GammaValueR[0]>>1, 0x07FF);
575 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_72_L, u16GammaDeltaR[0]);
576
577 if(!bUsingBurstWrite) //Normal write mode
578 {
579 //After finish normal write mode,toggle write pulse, GAMMA_WR_EN.
580 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L,BIT(3),BIT(3));
581 while ( SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L,BIT(3)));
582 }
583 u16Addr ++ ; // Continue to write next entry of gamma table .
584 }
585 }
586 else //For 256 Entry Mode
587 {
588 // write ref of one entry of gamma table, WR_R[11:0]
589 for(i = 0; u16Addr < u16NumOfLevel; i += 3)
590 {
591 // gamma x
592 u16GammaValueR[0] = u8Tab[i] & 0x0F;
593 u16GammaValueR[0] |= u8Tab[i+1] << 4;
594
595 // gamma x+1
596 u16GammaValueR[1] = (u8Tab[i] & 0xF0) >> 4;
597 u16GammaValueR[1] |= u8Tab[i+2] << 4;
598
599 // gamma x+2
600 u16GammaValueR[2] = u8Tab[i+3] & 0x0F;
601 u16GammaValueR[2] |= u8Tab[i+4] << 4;
602
603 u16MaxGammaValue1 = MAX(u16GammaValueR[0],u16GammaValueR[1]);
604
605 if(u16MaxGammaValue < u16MaxGammaValue1)
606 {
607 u16MaxGammaValue = u16MaxGammaValue1;
608 }
609
610 if(!bUsingBurstWrite) //Normal write mode
611 {
612 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_71_L, u16Addr,0x00FF); // set write address, GAMMA_ADR[7:0]
613 }
614
615 u16GammaDeltaR[0] = ( u16GammaValueR[1] - u16GammaValueR[0] ) / 4;
616 u16GammaDeltaR[0] = ((u16GammaValueR[0]<<15)&0x8000) | ((u16GammaDeltaR[0]<<10)&0x7C00)
617 |((u16GammaDeltaR[0]<<5)&0x03E0) | ((u16GammaDeltaR[0]&0x001F));
618 //write ref of one entry of gamma table, GAMMA_DATA[26:0]
619 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_73_L, u16GammaValueR[0]>>1, 0x07FF);
620 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_72_L, u16GammaDeltaR[0] , 0xFFFF);
621
622 if(!bUsingBurstWrite) //Normal write mode
623 {
624 //After finish normal write mode,toggle write pulse, GAMMA_WR_EN.
625 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L,BIT(3),BIT(3));
626 while ( SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L,BIT(3)));
627 }
628 u16Addr ++ ; // continue to write next entry of gamma table
629
630
631 if(!bUsingBurstWrite) //Normal write mode
632 {
633 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_71_L, u16Addr,0x00FF); // set write address, GAMMA_ADR[7:0]
634 }
635
636 u16GammaDeltaR[1] = ( u16GammaValueR[2] - u16GammaValueR[1] ) / 4;
637 u16GammaDeltaR[1] = ((u16GammaValueR[1]<<15)&0x8000) | ((u16GammaDeltaR[1]<<10)&0x7C00)
638 |((u16GammaDeltaR[1]<<5)&0x03E0) | ((u16GammaDeltaR[1]&0x001F));
639 //write ref of one entry of gamma table, GAMMA_DATA[26:0]
640 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_73_L, u16GammaValueR[1]>>1, 0x07FF);
641 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_72_L, u16GammaDeltaR[1], 0xFFFF);
642
643 if(!bUsingBurstWrite) //Normal write mode
644 {
645 //After finish normal write mode,toggle write pulse, GAMMA_WR_EN.
646 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L,BIT(3),BIT(3));
647 while ( SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L,BIT(3)));
648 }
649 u16Addr ++ ; // continue to write next entry of gamma table
650 }
651 }
652
653 if(bUsingBurstWrite)
654 {
655 //After finish burst write data of one channel, disable burst write mode .
656 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_70_L, 0x00 , BIT(7));
657 }
658 hal_PNL_SetMaxGammaValue(pInstance, u8Channel, u16MaxGammaValue);
659
660 }
661 /////////////////////////////////////////////////////////////////////////////
662 // Gamma format (12 bit LUT)
663 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
664 // 1 set uses 2 bytes of memory.
665 //
666 // [T2 and before ] N = 256
667 // [T3] N = 256 or 1024
668 // ______________________________________________________________________________
669 // Byte | 0 1 2 n-1 n
670 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
671 // 3:0 3:0 11:4 11:4 3:0 11:4
672 //
673 #ifdef MONACO_SC2
Hal_PNL_Set12BitGammaPerChannel_SC2(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)674 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
675 {
676 MS_U16 u16Addr = 0;
677 MS_U16 u16CodeTableIndex = u16Addr/2*3;
678 MS_U16 u16GammaValue = 0;
679 MS_U16 u16MaxGammaValue = 0;
680 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
681 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
682 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
683 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
684
685 // Go to burst write if not support
686 if ( bUsingBurstWrite )
687 {
688 // 1. initial burst write address, LUT_ADDR[7:0]
689 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
690
691 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
692 switch(u8Channel)
693 {
694 case 0: // Red
695 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
696 break;
697
698 case 1: // Green
699 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
700 break;
701
702 case 2: // Blue
703 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
704 break;
705 }
706
707 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
708 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
709
710 }
711
712 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
713 // write gamma table per one channel
714 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
715 {
716 // gamma x
717 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
718 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
719
720 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
721 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
722
723 if(u16MaxGammaValue < u16GammaValue)
724 {
725 u16MaxGammaValue = u16GammaValue;
726 }
727
728 // write gamma value
729 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
730 u16Addr++;
731
732 // gamma x+1
733 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
734 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
735
736 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
737
738 if(u16MaxGammaValue < u16GammaValue)
739 {
740 u16MaxGammaValue = u16GammaValue;
741 }
742
743 // write gamma value
744 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
745 u16Addr++;
746 }
747
748 if ( bUsingBurstWrite )
749 {
750 // 5. after finish burst write data of one channel, disable burst write mode
751 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(0));
752 }
753
754 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
755 }
756 #endif
757 // src : 1 (scaler lpll)
758 // src : 0 (frc lpll)
MHal_PNL_FRC_lpll_src_sel(void * pInstance,MS_U8 u8src)759 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src)
760 {
761 if (u8src > 1)
762 {
763 return FALSE;
764 }
765 else
766 {
767 //Not support two LPLL (frc lpll) for Manhattan
768 #if 0
769 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F);
770 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8));
771
772 if(u8src==0)
773 {
774 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F);
775 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8));
776 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0
777 }
778 #endif
779 return TRUE;
780 }
781
782 }
783
_MHal_PNL_GetSupportedLPLLIndex(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz,PNL_LPLL_TYPE_SEL lpll_type_sel)784 static MS_U8 _MHal_PNL_GetSupportedLPLLIndex(void *pInstance,
785 PNL_TYPE eLPLL_Type,
786 PNL_MODE eLPLL_Mode,
787 MS_U64 ldHz, PNL_LPLL_TYPE_SEL lpll_type_sel)
788 {
789 MS_U8 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
790 #if defined (__aarch64__)
791 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
792 #else
793 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
794 #endif
795
796 /// Mini LVDS, EPI34/28, LVDS_1CH, Vx1_1P are 1P structure
797 if(!((eLPLL_Type == E_PNL_TYPE_TTL)||
798 ((eLPLL_Type == E_PNL_TYPE_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
799 ((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
800 (eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_1LANE)||(eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_1LANE)||
801 ((eLPLL_Type >= E_PNL_LPLL_MINILVDS_2CH_3P_8BIT)&&(eLPLL_Type <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT))||
802 ((eLPLL_Type >= E_PNL_LPLL_EPI34_2P)&&(eLPLL_Type <= E_PNL_LPLL_EPI28_4P))))
803 {
804 ldHz/=2;
805 }
806
807 switch(lpll_type_sel)
808 {
809 default:
810 case E_PNL_LPLL_VIDEO:
811 {
812 switch (eLPLL_Type)
813 {
814 case E_PNL_TYPE_TTL:
815 if (ldHz < 250000000)
816 {
817 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to25MHz;
818 }
819 else if ((ldHz >= 250000000) && (ldHz < 500000000))
820 {
821 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to50MHz;
822 }
823 else if((ldHz >= 500000000) && (ldHz < 1000000000))
824 {
825 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_50to100MHz;
826 }
827 else
828 {
829 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_100to150MHz;
830 }
831 break;
832
833 case E_PNL_TYPE_LVDS:
834 switch (eLPLL_Mode)
835 {
836 case E_PNL_MODE_SINGLE:
837 if (ldHz < 500000000)
838 {
839 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz;
840 }
841 else
842 {
843 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz;
844 }
845 break;
846
847 default:
848 case E_PNL_MODE_DUAL:
849 if (ldHz < 250000000)
850 {
851 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz;
852 }
853 else if ((ldHz >= 250000000) && (ldHz < 500000000))
854 {
855 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz;
856 }
857 else
858 {
859 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz;
860 }
861 break;
862 }
863 break;
864
865 case E_PNL_TYPE_HS_LVDS:
866
867 switch (eLPLL_Mode)
868 {
869 case E_PNL_MODE_SINGLE:
870 if(ldHz < 500000000)
871 {
872 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz;
873 }
874 else if((ldHz >= 500000000) && (ldHz < 1150000000))
875 {
876 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz;
877 }
878 else
879 {
880 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz;
881 }
882 break;
883
884 default:
885 case E_PNL_MODE_DUAL:
886 if(ldHz < 250000000)
887 {
888 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz;
889 }
890 else if((ldHz >= 250000000) && (ldHz < 570000000))
891 {
892 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz;
893 }
894 else if((ldHz >= 570000000) && (ldHz < 1150000000UL))
895 {
896 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz;
897 }
898 else
899 {
900 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz;
901 }
902 break;
903 }
904 break;
905 ///Not Support
906 #if 0
907 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
908 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz;
909 break;
910
911 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
912 if((ldHz >= 500000000) && (ldHz < 1000000000))
913 {
914 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz;
915 }
916 else
917 {
918 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz;
919 }
920 break;
921
922 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
923 if((ldHz >= 500000000) && (ldHz < 1000000000))
924 {
925 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz;
926 }
927 else
928 {
929 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz;
930 }
931 break;
932
933 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
934 if((ldHz >= 500000000) && (ldHz < 666700000))
935 {
936 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz;
937 }
938 else
939 {
940 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz;
941 }
942 break;
943
944 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
945 if ((ldHz <= 500000000) && (ldHz < 666700000))
946 {
947 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz;
948 }
949 else if((ldHz >= 666700000) && (ldHz < 1333300000))
950 {
951 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz;
952 }
953 else
954 {
955 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz;
956 }
957 break;
958
959 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
960 if ((ldHz <= 500000000) && (ldHz < 670000000))
961 {
962 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz;
963 }
964 else if((ldHz >= 670000000) && (ldHz < 1330000000))
965 {
966 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz;
967 }
968 else
969 {
970 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz;
971 }
972 break;
973
974 case E_PNL_LPLL_EPI34_4P:
975 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_95to150MHz;
976 break;
977
978 case E_PNL_LPLL_EPI34_6P:
979 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz;
980 break;
981
982 case E_PNL_LPLL_EPI34_8P:
983 if((ldHz >= 800000000) && (ldHz < 940000000))
984 {
985 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to94MHz;
986 }
987 else if((ldHz >= 940000000) && (ldHz < 1880000000))
988 {
989 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_94to188MHz;
990 }
991 else
992 {
993 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz;
994 }
995 break;
996
997 case E_PNL_LPLL_EPI28_4P:
998 if((ldHz >= 800000000) && (ldHz < 1140000000))
999 {
1000 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz;
1001 }
1002 else
1003 {
1004 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz;
1005 }
1006 break;
1007
1008 case E_PNL_LPLL_EPI28_6P:
1009 if((ldHz >= 800000000) && (ldHz < 1720000000))
1010 {
1011 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_80to172MHz;
1012 }
1013 else
1014 {
1015 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_172to300MHz;
1016 }
1017 break;
1018
1019 case E_PNL_LPLL_EPI28_8P:
1020 if((ldHz >= 800000000) && (ldHz < 1140000000))
1021 {
1022 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_80to114MHz;
1023 }
1024 else if((ldHz >= 1140000000UL) && (ldHz < 2280000000UL))
1025 {
1026 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_114to228MHz;
1027 }
1028 else
1029 {
1030 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_228to300MHz;
1031 }
1032 break;
1033 #endif
1034 case E_PNL_LPLL_EPI28_12P:
1035 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_V15_330to330MHz;
1036 break;
1037 /*
1038 case E_PNL_LPLL_EPI34_12P:
1039 case E_PNL_LPLL_EPI24_12P:
1040 break;
1041 */
1042
1043 case E_PNL_LPLL_VBY1_10BIT_8LANE:
1044 if(ldHz < 1500000000)
1045 {
1046 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz;
1047 }
1048 else
1049 {
1050 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to340MHz;
1051 }
1052 printf("@@11=%u\n",u8SupportedLPLLIndex);
1053 break;
1054
1055 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1056 if(ldHz < 750000000)
1057 {
1058 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz;
1059 }
1060 else
1061 {
1062 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz;
1063 }
1064 break;
1065
1066 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1067 if(ldHz < 380000000)
1068 {
1069 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to38MHz;
1070 }
1071 else
1072 {
1073 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz;
1074 }
1075 break;
1076
1077 case E_PNL_LPLL_VBY1_8BIT_8LANE:
1078 if(ldHz < 1500000000UL)
1079 {
1080 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz;
1081 }
1082 else if((ldHz >= 1500000000UL) && (ldHz < 2200000000UL))
1083 {
1084 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz;
1085 }
1086 else
1087 {
1088 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to340MHz;
1089 }
1090 break;
1091
1092 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1093 if(ldHz < 750000000)
1094 {
1095 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz;
1096 }
1097 else if((ldHz >= 750000000) && (ldHz < 1100000000))
1098 {
1099 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz;
1100 }
1101 else
1102 {
1103 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz;
1104 }
1105 break;
1106
1107 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1108 if(ldHz < 380000000)
1109 {
1110 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to55MHz;
1111 }
1112 else if((ldHz >= 380000000) && (ldHz < 550000000))
1113 {
1114 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to55MHz;
1115 }
1116 else
1117 {
1118 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz;
1119 }
1120 break;
1121
1122 default:
1123 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1124 break;
1125 }
1126 }
1127 break;
1128 case E_PNL_LPLL_OSD:
1129 {
1130 switch (eLPLL_Type)
1131 {
1132 case E_PNL_TYPE_HS_LVDS:
1133 {
1134 if(ldHz < 250000000)
1135 {
1136 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz;
1137 }
1138 else if((ldHz >= 250000000) && (ldHz < 570000000))
1139 {
1140 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz;
1141 }
1142 else if((ldHz >= 570000000) && (ldHz < 1150000000))
1143 {
1144 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz;
1145 }
1146 else
1147 {
1148 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz;
1149 }
1150 }
1151 break;
1152
1153 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1154 if(ldHz < 1500000000)
1155 {
1156 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to150MHz;
1157 }
1158 else
1159 {
1160 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz;
1161 }
1162 break;
1163
1164 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1165 if(ldHz < 750000000)
1166 {
1167 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to75MHz;
1168 }
1169 else
1170 {
1171 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz;
1172 }
1173 break;
1174
1175 case E_PNL_LPLL_VBY1_10BIT_1LANE:
1176 if(ldHz < 380000000)
1177 {
1178 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to38MHz;
1179 }
1180 else
1181 {
1182 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to75MHz;
1183 }
1184 break;
1185
1186 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1187 if(ldHz < 1500000000UL)
1188 {
1189 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to150MHz;
1190 }
1191 else if((ldHz >= 1500000000UL) && (ldHz < 2200000000UL))
1192 {
1193 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz;
1194 }
1195 else
1196 {
1197 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz;
1198 }
1199 break;
1200
1201 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1202 if(ldHz < 750000000)
1203 {
1204 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to75MHz;
1205 }
1206 else if((ldHz >= 750000000) && (ldHz < 1100000000))
1207 {
1208 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz;
1209 }
1210 else
1211 {
1212 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz;
1213 }
1214 break;
1215
1216 case E_PNL_LPLL_VBY1_8BIT_1LANE:
1217 if(ldHz < 380000000)
1218 {
1219 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to38MHz;
1220 }
1221 else if((ldHz >= 380000000) && (ldHz < 550000000))
1222 {
1223 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to55MHz;
1224 }
1225 else
1226 {
1227 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz;
1228 }
1229 break;
1230
1231 default:
1232 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
1233 break;
1234 }
1235 }
1236 break;
1237 }
1238 return u8SupportedLPLLIndex;
1239 }
1240
_MHal_PNL_DumpLPLLTable(void * pInstance,MS_U8 LPLLTblIndex,PNL_LPLL_TYPE_SEL lpll_type_sel)1241 static void _MHal_PNL_DumpLPLLTable(void *pInstance, MS_U8 LPLLTblIndex, PNL_LPLL_TYPE_SEL lpll_type_sel)
1242 {
1243 if(lpll_type_sel == E_PNL_LPLL_VIDEO)
1244 {
1245 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_MAX)
1246 {
1247 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1248 return;
1249 }
1250
1251 int indexCounter = 0;
1252
1253 for(indexCounter = 0 ; indexCounter<LPLL_REG_NUM; indexCounter++)
1254 {
1255 if (LPLLSettingTBL[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1256 {
1257 MsOS_DelayTaskUs(LPLLSettingTBL[LPLLTblIndex][indexCounter].value);
1258 continue; // step forward to next register setting.
1259 }
1260
1261 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address),
1262 LPLLSettingTBL[LPLLTblIndex][indexCounter].value,
1263 LPLLSettingTBL[LPLLTblIndex][indexCounter].mask);
1264 }
1265 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1266 }
1267 else
1268 {
1269 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
1270 {
1271 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1272 return;
1273 }
1274
1275 int indexCounter = 0;
1276
1277 for(indexCounter = 0 ; indexCounter<LPLL_EXT_REG_NUM; indexCounter++)
1278 {
1279 if (LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1280 {
1281 MsOS_DelayTaskUs(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value);
1282 continue; // step forward to next register setting.
1283 }
1284
1285 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address),
1286 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value,
1287 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].mask);
1288 }
1289 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1290 }
1291 }
1292
MHal_PNL_Init_LPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)1293 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
1294 {
1295 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1296 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1297 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1298 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1299 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1300 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1301
1302 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_VIDEO);
1303
1304 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1305 {
1306 printf("Not Supported LPLL Type, skip LPLL Init\n");
1307 return;
1308 }
1309
1310 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_VIDEO);
1311
1312
1313 MHal_MOD_PVDD_Power_Setting(pInstance, pPNLResourcePrivate->sthalPNL._bPVDD_2V5); // Einstein is always use 3.3V PVDD Power.
1314 }
1315
MHal_PNL_Get_Loop_DIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1316 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1317 {
1318 MS_U16 u16loop_div = 0;
1319 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1320 #if defined (__aarch64__)
1321 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1322 #else
1323 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1324 #endif
1325 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1326
1327 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1328 {
1329 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1330 u16loop_div = 0 ;
1331 }
1332 else
1333 {
1334 u16loop_div = u16LoopDiv[u8SupportedLPLLLIndex];
1335 }
1336 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_div=%u\n", u16loop_div);
1337
1338 u16loop_div *= 2;
1339 return u16loop_div;
1340 }
1341
MHal_PNL_Get_LPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1342 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1343 {
1344 MS_U16 u16loop_gain = 0;
1345 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1346 #if defined (__aarch64__)
1347 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1348 #else
1349 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1350 #endif
1351 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1352
1353 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1354 {
1355 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1356 u16loop_gain = 0 ;
1357 }
1358 else
1359 {
1360 u16loop_gain = u16LoopGain[u8SupportedLPLLLIndex];
1361 }
1362 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_gain=%u\n", u16loop_gain);
1363 return u16loop_gain;
1364 }
1365
1366 #define SKIP_TIMING_CHANGE_CAP TRUE
Hal_PNL_SkipTimingChange_GetCaps(void * pInstance)1367 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance)
1368 {
1369 #if (SKIP_TIMING_CHANGE_CAP)
1370 return TRUE;
1371 #else
1372 return FALSE;
1373 #endif
1374 }
1375
MHal_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1376 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1377 {
1378 if (bSetMode == TRUE)
1379 {
1380 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15));
1381 }
1382 else
1383 {
1384 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15));
1385 }
1386 }
1387
MHal_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)1388 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo)
1389 {
1390 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1391 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1392 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1393 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1394
1395 if (lvdsresinfo.bEnable)
1396 {
1397 if (lvdsresinfo.u16channel & BIT(0)) // Channel A
1398 {
1399 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1400 {
1401 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15));
1402 }
1403 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1404 {
1405 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14));
1406 }
1407 }
1408 if (lvdsresinfo.u16channel & BIT(1)) // Channel B
1409 {
1410 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1411 {
1412 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13));
1413 }
1414 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1415 {
1416 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12));
1417 }
1418 }
1419
1420 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)
1421 &&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
1422 {
1423 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14));
1424 }
1425 }
1426 else
1427 {
1428 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12)));
1429
1430 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)
1431 &&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
1432 {
1433 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14));
1434 }
1435 }
1436 }
1437
1438 ////////////////////////////////////////////////////////////////////////
1439 // Turn OD function
1440 ////////////////////////////////////////////////////////////////////////
MHal_PNL_OverDriver_Init(void * pInstance,MS_PHY u32OD_MSB_Addr,MS_PHY u32OD_MSB_limit,MS_PHY u32OD_LSB_Addr,MS_PHY u32OD_LSB_limit,MS_U8 u8MIUSel)1441 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_PHY u32OD_LSB_Addr, MS_PHY u32OD_LSB_limit, MS_U8 u8MIUSel)
1442 {
1443 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1444 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1445 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK16_61_L,u8MIUSel<<8,BIT(8)|BIT(9)); // OD MIU select
1446
1447 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_15_L, (MS_U16)(u32OD_MSB_Addr & 0xFFFF)); // OD MSB request base address
1448 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_16_L, (MS_U16)((u32OD_MSB_Addr >> 16) & 0x00FF), 0x00FF); // OD MSB request base address
1449 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_Addr >> 24) & 0x0003), 0x0003); // OD MSB request base address
1450 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_17_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD MSB request address limit
1451 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_18_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD MSB request address limit
1452 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_limit >> 24) & 0x0003)<<2, 0x000C); // OD MSB request address limit
1453 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_39_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer write address limit
1454 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer write address limit
1455 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3B_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer read address limit
1456 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3C_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer read address limit
1457 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_4F_L, (MS_U16)(u32OD_LSB_Addr & 0xFFFF)); // OD LSB request base address
1458 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_Addr >> 16) & 0x00FF), 0x00FF); // OD LSB request base address
1459 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_limit & 0x00FF) << 8), 0xFF00); // OD LSB request limit address
1460 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_51_L, (MS_U16)((u32OD_LSB_limit >> 8) & 0xFFFF)); // OD LSB request limit address
1461
1462 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1A_L, 0x4020); // OD request rFIFO limit threshold, priority threshold
1463 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1C_L, 0x4020); // OD request wFIFO limit threshold, priority threshold
1464 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x00, BIT(14)); // OD strength gradually bypass
1465 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x2F00, 0x3F00); // OD strength gradually slop
1466 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_12_L, 0x0C, 0xFF); // OD active threshold
1467
1468 }
1469
MHal_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1470 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable)
1471 {
1472 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1473 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1474
1475 // OD mode
1476 // OD used user weight to output blending directly
1477 // OD Enable
1478 if (bEnable)
1479 {
1480 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2D, 0x2F);
1481 }
1482 else
1483 {
1484 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2C, 0x2F);
1485 }
1486 }
1487
MHal_PNL_OverDriver_TBL(void * pInstance,MS_U8 u8ODTbl[1056])1488 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056])
1489 {
1490 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1491 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1492
1493 MS_U16 i;
1494 MS_U8 u8target;
1495 MS_BOOL bEnable;
1496
1497 bEnable = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, BIT(0));
1498 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x00, BIT(0)); // OD enable
1499 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x0E, 0x0E); // OD table SRAM enable, RGB channel
1500
1501 u8target= u8ODTbl[9];
1502 for (i=0; i<272; i++)
1503 {
1504 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_03_L, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
1505 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1506 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, BIT(15)));
1507 }
1508
1509 u8target= u8ODTbl[(272+19)];
1510 for (i=0; i<272; i++)
1511 {
1512 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_06_L, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
1513 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, (i|0x8000), 0x81FF);
1514 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, BIT(15)));
1515 }
1516
1517 u8target= u8ODTbl[(272*2+29)];
1518 for (i=0; i<256; i++)
1519 {
1520 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_09_L, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
1521 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
1522 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, BIT(15)));
1523 }
1524
1525 u8target= u8ODTbl[(272*2+256+39)];
1526 for (i=0; i<256; i++)
1527 {
1528 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0C_L, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
1529 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0B_L, (i|0x8000), 0x81FF);
1530 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0D_L, BIT(15)));
1531 }
1532
1533 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x00, 0x0E); // OD table SRAM enable, RGB channel
1534 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, bEnable, BIT(0)); // OD enable
1535 }
1536
_MHal_PNL_MOD_Swing_Refactor_AfterCAL(void * pInstance,MS_U16 u16Swing_Level)1537 MS_U16 _MHal_PNL_MOD_Swing_Refactor_AfterCAL(void *pInstance, MS_U16 u16Swing_Level)
1538 {
1539 MS_U8 u8ibcal = 0x00;
1540 MS_U16 u16AfterCal_value = 0;
1541 MS_U16 u16Cus_value = 0;
1542
1543 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1544 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1545 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1546 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1547 // =========
1548 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1549 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1550 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1551 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1552 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1553 // =========
1554 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1555 {
1556 default:
1557 case 0:
1558 u8ibcal = 0x15;
1559 break;
1560 case 1:
1561 u8ibcal = 0x1F;
1562 break;
1563 case 2:
1564 u8ibcal = 0x1A;
1565 break;
1566 case 3:
1567 u8ibcal = 0x10;
1568 break;
1569 }
1570 u16Cus_value = (u16Swing_Level) * (pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4)/(u8ibcal + 4);
1571 u16AfterCal_value = (u16Cus_value-40)/10+2;
1572
1573 HAL_MOD_CAL_DBG(printf("\r\n--Swing value after refactor = %d\n", u16AfterCal_value));
1574
1575 return u16AfterCal_value;
1576 }
1577
MHal_PNL_MODSwingRegToRealLevelValue(void * pInstance,MS_U16 u16SwingRegValue)1578 MS_U16 MHal_PNL_MODSwingRegToRealLevelValue(void *pInstance, MS_U16 u16SwingRegValue)
1579 {
1580 MS_U8 u8ibcal = 0x00;
1581 MS_U16 u16SwingRealLevelValue = 0;
1582 MS_U16 u16CusValue = 0;
1583 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1584 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1585 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1586 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1587 // =========
1588 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1589 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1590 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1591 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1592 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1593 // =========
1594 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1595 {
1596 default:
1597 case 0:
1598 u8ibcal = 0x15;
1599 break;
1600 case 1:
1601 u8ibcal = 0x1F;
1602 break;
1603 case 2:
1604 u8ibcal = 0x1A;
1605 break;
1606 case 3:
1607 u8ibcal = 0x10;
1608 break;
1609 }
1610
1611 u16CusValue = ((u16SwingRegValue-2)*10)+40;
1612 u16SwingRealLevelValue=(u16CusValue*(u8ibcal + 4))/(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4);
1613
1614 HAL_MOD_CAL_DBG(printf("\r\n--Swing Real Level Value = %d\n", u16SwingRealLevelValue));
1615
1616 return u16SwingRealLevelValue;
1617 }
1618
MHal_PNL_MOD_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)1619 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level)
1620 {
1621 MS_BOOL bStatus = FALSE;
1622
1623 MS_U16 u16ValidSwing = 0;
1624 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1625 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1626 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1627 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1628
1629 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)||
1630 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS))
1631 {
1632 if(u16Swing_Level>600)
1633 u16Swing_Level=600;
1634 if(u16Swing_Level<40)
1635 u16Swing_Level=40;
1636
1637 u16ValidSwing = _MHal_PNL_MOD_Swing_Refactor_AfterCAL(pInstance, u16Swing_Level);
1638 }
1639 else
1640 {
1641 u16ValidSwing = u16Swing_Level;
1642 }
1643
1644 // Disable HW calibration keep mode first, to make SW icon value can write into register.
1645 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
1646
1647 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
1648 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
1649 {
1650 u16ValidSwing &=0x0F;
1651 // vby1 vreg
1652 // ch0+ch1+ch2+ch3
1653 MOD_A_W2BYTE(REG_MOD_A_BK00_20_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
1654 // ch4+ch5+ch6+ch7
1655 MOD_A_W2BYTE(REG_MOD_A_BK00_21_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
1656 // ch8+ch9+ch10+ch11
1657 MOD_A_W2BYTE(REG_MOD_A_BK00_22_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
1658 // ch12+ch13
1659 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_23_L, (u16ValidSwing << 4 | u16ValidSwing), 0x00ff);
1660 }
1661 else
1662 {
1663 u16ValidSwing &=0xFF;
1664 // LVDS fill ICON
1665 // ch0+ch1
1666 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, (u16ValidSwing << 8 | u16ValidSwing));
1667 // ch2+ch3
1668 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, (u16ValidSwing << 8 | u16ValidSwing));
1669 // ch4+ch5
1670 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, (u16ValidSwing << 8 | u16ValidSwing));
1671 // ch6+ch7
1672 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, (u16ValidSwing << 8 | u16ValidSwing));
1673 // ch8+ch9
1674 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, (u16ValidSwing << 8 | u16ValidSwing));
1675 // ch10+ch11
1676 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, (u16ValidSwing << 8 | u16ValidSwing));
1677 // ch12+ch13
1678 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, (u16ValidSwing << 8 | u16ValidSwing));
1679 }
1680 bStatus = TRUE;
1681
1682 return bStatus;
1683 }
1684
1685 ////////////////////////////////////////////////////////////////////////
1686 // Turn Pre-Emphasis Current function
1687 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_PE_Current(void * pInstance,MS_U16 u16Current_Level)1688 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level)
1689 {
1690 MS_BOOL bStatus = FALSE;
1691 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
1692
1693 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,
1694 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1695 |(u16ValidCurrent << 12 )));
1696
1697 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,
1698 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1699 |(u16ValidCurrent << 12 )));
1700
1701 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,
1702 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1703 |(u16ValidCurrent << 12 )));
1704
1705 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,
1706 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1707 |(u16ValidCurrent << 12 )));
1708
1709 bStatus = TRUE;
1710
1711 return bStatus;
1712 }
1713
MHal_PNL_MOD_PECurrent_Setting(void * pInstance,MS_U16 u16Current_Level,MS_U16 u16Channel_Select)1714 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select)
1715 {
1716 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
1717 MS_U16 u16Ch00_03_mask,u16Ch04_07_mask,u16Ch08_11_mask,u16Ch12_15_mask = 0;
1718
1719 u16Ch00_03_mask = (((u16Channel_Select & BIT(0))? 0x000F:0x00)|((u16Channel_Select & BIT(1))? 0x00F0:0x00)
1720 |((u16Channel_Select & BIT(2))? 0x0F00:0x00)|((u16Channel_Select & BIT(3))? 0xF000:0x00));
1721 u16Ch04_07_mask = (((u16Channel_Select & BIT(4))? 0x000F:0x00)|((u16Channel_Select & BIT(5))? 0x00F0:0x00)
1722 |((u16Channel_Select & BIT(6))? 0x0F00:0x00)|((u16Channel_Select & BIT(7))? 0xF000:0x00));
1723 u16Ch08_11_mask = (((u16Channel_Select & BIT(8))? 0x000F:0x00)|((u16Channel_Select & BIT(9))? 0x00F0:0x00)
1724 |((u16Channel_Select & BIT(10))? 0x0F00:0x00)|((u16Channel_Select & BIT(11))? 0xF000:0x00));
1725 u16Ch12_15_mask = (((u16Channel_Select & BIT(12))? 0x000F:0x00)|((u16Channel_Select & BIT(13))? 0x00F0:0x00)
1726 |((u16Channel_Select & BIT(14))? 0x0F00:0x00)|((u16Channel_Select & BIT(15))? 0xF000:0x00));
1727
1728 if(u16Ch00_03_mask)
1729 {
1730 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L,
1731 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch00_03_mask);
1732 }
1733 else
1734 {
1735 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x00);
1736 }
1737
1738 if(u16Ch04_07_mask)
1739 {
1740 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L,
1741 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch04_07_mask);
1742 }
1743 else
1744 {
1745 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x00);
1746 }
1747
1748 if(u16Ch08_11_mask)
1749 {
1750 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L,
1751 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch08_11_mask);
1752 }
1753 else
1754 {
1755 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x00);
1756 }
1757
1758 if(u16Ch12_15_mask)
1759 {
1760 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L,
1761 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch12_15_mask);
1762 }
1763 else
1764 {
1765 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x00);
1766 }
1767 }
1768
1769 ////////////////////////////////////////////////////////////////////////
1770 // 1.Turn TTL low-power mode function
1771 // 2.Turn internal termination function
1772 // 3.Turn DRIVER BIAS OP function
1773 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_TTL_Resistor_OP(void * pInstance,MS_BOOL bEnble)1774 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL bEnble)
1775 {
1776 MS_BOOL bStatus = FALSE;
1777 if(bEnble)
1778 {
1779 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode
1780 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x001E, 0x001E);
1781
1782 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open)
1783 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F);
1784
1785 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP
1786 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F);
1787 }
1788 else
1789 {
1790 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode
1791 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x0000, 0x001E);
1792
1793 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close)
1794 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F);
1795
1796 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP
1797 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F);
1798 }
1799
1800 bStatus = TRUE;
1801 return bStatus;
1802 }
1803
MHal_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)1804 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam)
1805 {
1806 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1807 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1808 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1809 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1810 pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions = eParam;
1811 }
1812
MHal_PNL_Get_Output_MODE(void * pInstance)1813 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance)
1814 {
1815 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1816 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1817 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1818 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1819 PNL_OUTPUT_MODE eParam = pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions;
1820
1821 return eParam;
1822 }
1823
msReadEfuse(void * pInstance,MS_U8 u8Bank,MS_U32 u32Mask)1824 MS_U32 msReadEfuse(void *pInstance, MS_U8 u8Bank, MS_U32 u32Mask)
1825 {
1826 MS_U32 u32Result = 0;
1827 MS_U8 u8Count = 0;
1828
1829 W2BYTEMSK(0x2050, u8Bank<<2, BMASK(8:2)); /// reg28[8:2]Addr 6~0
1830 W2BYTEMSK(0x2050, BIT(13), BIT(13)); /// Reg28[13] Margin Read
1831 while(R2BYTEMSK(0x2050, BIT(13)) == BIT(13))
1832 {
1833 MsOS_DelayTask(1);
1834 u8Count ++;
1835
1836 if (u8Count >10)
1837 break;
1838 }
1839
1840 u32Result = (R4BYTE(0x2058)& u32Mask); /// reg2C,2D read value
1841 printf("[%s][%d]u32Result=%tx, after mask u32Result=%tx\n", __FUNCTION__, __LINE__,(ptrdiff_t) R4BYTE(0x2058), (ptrdiff_t)u32Result);
1842 return u32Result;
1843
1844 }
1845
msSetVBY1RconValue(void * pInstance)1846 void msSetVBY1RconValue(void *pInstance)
1847 {
1848 MS_U16 u16DefaultICON_Max = 40, u16DefaultICON_Min = 7;
1849 MS_U16 u16DefaultICON = 18;
1850 MS_U32 u32Mask = 0x3F;
1851 MS_BOOL bEfuseMode = FALSE;
1852 MS_U16 u16SwingOffset = 0; // by HW RD request
1853 MS_U16 u16temp = 0;
1854 if (msReadEfuse(pInstance, 0x4E, BIT(6)) == BIT(6))
1855 bEfuseMode = TRUE;
1856
1857
1858 // Disable HW calibration keep mode first, to make SW icon value can write into register.
1859 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
1860
1861 if (bEfuseMode)
1862 {
1863 if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) > u16DefaultICON_Max)
1864 u16temp = u16DefaultICON;
1865 else if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) < u16DefaultICON_Min)
1866 u16temp = u16DefaultICON;
1867 else
1868 u16temp = (MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset;
1869 }
1870 else
1871 {
1872 u16temp = u16DefaultICON;
1873 }
1874
1875 //ch0~ch13 rcon setting
1876 u16temp &= (u16temp&(MS_U16)u32Mask);
1877 printf("[%s][%d]u16temp= %x\n", __FUNCTION__, __LINE__, u16temp);
1878
1879 MOD_A_W2BYTE(REG_MOD_A_BK00_10_L, (u16temp<<8|u16temp));
1880 MOD_A_W2BYTE(REG_MOD_A_BK00_11_L, (u16temp<<8|u16temp));
1881 MOD_A_W2BYTE(REG_MOD_A_BK00_12_L, (u16temp<<8|u16temp));
1882 MOD_A_W2BYTE(REG_MOD_A_BK00_13_L, (u16temp<<8|u16temp));
1883 MOD_A_W2BYTE(REG_MOD_A_BK00_14_L, (u16temp<<8|u16temp));
1884 MOD_A_W2BYTE(REG_MOD_A_BK00_15_L, (u16temp<<8|u16temp));
1885 MOD_A_W2BYTE(REG_MOD_A_BK00_16_L, (u16temp<<8|u16temp));
1886 }
1887
MHal_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)1888 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
1889 {
1890 MS_U16 u16ValidSwing2 = 0;
1891 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1892 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1893 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1894 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1895 if( eLPLL_Type == E_PNL_TYPE_TTL)
1896 {
1897 // select pair output to be TTL
1898 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
1899 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
1900 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
1901 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
1902
1903 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair
1904
1905 // other TTL setting
1906 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x0000); // TTL output enable
1907
1908 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0x0000);
1909 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
1910 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000);
1911
1912 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew
1913
1914 // GPO gating
1915 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating
1916 }
1917 else if(( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)||
1918 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
1919 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE))
1920 {
1921 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2
1922
1923 // rcon
1924 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE)
1925 {
1926 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
1927 MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel);
1928 }
1929 else
1930 {
1931 HAL_MOD_CAL_DBG(printf("Use RconValue\n", __FUNCTION__, __LINE__));
1932 msSetVBY1RconValue(pInstance);
1933 }
1934
1935 // rint
1936 MOD_A_W2BYTE(REG_MOD_A_BK00_32_L, 0x0000);
1937
1938 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003f);
1939
1940 //-------------------------------------
1941 //## pe
1942 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
1943 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
1944 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
1945 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
1946
1947 // VBY1 setting
1948 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0xFFFF);
1949
1950 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8F3F); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
1951 // MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
1952
1953 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0xFFFF);
1954 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
1955 MOD_A_W2BYTE(REG_MOD_A_BK00_48_L, 0xFFFF);
1956 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
1957 MOD_A_W2BYTE(REG_MOD_A_BK00_42_L, 0xFFFF);
1958 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0xFFFF);
1959
1960 switch(eOutputMode)
1961 {
1962 case E_PNL_OUTPUT_NO_OUTPUT:
1963 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
1964 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
1965 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
1966 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
1967 if(1)//( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
1968 {
1969 //-------------------------------------
1970 //## icon (Swing)
1971 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
1972 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
1973
1974 //-------------------------------------
1975 //vby1
1976 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
1977 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
1978 }
1979 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
1980 {
1981 //-------------------------------------
1982 //## icon (Swing)
1983 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
1984 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
1985
1986 //vby1
1987 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f);
1988 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF);
1989 }
1990 break;
1991
1992 case E_PNL_OUTPUT_CLK_ONLY:
1993 case E_PNL_OUTPUT_DATA_ONLY:
1994 case E_PNL_OUTPUT_CLK_DATA:
1995 default:
1996 if(eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
1997 {
1998 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC100);
1999 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x5555); //[15:0]reg_output_conf[15:0]
2000 }
2001 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2002 {
2003 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2004 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0002); //[1]reg_dualmode[0]abswitch
2005 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2006 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x7f7f);
2007 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x5500); //[15:0]reg_output_conf[15:0]
2008 }
2009 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2010 {
2011 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2012 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0000);
2013 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2014 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x0000);
2015 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0500);
2016 }
2017 break;
2018 }
2019 }
2020 //// for osd dedicated output port, 1 port for video and 1 port for osd
2021 else if((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&
2022 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
2023 {
2024 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2025 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path
2026 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
2027 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2028 }
2029 else
2030 {
2031 switch(eOutputMode)
2032 {
2033 case E_PNL_OUTPUT_NO_OUTPUT:
2034 // if MOD_45[5:0] = 0x3F && XC_MOD_EXT_DATA_EN_L = 0x0,
2035 // then if XC_MOD_OUTPUT_CONF_L = 0x0 ---> output TTL as tri-state
2036 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2037 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2038 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2039 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2040
2041 //----------------------------------
2042 // Purpose: Set the output to be the GPO, and let it's level to Low
2043 // 1. External Enable, Pair 0~5
2044 // 2. GPIO Enable, pair 0~5
2045 // 3. GPIO Output data : All low, pair 0~5
2046 // 4. GPIO OEZ: output piar 0~5
2047 //----------------------------------
2048
2049 //1.External Enable, Pair 0~5
2050 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF);
2051 //2.GPIO Enable, pair 0~5
2052 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF);
2053 //3.GPIO Output data : All low, pair 0~5
2054 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF);
2055 //4.GPIO OEZ: output piar 0~5
2056 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF);
2057
2058 //1.External Enable, Pair 6~15
2059 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000);
2060 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2061 //2.GPIO Enable, pair 6~15
2062 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000);
2063 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2064 //3.GPIO Output data : All low, pair 6~15
2065 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000);
2066 MOD_A_W2BYTE(REG_MOD_A_BK00_45_L, 0x0000);
2067 //4.GPIO OEZ: output piar 6~15
2068 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000);
2069 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0x0000);
2070
2071 //1234.External Enable, Pair 16~17
2072 MOD_W2BYTE(REG_MOD_BK00_7E_L, 0xFF00);
2073
2074 //1.External Enable, Pair 18~20, 2.GPIO Enable, pair 18~20
2075 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F);
2076 //3.GPIO Output data : All low, pair 18~20
2077 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00);
2078 //4.GPIO OEZ: output piar 18~20
2079 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00);
2080 break;
2081
2082 case E_PNL_OUTPUT_CLK_ONLY:
2083 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000);
2084 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x4004);
2085 break;
2086
2087 case E_PNL_OUTPUT_DATA_ONLY:
2088 case E_PNL_OUTPUT_CLK_DATA:
2089 default:
2090
2091 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000);
2092 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0x0000);
2093 //1. set GCR_PVDD_2P5=1¡¦b1; MOD PVDD power: 1: 2.5V
2094 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0, BIT(6));
2095 //2. set PD_IB_MOD=1¡¦b0;
2096 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(0));
2097 // save ch6 init value
2098 u16ValidSwing2 = (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0B_L, 0x3F00)>>8);
2099 //3. set Desired Pairs: GCR_ICON[5:0]=6h3f (current all open);
2100 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, 0x3F));
2101 //4. set Desired Pairs: GCR_PE_ADJ[2:0]=3h7 (pre-emphasis current all open )
2102 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x07);
2103 //5. Enable low-power modeinternal termination Open, Enable OP
2104 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 1);
2105
2106 MsOS_DelayTask(1);
2107
2108 //6. Enable low-power modeinternal termination Open, Enable OP
2109 MHal_Output_LVDS_Pair_Setting(pInstance,
2110 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
2111 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
2112 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
2113 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2114 MHal_Shift_LVDS_Pair(pInstance, pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift);
2115
2116 //7. set Desired Pairs: GCR_PE_ADJ[2:0]=3¡¦h0 (pre-emphasis current all Close)
2117 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x00);
2118 //8. set Desired Pairs: GCR_ICON[5:0] (current all init);
2119 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, u16ValidSwing2));
2120 //9. Disable low-power modeinternal termination Close, Disable OP
2121 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 0);
2122
2123 // other TTL setting
2124 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/ PANEL_miniLVDS/ PANEL_RSDS
2125
2126 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000);
2127 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2128 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F);
2129
2130 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew
2131
2132 // GPO gating
2133 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating
2134
2135 break;
2136 }
2137 }
2138
2139 // MHal_PNL_Bringup(pInstance);
2140 }
2141
Mhal_PNL_Flock_LPLLSet(void * pInstance,MS_U64 ldHz)2142 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz)
2143 {
2144 UNUSED(ldHz);
2145 }
2146
MHal_PNL_MISC_Control(void * pInstance,MS_U32 u32PNL_MISC)2147 void MHal_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC)
2148 {
2149 if(u32PNL_MISC & E_DRVPNL_MISC_MFC_ENABLE)
2150 {
2151 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair
2152 }
2153 }
2154
MHal_PNL_Init_XC_Clk(void * pInstance,PNL_InitData * pstPanelInitData)2155 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData)
2156 {
2157 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2158 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2159 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2160 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2161
2162 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2163
2164 // setup output dot clock
2165
2166 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock
2167 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert
2168 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock
2169 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft
2170
2171 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod
2172 W2BYTE(L_CLKGEN1(0x31), 0x0000); //[11:8]ckg_odclk_frc
2173
2174 if((pstPanelInitData->eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2175 (pstPanelInitData->eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
2176 {
2177
2178 W2BYTE(REG_CLKGEN0_57_L,0x0008); //[3:0]ckg_fifo
2179 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod
2180 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2181 W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc
2182 }
2183 else
2184 {
2185
2186 W2BYTE(REG_CLKGEN0_57_L,0x0000); //[3:0]ckg_fifo
2187 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
2188 {
2189 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod
2190 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+
2191 }
2192 else
2193 {
2194 W2BYTE(L_CLKGEN0(0x63),0x0000); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod
2195 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2196 }
2197 }
2198 }
2199
MHal_PNL_Init_MOD(void * pInstance,PNL_InitData * pstPanelInitData)2200 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData)
2201 {
2202 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2203 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2204 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2205 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2206
2207 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2208
2209 //------------------------------------------------------------------------
2210
2211 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL0 = %x\n", pstPanelInitData->u16MOD_CTRL0);
2212 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL9 = %x\n", pstPanelInitData->u16MOD_CTRL9);
2213 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRLA = %x\n", pstPanelInitData->u16MOD_CTRLA);
2214 PNL_DBG(PNL_DBGLEVEL_INIT, "u8MOD_CTRLB = %x\n", pstPanelInitData->u8MOD_CTRLB);
2215
2216 //-------------------------------------------------------------------------
2217 // Set MOD registers
2218 //-------------------------------------------------------------------------
2219
2220 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK);
2221
2222 // GPIO is controlled in drvPadConf.c
2223 // MDrv_Write2Byte(L_BK_MOD(0x46), 0x0000); //EXT GPO disable
2224 // MDrv_Write2Byte(L_BK_MOD(0x47), 0x0000); //EXT GPO disable
2225 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2226 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
2227 {
2228 ///u16MOD_CTRL9 [6] : 62[9]reg_vby1_pair_swap
2229 ///u16MOD_CTRL9 [12:11] : 62[5:4]reg_vby1_pair_mirror
2230 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xAC40, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2231
2232 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9));
2233 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|BIT(4));
2234
2235 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2236 {
2237 if(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
2238 {
2239 // 2 divison just be supported in monet vby1 8 lane
2240 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2241 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode
2242
2243 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value
2244 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize
2245 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len
2246 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage
2247 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask
2248 }
2249 else
2250 {
2251 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode
2252 }
2253 }
2254 else
2255 {
2256 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2257 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);
2258 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask
2259 }
2260
2261 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
2262 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1
2263 else
2264 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1
2265
2266
2267 ///u16MOD_CTRL9 [7] : 63[13]reg_vby1_pair_swap_osd
2268 ///u16MOD_CTRL9 [14:13] : 63[11:10]reg_vby1_pair_mirror2
2269 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13));
2270 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|BIT(10));
2271
2272 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
2273 {
2274 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1
2275
2276 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
2277 {
2278 // 2 Divisoin
2279 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2
2280 }
2281 else
2282 {
2283 // 1 Division
2284 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2
2285 }
2286 }
2287 else //if ///E_PNL_LPLL_VBY1_10BIT_4LANE, E_PNL_LPLL_VBY1_10BIT_2LANE
2288 {
2289 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(12)); // [12] enable 8ch vx1 mode : 0
2290 }
2291
2292 MHal_Output_Channel_Order(pInstance,
2293 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2294 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2295 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2296 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2297 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2298
2299
2300 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2301 {
2302 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2303 }
2304 else
2305 {
2306 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2307 }
2308
2309 ////per RD's suggestion ---Start
2310 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, 0x3FFF, 0x3FFF); //reg_gcr_pe_en_ch
2311 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0x3FFF); //reg_gcr_en_rint_ch
2312 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x3FFF, 0x3FFF); //reg_gcr_test_ch
2313
2314 /// reg_gcr_pe_adj ch0~ch13
2315 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x2222);
2316 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x2222);
2317 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x2222);
2318 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x2222);
2319
2320 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(0)|BIT(3), BIT(0)|BIT(3)); // [0] reg_vby1_8v4o_mode, [3]reg_vby1_ext_ptr_en
2321 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(15), BIT(15));
2322
2323 //The threshold value be set too strict ( ori: MOD_5C =0x0 )
2324 //And this reg should be set before enable serializer function
2325 //[15]reg_sw_rptr_fix_en: pointer fix by sw mode enable
2326 //[14:12]reg_sw_wptr_check: sw mode to decision write point check point
2327 //[10:8]reg_sw_rptr_fix_ini: sw mode to decision read point initial value
2328 //[6:4]reg_sw_rptr_fix_hi_th: sw mode to decision read pointer hi boundary
2329 //[2:0]reg_sw_rptr_fix_lo_th: sw mode to decision read pointer low boundary
2330 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF);
2331 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF);
2332
2333 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
2334 //[1]enable serializer auto fix read/write point mis-balance
2335 //[2]enable osd serializer auto fix read/write point mis-balance
2336 //[7]for OSD, switch chanel 8~13 as OSD path
2337 }
2338 else
2339 {
2340 MOD_W2BYTE(REG_MOD_BK00_49_L, pstPanelInitData->u16MOD_CTRL9); //{L_BK_MOD(0x49), 0x00}, // [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit, bit shift
2341 MHal_Output_Channel_Order(pInstance,
2342 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2343 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2344 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2345 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2346 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2347 }
2348
2349 MOD_W2BYTE(REG_MOD_BK00_4A_L, pstPanelInitData->u16MOD_CTRLA);
2350 MOD_W2BYTE(REG_MOD_BK00_4B_L, pstPanelInitData->u8MOD_CTRLB); //[1:0]ti_bitmode 10:8bit 11:6bit 0x:10bit
2351
2352 //dual port lvds _start_//
2353 // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
2354 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck // original is MDrv_WriteByteMask(L_BK_MOD(0x77), 0x0F, BITMASK(7:2));
2355 //dual port lvds _end_//
2356
2357 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, (_u8PnlDiffSwingLevel << 1), 0xFE); //differential output swing level
2358 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2359 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
2360 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000, 0xF000); //bank selection for skew clock
2361
2362 //if(!MHal_PNL_MOD_Control_Out_Swing(_u8PnlDiffSwingLevel))
2363 // printf(">>Swing Level setting error!!\n");
2364 if(pstPanelInitData->eLPLL_Type != E_PNL_TYPE_MINILVDS)
2365 {
2366 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07);
2367 }
2368
2369 //// Patch for Vx1 and it should be control by panel ini
2370 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2371 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
2372 {
2373 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, 0x0FFF, 0x3FFF);
2374 }
2375 else
2376 {
2377 MOD_A_W2BYTE(REG_MOD_A_BK00_31_L, pstPanelInitData->u16LVDSTxSwapValue);
2378 }
2379
2380
2381 // TODO: move from MDrv_Scaler_Init(), need to double check!
2382 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0));
2383
2384
2385 //--------------------------------------------------------------
2386 //Depend On Bitmode to set Dither
2387 //--------------------------------------------------------------
2388
2389
2390 // always enable noise dither and disable TAILCUT
2391 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, ((pstPanelInitData->u8PanelNoiseDith ? XC_PAFRC_DITH_NOISEDITH_EN : (1 - XC_PAFRC_DITH_NOISEDITH_EN)) <<3) , BIT(3));
2392 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, XC_PAFRC_DITH_TAILCUT_DISABLE, BIT(4));
2393
2394 switch(pstPanelInitData->u8MOD_CTRLB & 0x03)//[1:0]ti_bitmode b'10:8bit 11:6bit 0x:10bit
2395 {
2396 case HAL_TI_6BIT_MODE:
2397 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
2398 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(2), BIT(2));
2399 break;
2400
2401 case HAL_TI_8BIT_MODE:
2402 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
2403 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
2404 break;
2405
2406 case HAL_TI_10BIT_MODE:
2407 default:
2408 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(0));
2409 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
2410 break;
2411 }
2412
2413
2414 //-----depend on bitmode to set Dither------------------------------
2415 MHal_PNL_SetOutputType(pInstance, pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type); // TTL to Ursa
2416 //MHal_PNL_Bringup(pInstance);
2417
2418 MHal_PNL_MISC_Control(pInstance, pstPanelInitData->u32PNL_MISC);
2419
2420 PNL_DBG(PNL_DBGLEVEL_INIT, "OutputType = %x, eLPLL_Type = %x\n", pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type);
2421 PNL_DBG(PNL_DBGLEVEL_INIT, "u32PNL_MISC = %tx\n", (ptrdiff_t)pstPanelInitData->u32PNL_MISC);
2422
2423 }
2424
MHal_PNL_DumpMODReg(void * pInstance,MS_U32 u32Addr,MS_U16 u16Value,MS_BOOL bHiByte,MS_U16 u16Mask)2425 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask)
2426 {
2427 if (bHiByte)
2428 {
2429 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
2430 }
2431 else
2432 {
2433 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask);
2434 }
2435 }
2436
MHal_MOD_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)2437 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
2438 {
2439 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2440 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2441 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2442 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2443 // Setup the default swing level
2444 pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel = pstModCaliInitData->u16ExpectSwingLevel; //mv
2445 #if 0
2446 // Pair setting
2447 // =========
2448 // Select calibration source pair, 00: ch2, 01: ch6, 10:ch8, 11:ch12
2449 //MOD_7D_L[3:2]
2450 // =========
2451 //in msModCurrentCalibration, it will transfer to the real data
2452
2453 switch(pstModCaliInitData->u8ModCaliPairSel)
2454 {
2455 default:
2456 case 0:
2457 //ch 2
2458 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x00; // ch2
2459 break;
2460 case 1:
2461 //ch 6
2462 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x01; // ch6, calibration initialized value
2463 break;
2464 case 2:
2465 //ch 8
2466 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x02;
2467 break;
2468 case 3:
2469 //ch 12
2470 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x03;
2471 break;
2472 }
2473 #endif
2474 // Target setting
2475 // =========
2476 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
2477 // =========
2478 //in msModCurrentCalibration, it will transfer to the real data
2479 switch(pstModCaliInitData->u8ModCaliTarget)
2480 {
2481 default:
2482 case 0:
2483 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 0;
2484 break;
2485 case 1:
2486 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 1;
2487 break;
2488 case 2:
2489 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 2;
2490 break;
2491 case 3:
2492 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 3;
2493 break;
2494 }
2495 // Offset setting, for fine tune
2496 //_usMOD_CALI_OFFSET = pstModCaliInitData->s8ModCaliOffset;
2497 // _u8MOD_CALI_VALUE is a real value; the _u8MOD_CALI_VALUE is an idea value
2498 // Target value should be the same with _u8MOD_CALI_VALUE to be a default value
2499 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE= pstModCaliInitData->u8ModCaliTarget;
2500 // PVDD setting
2501 pPNLResourcePrivate->sthalPNL._bPVDD_2V5 = pstModCaliInitData->bPVDD_2V5;
2502
2503 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2504 PNL_DBG(PNL_DBGLEVEL_INIT, "u16ExpectSwingLevel = %u\n", pstModCaliInitData->u16ExpectSwingLevel);
2505 PNL_DBG(PNL_DBGLEVEL_INIT, "u8ModCaliTarget = %x\n", pstModCaliInitData->u8ModCaliTarget);
2506 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_TARGET = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET);
2507 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_VALUE = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE);
2508 PNL_DBG(PNL_DBGLEVEL_INIT, "bPVDD_2V5 = %x\n", pstModCaliInitData->bPVDD_2V5);
2509
2510 }
2511
MHal_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)2512 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type)
2513 {
2514 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2515 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2516 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2517 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2518 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
2519 {
2520 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift = LVDS_DUAL_OUTPUT_SPECIAL;
2521 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = 1;
2522 }
2523 else
2524 {
2525 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = Type;
2526 }
2527 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2528 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_LVDS_Pair_Type = %u\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
2529
2530 }
2531
msModCalDDAOUT(void)2532 MS_BOOL msModCalDDAOUT(void)
2533 {
2534 // W2BYTEMSK(BK_MOD(0x7D), ENABLE, 8:8);
2535 // MsOS_DelayTask(10); //10ms
2536 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_A_BK00_74_L, BIT(8))) >> 8);
2537 }
2538
msModCurrentCalibration(void * pInstance)2539 MS_U8 msModCurrentCalibration(void *pInstance)
2540 {
2541 #if MOD_CAL_TIMER
2542 MS_U32 delay_start_time;
2543 delay_start_time=MsOS_GetSystemTime();
2544 #endif
2545
2546 #if (!ENABLE_Auto_ModCurrentCalibration)
2547 return 0x60;
2548 #else
2549 MS_U8 u8cur_ibcal=0;
2550 MS_U16 u16reg_32da = 0, u16reg_32dc = 0;
2551 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2552 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2553 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2554 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2555 u16reg_32da = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2556 u16reg_32dc = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2557
2558 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s][%d]\n", __FUNCTION__, __LINE__);
2559
2560 // (1) Set keep mode to auto write calibration result into register.
2561 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15));
2562
2563 // (2) Set calibration step waiting time
2564 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0x0080); // (about 5us)
2565 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, 0x00FF);
2566
2567 // (3) Set calibration toggle time
2568 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00);
2569
2570 // (4) Select calibration level (LVDS is 250mV)
2571 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(1)|BIT(0)); // Select calibration target voltage, 00: 250mV, 01:350mV, 10: 300mV, 11: 200mV
2572
2573 // (5) Enable Calibration mode
2574 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function
2575
2576 // (6) Store output configuration value and Enable each pair test mode
2577 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0xFFFF);
2578 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0FFF);
2579
2580 MS_U8 u8CheckTimes = 0;
2581 while(1)
2582 {
2583 // (7) Enable Hardware calibration
2584 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, BIT(15), BIT(15));
2585
2586 // (8) Wait 2ms
2587 MsOS_DelayTask(2);
2588
2589 // (10) Disable Hardware calibration
2590 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, 0x00, BIT(15));
2591
2592 // (9)Check Finish and Fail flag bit
2593 //BK1032, 0x3D[14], Finish flag=1
2594 //BK1032, 0x3D[13], Fail flag=0
2595 if (MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000) == 0x4000)
2596 {
2597 //printf("\033[0;31m [%s][%d] cal ok, break \033[0m\n", __FUNCTION__, __LINE__);
2598 break;
2599 }
2600 else
2601 {
2602 u8CheckTimes ++;
2603 //printf("\033[0;31m [%s][%d] cal ng, u8CheckTimes: %d \033[0m\n", __FUNCTION__, __LINE__, u8CheckTimes);
2604 }
2605
2606 if (u8CheckTimes > 3)
2607 {
2608 // (13) If 3 times all fail, set all pair to nominal value by disable keep mode
2609 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15));
2610 //printf("\033[0;31m [%s][%d] If 3 times all fail, set all pair to nominal value by disable keep mode \033[0m\n", __FUNCTION__, __LINE__);
2611 break;
2612 }
2613 }
2614
2615 if (u8CheckTimes <=3)
2616 {
2617 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration ok \n");
2618 }
2619 else
2620 {
2621 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration fail: 0x%x \n", MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000));
2622 }
2623
2624 // Wait 2ms to make sure HW auto write calibration result into register
2625 MsOS_DelayTask(2);
2626
2627 // (14) Restore each pair output configuration
2628 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16reg_32da);
2629 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16reg_32dc);
2630
2631 // (15) Disable calibration mode
2632 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Disable calibration function
2633
2634 // With HW calibration mode, HW would cal for each channel, and each channel would get different value
2635 // Return channel 2 vaule
2636 u8cur_ibcal = MOD_A_R2BYTEMSK(REG_MOD_A_BK00_09_L, 0x007F); // return ch2 calibration result
2637
2638 #if MOD_CAL_TIMER
2639 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s] takes %ld ms\n", __FUNCTION__, (MsOS_GetSystemTime()-delay_start_time));
2640 #endif
2641 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n Calibration result= %x\n", u8cur_ibcal);
2642
2643 return (u8cur_ibcal&0x7F);//MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0D_L, 0x003F);
2644 #endif
2645 }
2646
MHal_PNL_MOD_Calibration(void * pInstance)2647 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance)
2648 {
2649 MS_U8 u8Cab;
2650 MS_U8 u8BackUSBPwrStatus;
2651 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2652 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2653 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2654 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2655
2656 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
2657
2658 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
2659
2660 u8Cab = msModCurrentCalibration(pInstance);
2661
2662 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
2663
2664 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type !=E_PNL_TYPE_MINILVDS)
2665 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07);
2666
2667 return E_PNL_OK;
2668
2669 }
2670
MHal_PNL_PowerDownLPLL(void * pInstance,MS_BOOL bEnable)2671 static void MHal_PNL_PowerDownLPLL(void *pInstance, MS_BOOL bEnable)
2672 {
2673 if(bEnable)
2674 {
2675 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5));
2676 }
2677 else
2678 {
2679 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5));
2680 }
2681 }
2682
MHal_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)2683 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn)
2684 {
2685 MS_U8 u8Cab;
2686 MS_U8 u8BackUSBPwrStatus;
2687 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2688 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2689 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2690 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2691
2692 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "[%s][%d]\n", __FUNCTION__, __LINE__);
2693
2694 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u32PNL_MISC = %tx\n", (ptrdiff_t)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC);
2695 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "bPanelOn = %x\n", bPanelOn);
2696 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "eLPLL_Type = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type);
2697 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "_u8MOD_LVDS_Pair_Type = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
2698 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
2699 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
2700 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2701
2702 MS_U16 u16PortA = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2703 MS_U16 u16PortB = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2704
2705 if(u16PortA!=0)
2706 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2707 if(u16PortB!=0)
2708 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2709
2710 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "==========================\n\n");
2711 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
2712 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
2713 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2714
2715
2716 if(bPanelOn)
2717 {
2718 // The order is PanelVCC -> delay pnlGetOnTiming1() -> VOP -> MOD
2719 // VOP
2720 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x4000, HBMASK);
2721
2722 // For Napoli compatible
2723 // need to wait 1ms to wait LDO stable before MOD power on
2724 MsOS_DelayTask(1);
2725
2726 // turn on LPLL
2727 MHal_PNL_PowerDownLPLL(pInstance, FALSE);
2728
2729 // mod power on
2730 MHal_MOD_PowerOn(pInstance
2731 , ENABLE
2732 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
2733 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
2734 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
2735 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
2736 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2737
2738 if(bCalEn)
2739 {
2740
2741 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
2742
2743 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
2744
2745 u8Cab = msModCurrentCalibration(pInstance);
2746
2747 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
2748
2749 }
2750 else
2751 {
2752 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type>=E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2753 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type<=E_PNL_LPLL_VBY1_8BIT_8LANE) &&
2754 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE) == FALSE))
2755 {
2756 HAL_MOD_CAL_DBG(printf("Use RCON value \n", __FUNCTION__, __LINE__));
2757 msSetVBY1RconValue(pInstance);
2758 }
2759 else
2760 {
2761 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
2762
2763 if(!MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel))
2764 printf(">>Swing Level setting error!!\n");
2765 }
2766 }
2767
2768 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
2769 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, ENABLE);
2770 }
2771 else
2772 {
2773 // The order is LPLL -> MOD -> VOP -> delay for MOD power off -> turn off VCC
2774
2775 // LPLL
2776 // MHal_PNL_PowerDownLPLL(TRUE); //Remove to keep op vsync if panel off
2777
2778 MHal_MOD_PowerOn(pInstance
2779 , DISABLE
2780 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
2781 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
2782 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
2783 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
2784 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2785 // VOP
2786 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS ||
2787 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_I ||
2788 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_P)//(bIsLVDS)
2789 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0xFF, LBMASK);
2790 else
2791 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x00, 0xFF);
2792 }
2793
2794 return E_PNL_OK;
2795 }
2796
MHal_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)2797 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
2798 {
2799 if (bEnable)
2800 {
2801 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF);
2802 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF);
2803 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF);
2804 MsOS_DelayTask(10);
2805 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15));
2806 }
2807 else
2808 {
2809 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15));
2810 }
2811
2812 }
2813
MHal_PNL_Switch_LPLL_SubBank(void * pInstance,MS_U16 u16Bank)2814 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank)
2815 {
2816 UNUSED(u16Bank);
2817 }
2818
MHal_PNL_Switch_TCON_SubBank(void * pInstance,MS_U16 u16Bank)2819 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank)
2820 {
2821 W2BYTEMSK(L_BK_TCON(0x00), u16Bank&0xff, 0xFF);
2822 }
2823
MHal_PNL_Read_TCON_SubBank(void * pInstance)2824 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance)
2825 {
2826 return (MS_U16)R2BYTEMSK(L_BK_TCON(0x00),0xFF);
2827 }
2828
MHal_PNL_Is_VBY1_Locked(void * pInstance)2829 MS_BOOL MHal_PNL_Is_VBY1_Locked(void *pInstance)
2830 {
2831 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0300) == 0x00)
2832 {
2833 return TRUE;
2834 }
2835 else
2836 {
2837 return FALSE;
2838 }
2839 }
2840
MHal_PNL_Is_VBY1_LockN_Locked(void * pInstance)2841 MS_BOOL MHal_PNL_Is_VBY1_LockN_Locked(void *pInstance)
2842 {
2843 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0100) == 0x00)
2844 {
2845 return TRUE;
2846 }
2847 else
2848 {
2849 return FALSE;
2850 }
2851 }
2852
MHal_PNL_VBY1_Handshake(void * pInstance)2853 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance)
2854 {
2855 MS_BOOL bIsLock = FALSE;
2856
2857 if (MHal_PNL_Is_VBY1_Locked(pInstance) == FALSE)
2858 {
2859 MS_U16 u16CheckTimes = 0;
2860 //MS_U16 u16DeboundTimes = 0;
2861
2862 // need to toggle vby1 packer process start first
2863 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11));
2864 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11));
2865
2866 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value
2867 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by
2868 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition
2869 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
2870 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance
2871
2872 while(u16CheckTimes < 10)
2873 {
2874 #if 0
2875 u16DeboundTimes = 2;
2876 while ((!MHal_PNL_Is_VBY1_LockN_Locked()) && (u16DeboundTimes --))
2877 {
2878 MsOS_DelayTask(1); // can't remove
2879 }
2880 #endif
2881 if(MHal_PNL_Is_VBY1_LockN_Locked(pInstance))
2882 {
2883 //-------------------------------------------------------------------
2884 // step1. Toggle clock when training
2885 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
2886 //--------------------------------------------------------------------
2887 bIsLock = TRUE;
2888 // pass 2 times debound to make sure VBY1 is locked
2889 break;
2890 }
2891
2892 u16CheckTimes++;
2893 MsOS_DelayTaskUs(40);
2894 }
2895
2896 if(bIsLock)
2897 {
2898 // step3. Disable HW check when lock done, Enable when loss lock
2899 //MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
2900
2901 /// Add the delay to increase time to send
2902 //MDrv_TIMER_Delayms(10);
2903 }
2904 }
2905 else
2906 {
2907 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE)
2908 {
2909 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
2910 }
2911 bIsLock = TRUE;
2912 }
2913
2914 return bIsLock;
2915 }
2916
MHal_PNL_Is_VBY1_OC_Locked(void * pInstance)2917 MS_BOOL MHal_PNL_Is_VBY1_OC_Locked(void *pInstance)
2918 {
2919 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0C00) == 0x00) // MOD_BK00_56_L[11:10] for OSD
2920 {
2921 return TRUE;
2922 }
2923 else
2924 {
2925 return FALSE;
2926 }
2927 }
2928
MHal_PNL_Is_VBY1_OC_LockN_Locked(void * pInstance)2929 MS_BOOL MHal_PNL_Is_VBY1_OC_LockN_Locked(void *pInstance)
2930 {
2931 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0400) == 0x00) // MOD_BK00_56_L[11:10] for OSD
2932 {
2933 return TRUE;
2934 }
2935 else
2936 {
2937 return FALSE;
2938 }
2939 }
2940
MHal_PNL_VBY1_OC_Handshake(void * pInstance)2941 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance)
2942 {
2943 MS_BOOL bIsLock = FALSE;
2944
2945 if (MHal_PNL_Is_VBY1_OC_Locked(pInstance) == FALSE)
2946 {
2947 MS_U16 u16CheckTimes = 0;
2948 // MS_U16 u16DeboundTimes = 0;
2949
2950 // need to toggle vby1 packer process start first
2951 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11));
2952 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11));
2953
2954
2955 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value
2956 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by
2957 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition
2958 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
2959 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance
2960
2961 while(u16CheckTimes < 10)
2962 {
2963 #if 0
2964 u16DeboundTimes = 2;
2965 while ((!MHal_PNL_Is_VBY1_OC_LockN_Locked()) && (u16DeboundTimes --))
2966 {
2967 MsOS_DelayTask(1);
2968 }
2969 #endif
2970 if(MHal_PNL_Is_VBY1_OC_LockN_Locked(pInstance))
2971 {
2972 //-------------------------------------------------------------------
2973 // step1. Toggle clock when training
2974
2975 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
2976 bIsLock = TRUE;
2977 // pass 2 times debound to make sure VBY1 is locked
2978 break;
2979 }
2980
2981 u16CheckTimes++;
2982 MsOS_DelayTaskUs(40);
2983 }
2984
2985 if(bIsLock)
2986 {
2987 // step3. Disable HW check when lock done, Enable when loss lock
2988 // MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
2989 }
2990 }
2991 else
2992 {
2993 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE)
2994 {
2995 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
2996 }
2997 bIsLock = TRUE;
2998 }
2999
3000 return bIsLock;
3001 }
3002
MHal_PNL_IsYUVOutput(void * pInstance)3003 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance)
3004 {
3005 return FALSE;
3006 }
3007
MHal_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)3008 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
3009 {
3010 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3011 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3012
3013 if (bEnable == TRUE)
3014 {
3015 //interlace output vtotal modify
3016 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9), BIT(9));
3017
3018 // two different interlace information through channel A reserved bit
3019 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7));
3020 // two different interlace information through channel B reserved bit
3021 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11));
3022 }
3023 else
3024 {
3025 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L , 0, BIT(9));
3026 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7));
3027 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11));
3028 }
3029
3030 return TRUE;
3031 }
3032
MHal_PNL_GetOutputInterlaceTiming(void * pInstance)3033 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance)
3034 {
3035 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3036 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3037
3038 MS_BOOL bIsInterlaceOutput = FALSE;
3039 //interlace output vtotal modify
3040 if (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9)) == BIT(9))
3041 {
3042 if ((MOD_R2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7)) == (BIT(4) | BIT(7)))
3043 || (MOD_R2BYTEMSK(REG_MOD_BK00_42_L, BIT(10) | BIT(11)) == (BIT(10)|BIT(11))))
3044 {
3045 bIsInterlaceOutput = TRUE;
3046 }
3047 }
3048 else
3049 {
3050 bIsInterlaceOutput = FALSE;
3051 }
3052 return bIsInterlaceOutput;
3053 }
3054
3055 ////Ext LPLL setting
_MHal_PNL_Init_ExtLPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)3056 static void _MHal_PNL_Init_ExtLPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
3057 {
3058 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3059
3060 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_OSD);
3061
3062 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3063 {
3064 printf("Not Supported LPLL Type, skip LPLL Init\n");
3065 return;
3066 }
3067
3068 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_OSD);
3069 }
3070
_MHal_PNL_Get_ExtLPLL_LoopDIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3071 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopDIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3072 {
3073 MS_U16 u16loop_div = 0;
3074 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3075 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3076
3077 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3078 {
3079 u16loop_div = 0 ;
3080 }
3081 else
3082 {
3083 u16loop_div = u16EXT_LoopDiv[u8SupportedLPLLLIndex];
3084 }
3085
3086 u16loop_div *= 2;
3087 return u16loop_div;
3088 }
3089
_MHal_PNL_Get_ExtLPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3090 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3091 {
3092 MS_U16 u16loop_gain = 0;
3093 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3094 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3095
3096 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3097 {
3098 u16loop_gain = 0 ;
3099 }
3100 else
3101 {
3102 u16loop_gain = u16EXT_LoopGain[u8SupportedLPLLLIndex];
3103 }
3104 return u16loop_gain;
3105 }
3106
3107
3108 // Output Dclk
MHal_PNL_CalExtLPLLSETbyDClk(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U64 ldHz)3109 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz)
3110 {
3111
3112 MS_U64 u64LdPllSet = 0;
3113 MS_U64 u64DclkFactor = 0;
3114 MS_U32 u32Div = 0;
3115 // loop div and loop gain use default parameters to avoid dclk floating out of range and getting wrong value
3116 MS_U32 u32Factor = 10;
3117
3118 _MHal_PNL_Init_ExtLPLL(pInstance, u8LPLL_Type, u8LPLL_Mode, ldHz);
3119
3120 //the first " *2 " is from the dual mode
3121 u32Div=(MS_U32)(_MHal_PNL_Get_ExtLPLL_LoopDIV(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3122 u64DclkFactor=((MS_U64)LVDS_MPLL_CLOCK_MHZ * (MS_U64)524288 * (MS_U64)_MHal_PNL_Get_ExtLPLL_LoopGain(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3123 u64LdPllSet = (u64DclkFactor * 1000000 * u32Factor *2) + ((ldHz * u32Div) >> 1);
3124 do_div(u64LdPllSet, ldHz);
3125 do_div(u64LdPllSet, u32Div);
3126
3127 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet);
3128 //printf("MHal_PNL_CalExtLPLLSETbyDClk u32KHz = %u, u32LpllSet = %x\n", ldHz, (MS_U32)u64LdPllSet);
3129
3130 }
3131
MHal_PNL_SetOSDCOutputType(void * pInstance,PNL_TYPE eLPLL_Type,E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)3132 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)
3133 {
3134 // VBy1 co-registers
3135 if ((eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)
3136 && (eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
3137 {
3138 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1008); //[3]enable osd lvds channel
3139 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
3140
3141 //-------------------------------------
3142 //## pe
3143 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
3144 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
3145 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
3146 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
3147
3148 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
3149
3150 }
3151
3152 if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
3153 {
3154 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14),BIT(14)|BIT(15)); //[15]enskew_path2[14]enclk_path2[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3155 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0055); //[7:0]reg_output_conf[27:16]
3156 W2BYTE(REG_CLKGEN0_53_L,0x00CC); //[13:8] clk_bt656 -> clk_lpll_buf
3157 W2BYTE(REG_CLKGEN0_63_L,0x0410); //[11:8] clk_tx_mod_osd, [4:0] osd2mod
3158 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
3159
3160 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1000); //[12]sw_rst, [3]enable osd lvds channel
3161 MOD_A_W2BYTE(REG_MOD_A_BK00_38_L, 0xc01f);
3162 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); //[3:0] reg_ckg_tx_mod
3163 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); //reg_ckg_dot
3164
3165 MOD_W2BYTE(REG_MOD_BK00_71_L, 0xffff);
3166 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
3167 //[1]enable serializer auto fix read/write point mis-balance
3168 //[2]enable osd serializer auto fix read/write point mis-balance
3169 //[7]for OSD, switch chanel 8~13 as OSD path
3170 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000);
3171 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330);
3172 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd320);
3173 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f);
3174 //-------------------------------------
3175 //## icon (Swing)
3176 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3177 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x7f7f);
3178 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3179
3180 // vby1 osd 4 lane
3181 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa260); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap
3182 }
3183 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
3184 {
3185 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14) ,BIT(14)|BIT(15));
3186 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0005);
3187
3188 //-------------------------------------
3189 //## icon (Swing)
3190 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3191 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x0000);
3192 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3193
3194 //vby1 osd 2 lane
3195 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa240); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap[5]vby1_osd_4ch
3196 }
3197
3198 // Control VBY1 output format and bit orders
3199 switch(eOC_OutputFormat)
3200 {
3201 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB1:
3202 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3203 break;
3204
3205 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB2:
3206 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1));
3207 break;
3208
3209 default:
3210 printf("OSDC output format uses default value\n");
3211 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3212 break;
3213 }
3214
3215
3216 }
3217
MHal_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)3218 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
3219 {
3220 MS_U16 u16Span;
3221 MS_U16 u16Step;
3222 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
3223
3224 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
3225 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
3226 // Set SPAN
3227 if(u16Fmodulation < 200 || u16Fmodulation > 400)
3228 u16Fmodulation = 300;
3229 u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) / ((MS_U32)u32PLL_SET) ) ;
3230
3231 // Set STEP
3232 if(u16Rdeviation > 300)
3233 u16Rdeviation = 300;
3234 u16Step = ((MS_U32)u32PLL_SET*u16Rdeviation) / ((MS_U32)u16Span*10000);
3235
3236 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP
3237 W2BYTE(L_BK_LPLL(0x4F), u16Span & 0x3FFF);// LPLL_SPAN
3238 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
3239
3240
3241 return TRUE;
3242 }
3243
MHal_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)3244 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
3245 {
3246 //printf("bEnable = %d\n", bEnable);
3247 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
3248 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
3249 }
3250
MHal_PNL_Set_T3D_Setting(void * pInstance)3251 void MHal_PNL_Set_T3D_Setting(void *pInstance)
3252 {
3253 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3254 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3255 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3256 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3257
3258 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_55_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x1FFF);//pixel width
3259 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_66_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
3260 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_51_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x1FFF);//reg_ln_width
3261 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_52_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
3262 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_61_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Width, 0x3FFF);//reg_ln_width
3263 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_62_L, pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16Height, 0x1FFF);//reg_col_height
3264
3265 //per designer, should always enable t3d, since it will affect osd/video's pipeline
3266 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_61_L, BIT(0), BIT(0));//Enable Depth Render, for osd pipe line adjustment
3267 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_08_L, BIT(4), BIT(4));//mtv bypass mode
3268 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_57_L,(BIT(0)|BIT(1)),(BIT(0)|BIT(1)));//T3D fix subde enable, fix for T3D/PIP conflict issue (bit 0) Bug Fix miu eco (bit 1)
3269
3270 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
3271 }
3272
MHal_PNL_Set_Device_Bank_Offset(void * pInstance)3273 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance)
3274 {
3275 UNUSED(pInstance);
3276 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM);
3277 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg bank offset
3278 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg bank offset
3279 }
3280
MHal_PNL_Init(void * pInstance)3281 void MHal_PNL_Init(void *pInstance)
3282 {
3283 // Do nothing
3284 UNUSED(pInstance);
3285 }
3286
MHal_PNL_Bringup(void * pInstance)3287 void MHal_PNL_Bringup(void *pInstance)
3288 {
3289 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3290 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3291 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3292 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3293
3294 ///patch for bring up
3295 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
3296 {
3297 }
3298 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
3299 {
3300 //==========================//
3301 //= Setting LPLL =//
3302 //==========================//
3303 //==========================//
3304 //= ICON RCON PE =//
3305 //==========================//
3306 //W2BYTE(0x111e10, 0xffff);
3307 //W2BYTE(0x111e12, 0xffff);
3308 //W2BYTE(0x111e14, 0xffff);
3309 //W2BYTE(0x111e16, 0xffff);
3310 //W2BYTE(0x111e18, 0xffff);
3311 //W2BYTE(0x111e1a, 0xffff);
3312 //W2BYTE(0x111e1c, 0xffff);
3313
3314 //==========================//
3315 //= Setting MOD =//
3316 //==========================//
3317 //W2BYTE(0x103210, 0x5410);
3318 //W2BYTE(0x103212, 0x7632);
3319 W2BYTE(0x111ee2, 0xffff);
3320 W2BYTE(0x1032c0, 0xd000);
3321 W2BYTE(0x1032c0, 0xd330);
3322 W2BYTE(0x1032c0, 0xd320);
3323 W2BYTE(0x1032c2, 0x8f3f);
3324 // W2BYTE(0x1032c4, 0xac40); //Addr:62; bit[11:10] = 2'b11; => reg_vby1_w_r_ini[1:0]
3325 //W2BYTE(0x1032cc, 0xac40); //Addr:66; bit[11:10] = 2'b11; => reg_vby1_w_r_ini_osd[1:0]
3326 //==========================//
3327 //= GPIO =//
3328 //==========================//
3329 W2BYTE(0x111e80, 0xffff);
3330 W2BYTE(0x111e82, 0xffff);
3331 W2BYTE(0x111e84, 0xffff);
3332 W2BYTE(0x111e86, 0xffff);
3333 W2BYTE(0x111e90, 0xffff);
3334 W2BYTE(0x111e92, 0xffff);
3335
3336 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
3337 {
3338 printf("Vx1 2 division\n");
3339 //==========================//
3340 //= Setting MOD =//
3341 //==========================//
3342 W2BYTE(0x103240, 0x0002); //[2:0]reg_mft_mode
3343 W2BYTE(0x103242, 0x1002); //[11:0]reg_dly_value
3344 W2BYTE(0x103244, 0x0f00); //[12:0]reg_hsize
3345 W2BYTE(0x10324c, 0x0780); //[12:0]reg_div_len
3346 W2BYTE(0x1032fe, 0x0002); //[2:0]reg_sram_usage
3347 W2BYTE(0x1032a6, 0x4000); //[14]reg_vfde_mask
3348 //W2BYTE(0x103210, 0x6420); //vby1 swap
3349 //W2BYTE(0x103212, 0x7531);
3350 //W2BYTE(0x1032c6, 0x1800); //[12]vby1_8ch[11:10]pair_mirror2
3351 }
3352 }
3353
3354 }
3355
MHal_PNL_GetPanelVStart(void)3356 MS_U16 MHal_PNL_GetPanelVStart(void)
3357 {
3358 return 8;
3359 }
3360
MHal_PNL_Check_VBY1_Handshake_Status(void * pInstance)3361 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance)
3362 {
3363 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE)
3364 {
3365 //printf("VBY1 handshake return because the reg value is 0x%u, not 0xFAE.\n", MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF));
3366 return FALSE;
3367 }
3368 else
3369 {
3370 //printf("VBY handshake check success.\n");
3371 return TRUE;
3372 }
3373 }
3374
MHal_PNL_ChannelFIFOPointerADjust(void * pInstance)3375 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance)
3376 {
3377 // 0 to 1 then will do write and read point capture to
3378 // Read : REG_MOD_BK00_5F_L[14:12]
3379 // write : REG_MOD_BK00_5F_L[10:8]
3380 // it takes 3 ticks to capture and riu takes 5 ticks to write
3381 // so we don't have to do any delay between rising capture and
3382 // read/write pointer recognition
3383 MsOS_DelayTaskUs(500);
3384 MOD_A_W2BYTE(REG_MOD_A_BK00_5C_L, 0x3300);
3385
3386 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
3387 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
3388
3389 //split Video & OSD process start bit
3390 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
3391 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
3392 {
3393 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
3394 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
3395 }
3396
3397 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
3398 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
3399
3400 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
3401 MS_U16 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3402 MS_S8 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3403 MS_S8 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3404
3405 //OSD part
3406 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
3407 MS_U16 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3408 MS_S8 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3409 MS_S8 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3410
3411 MS_BOOL bOSDC = ((MOD_A_R2BYTE(REG_MOD_A_BK00_58_L)&0x00F0) == 0x0040)?TRUE:FALSE;
3412 while (((abs(u8WritePointer-u8ReadPointer) >4) && (abs(u8WritePointer-u8ReadPointer)<2))
3413 ||(((abs(OSDu8WritePointer-OSDu8ReadPointer) >4) && (abs(OSDu8WritePointer-OSDu8ReadPointer)<2))&&bOSDC))
3414 {
3415 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
3416 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
3417
3418 //split Video & OSD process start bit
3419 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
3420 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
3421 {
3422 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
3423 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
3424 }
3425
3426 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
3427 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
3428
3429 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
3430 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3431 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3432 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3433
3434 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
3435 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3436 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3437 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3438 printf("bOSDC [%d]\n",bOSDC);
3439
3440 }
3441
3442 }
3443
MHal_PNL_VBY1_Hardware_TrainingMode_En(void * pInstance,MS_BOOL bIsVideoMode,MS_BOOL bEnable)3444 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable)
3445 {
3446 if(bIsVideoMode)
3447 {
3448 if(bEnable)
3449 {
3450 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE);
3451 }
3452 else
3453 {
3454 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AA6);
3455 }
3456 }
3457 else
3458 {
3459 if(bEnable)
3460 {
3461 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE);
3462 }
3463 else
3464 {
3465 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6);
3466 }
3467 }
3468 }
3469
MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void * pInstance)3470 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance)
3471 {
3472 #ifdef SUPPORT_VBY1_HWTRAINING_MODE
3473 return TRUE;
3474 #else
3475 return FALSE;
3476 #endif
3477 }
3478
MHal_PNL_TCON_Patch(void)3479 void MHal_PNL_TCON_Patch(void)
3480 {
3481 // MOD sw reset
3482 MOD_W2BYTE(REG_MOD_BK00_42_L,0x0000);
3483 MOD_W2BYTE(REG_MOD_BK00_42_L,0x1000);
3484
3485 // Setting TCON signal through MOD PAD
3486 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1811);
3487 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9811);
3488 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
3489 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1912);
3490 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9912);
3491 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
3492 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1a13);
3493 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9a13);
3494 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
3495 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x1b17);
3496 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x9b17);
3497 MOD_A_W2BYTE(REG_MOD_A_BK00_51_L,0x0000);
3498 }
3499 #endif
3500
3501