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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_PNL_H_ 103 #define _HAL_PNL_H_ 104 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 #ifdef _HAL_PNL_C_ 110 #define HAL_PNL_INTERFACE 111 #else 112 #define HAL_PNL_INTERFACE extern 113 #endif 114 115 // Current platform is DAC out or not 116 #define IS_DAC_OUT FALSE 117 118 // version0: Not support TV chip as HDMITx 119 // version1: Maserati + Raptor 120 // version2: Maxim + inside HDMITx 121 #define HW_DESIGN_HDMITX_VER (0) 122 123 // XC register serpead define 124 #define XC_REGISTER_SPREAD 1 125 #define SUPPORT_FRC 0 126 #define REG_CHIP_REVISION 0x1ECEUL //0x1ECFUL is high byte 127 #define XC_SUPPORT_AUTO_VSYNC 1 128 #define PNL_SUPPORT_DEVICE_NUM 2 129 #define MONACO_SC2 130 #define PNL_SUPPORT_2P_MODE TRUE 131 //------------------------------------------------------------------------------------------------- 132 // Driver Capability 133 //------------------------------------------------------------------------------------------------- 134 #define GAMMA_10BIT BIT(0) ///< gamma value range up to 10 BIt 135 #define GAMMA_12BIT BIT(1) ///< gamma value range up to 12 BIT 136 137 #define GAMMA_8BIT_MAPPING BIT(0) ///< mapping GAMMA value to 256 sampline entries 138 #define GAMMA_10BIT_MAPPING BIT(1) ///< mapping GAMMA value to 1024 sampling entries 139 140 typedef struct 141 { 142 MS_U8 eSupportGammaType; ///< refer to HAL_PNL_GAMMA_TYPE 143 MS_U8 eSupportGammaMapMode; ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE 144 } PNL_HalInfo; 145 146 #define SUPPORT_OVERDRIVE 1 147 #define GAMMA_TYPE (GAMMA_10BIT | GAMMA_12BIT) 148 #define GAMMA_MAPPING (GAMMA_8BIT_MAPPING | GAMMA_10BIT_MAPPING) 149 #define SUPPORT_SYNC_FOR_DUAL_MODE TRUE //New feature after T7 150 #define ENABLE_Auto_ModCurrentCalibration 1 151 152 // MIU Word (Bytes) 153 #define BYTE_PER_WORD (32) 154 155 #define SUPPORT_TCON TRUE 156 //------------------------------------------------------------------------------------------------- 157 // Macro and Define 158 //------------------------------------------------------------------------------------------------- 159 160 161 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 162 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 163 164 // NONPM 165 #define REG_RVD_BASE 0x100A00UL 166 #define REG_CHIPTOP_BASE 0x100B00UL // 0x1E00 - 0x1EFF 167 #if XC_REGISTER_SPREAD 168 #define REG_SCALER_BASE 0x130000UL 169 #else 170 #define REG_SCALER_BASE 0x102F00UL 171 #endif 172 #define REG_HDGEN_BASE 0x103000UL 173 #define REG_LPLL_BASE 0x103100UL 174 #define REG_MOD_BASE 0x103200UL 175 #define REG_MOD_A_BASE 0x111E00UL 176 #define REG_CLKGEN1_BASE 0x103300UL 177 #define REG_UTMI1_BASE 0x103A00UL 178 179 #define REG_CLKGEN0_BASE 0x100B00UL 180 #define REG_CLKGEN1_BASE 0x103300UL 181 182 183 /* TCON */ 184 #define L_BK_TCON(x) BK_REG_L(REG_HDGEN_BASE, x) 185 #define H_BK_TCON(x) BK_REG_H(REG_HDGEN_BASE, x) 186 187 /* LPLL */ 188 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 189 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 190 191 /* UTMI1 */ 192 #define L_BK_UTMI1(x) BK_REG_L(REG_UTMI1_BASE, x) 193 #define H_BK_UTMI1(x) BK_REG_H(REG_UTMI1_BASE, x) 194 195 196 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 197 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 198 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 199 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 200 201 #define REG_CLKGEN0_52_L (REG_CHIPTOP_BASE + 0xA4) 202 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) 203 #define REG_CLKGEN0_57_L (REG_CHIPTOP_BASE + 0xAE) 204 #define REG_CLKGEN0_58_L (REG_CHIPTOP_BASE + 0xB0) 205 #define REG_CLKGEN0_5E_L (REG_CHIPTOP_BASE + 0xBC) 206 #define REG_CLKGEN0_63_L (REG_CHIPTOP_BASE + 0xC6) 207 208 #define REG_CLKGEN1_31_L (REG_CLKGEN1_BASE + 0x62) 209 #define REG_RVD_09_L (REG_RVD_BASE + 0x12) 210 211 212 213 #define XC_PAFRC_DITH_NOISEDITH_EN (0x00) 214 #define XC_PAFRC_DITH_TAILCUT_DISABLE (0x00) 215 216 #define LVDS_DUAL_OUTPUT 0 217 #define LVDS_DUAL_OUTPUT_SPECIAL 1// only for use with T8 board 218 #define LVDS_SINGLE_OUTPUT_A 2 219 #define LVDS_SINGLE_OUTPUT_B 3 220 #define LVDS_OUTPUT_User 4 221 222 // SCALER CLK select 223 #define REG_CKG_ODCLK REG_CLKGEN0_53_L 224 #define CKG_ODCLK_GATED BIT(0) 225 #define CKG_ODCLK_INVERT BIT(1) 226 #define CKG_ODCLK_MASK (BIT(3) | BIT(2)) 227 #define CKG_ODCLK_CLK_SC_PLL (0 << 2) 228 #define CKG_ODCLK_27M (2 << 2) 229 #define CKG_ODCLK_CLK_LPLL (3 << 2) 230 #define CKG_ODCLK_XTAL (1 << 2) 231 232 #define REG_CKG_BT656 REG_CLKGEN0_53_L 233 #define CKG_BT656_GATED BIT(8) 234 #define CKG_BT656_INVERT BIT(9) 235 #define CKG_BT656_MASK (BIT(11) | BIT(10)) 236 #define CKG_BT656_CLK_SC_PLL (0 << 10) 237 #define CKG_BT656_CLK_LPLL_DIV_2 (1 << 10) 238 #define CKG_BT656_27M (2 << 10) 239 #define CKG_BT656_CLK_LPLL (3 << 10) 240 241 #define REG_CKG_TX_MOD REG_CLKGEN0_58_L 242 #define CKG_TX_MOD_GATED BIT(0) 243 #define CKG_TX_MOD_INVERT BIT(1) 244 #define CKG_TX_MOD_MASK (BIT(3) | BIT(2)) 245 #define CKG_TX_1X_4XDIGITAL (0 << 2) 246 247 #define PANEL_LPLL_INPUT_DIV_1st 0x00 248 #define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 249 #define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8 250 #define PANEL_LPLL_LOOP_DIV_2nd 0x01 // 251 #define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 252 #define PANEL_LPLL_OUTPUT_DIV_2nd 0x00 253 254 #define LVDS_MPLL_CLOCK_MHZ 432 // For crystal 24Mhz 255 #define LVDS_SPAN_FACTOR 131072 256 257 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 258 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 259 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 260 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 261 262 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 263 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 264 265 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 266 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 267 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 268 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 269 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 270 271 #define SUPPORT_MOD_ADBANK_SEPARATE 272 273 #define SUPPORT_VBY1_HWTRAINING_MODE 274 //------------------------------------------------------------------------------------------------- 275 // Type and Structure 276 //------------------------------------------------------------------------------------------------- 277 typedef enum 278 { 279 E_HALPNL_DEVICE0_XC_BANK_OFFSET = 0, 280 E_HALPNL_DEVICE1_XC_BANK_OFFSET = 0x80 281 }PNL_HAL_DEVICE_XC_BANK_OFFSET; 282 283 typedef enum 284 { 285 E_DRVPNL_ALLIN_MODE = 1, 286 E_DRVPNL_2X_MODE = 2, 287 E_DRVPNL_SEPARATE_MODE = 3, 288 E_DRVPNL_TYPE_NUM 289 }DRVPNL_OUT_SWING_TYPE; 290 291 typedef enum 292 { 293 HAL_TI_10BIT_MODE = 0, 294 HAL_TI_8BIT_MODE = 2, 295 HAL_TI_6BIT_MODE = 3, 296 } PNL_HAL_TIMODES; 297 298 //------------------------------------------------------------------------------------------------- 299 // Function and Variable 300 //------------------------------------------------------------------------------------------------- 301 HAL_PNL_INTERFACE MS_VIRT g_ptr_PnlRiuBaseAddr; 302 HAL_PNL_INTERFACE MS_VIRT g_ptr_PMRiuBaseAddr; 303 304 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 305 void MHal_PNL_TCON_Init(void *pInstance); 306 307 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 308 309 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type); 310 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 311 void MHal_Output_Channel_Order(void *pInstance, MS_U8 Type, MS_U16 u16OutputOrder0_3, MS_U16 u16OutputOrder4_7, MS_U16 u16OutputOrder8_11, MS_U16 u16OutputOrder12_13); 312 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance); 313 314 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 315 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance); 316 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping); 317 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue); 318 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue); 319 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode); 320 #ifdef MONACO_SC2 321 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode ); 322 #endif 323 #define Hal_PNL_Get12BitGammaPerChannel(args...) 324 //void _MDrv_PNL_Set_12BIT_Gamma(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab); 325 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src); 326 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz); 327 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 328 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 329 330 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance); 331 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 332 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 333 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_PHY u32OD_LSB_Addr, MS_PHY u32OD_LSB_limit, MS_U8 u8MIUSel); 334 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 335 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]); 336 337 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 338 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance); 339 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 340 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 341 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level); 342 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select); 343 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level); 344 345 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData); 346 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData); 347 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask); 348 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 349 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 350 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance); 351 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); 352 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 353 354 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank); 355 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz); 356 357 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank); 358 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance); 359 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance); 360 361 362 /// Set pair swap for user mode 363 #define MHal_FRC_MOD_PairSwap_UserMode(args...) 364 365 #define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC 366 367 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz); 368 369 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance); 370 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance); 371 372 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable); 373 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance); 374 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat); 375 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 376 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 377 378 void MHal_PNL_Set_T3D_Setting(void *pInstance); 379 380 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance); 381 void MHal_PNL_Init(void *pInstance); 382 void MHal_PNL_Bringup(void *pInstance); 383 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance); 384 385 MS_U16 MHal_PNL_GetPanelVStart(void); 386 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance); 387 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable); 388 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance); 389 void MHal_PNL_TCON_Patch(void); 390 391 392 #ifdef __cplusplus 393 } 394 #endif 395 396 #endif // _HAL_PNL_H_ 397 398