Lines Matching refs:L_CLKGEN0
2697 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2698 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2699 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2700 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2703 W2BYTEMSK(L_CLKGEN0(0x58), 0x0001, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2708 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2709 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2710 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2711 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_DIV_2, CKG_ODCLK_MASK); // [4..3] LPLL cloc… in MHal_PNL_Init_XC_Clk()
2714 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2718 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2719 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2720 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2721 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // [4..3] LPLL clock… in MHal_PNL_Init_XC_Clk()
2728 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2729 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2730 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_SEL_LPLL, CKG_ODCLK_SEL_SOURCE); // [2] select sourc… in MHal_PNL_Init_XC_Clk()
2731 … W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_XTAL, CKG_ODCLK_MASK); // [4..3] LPLL clock div in MHal_PNL_Init_XC_Clk()
2734 W2BYTEMSK(L_CLKGEN0(0x58), 0x0000, 0x000F); //[3:0]ckg_tx_mod in MHal_PNL_Init_XC_Clk()
2738 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_MFT_GATED); // [8] disable … in MHal_PNL_Init_XC_Clk()
2739 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_MFT_INVERT); // [9] invert c… in MHal_PNL_Init_XC_Clk()
2740 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_MFT_SEL_LPLL, CKG_ODCLK_MFT_SEL_SOURCE); // [10] select … in MHal_PNL_Init_XC_Clk()
2741 …W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_MFT_XTAL, CKG_ODCLK_MFT_MASK); // [12:11] LPLL… in MHal_PNL_Init_XC_Clk()
2750 W2BYTEMSK(L_CLKGEN0(0x56),0x0010, 0x00F0); //[7:4]reg_ckg_odclk_a in MHal_PNL_Init_XC_Clk()
2751 … W2BYTE(L_CLKGEN0(0x63),0x1001); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
2756 W2BYTE(L_CLKGEN0(0x5A),0x0800); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode in MHal_PNL_Init_XC_Clk()
2761 W2BYTE(L_CLKGEN0(0x5A),0x0900); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode in MHal_PNL_Init_XC_Clk()
2765 W2BYTE(L_CLKGEN0(0x5A),0x0A00); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode in MHal_PNL_Init_XC_Clk()
2775 W2BYTEMSK(L_CLKGEN0(0x56),0x0040, 0x00F0); //[7:4]reg_ckg_odclk_a in MHal_PNL_Init_XC_Clk()
2776 … W2BYTE(L_CLKGEN0(0x63),0x1100); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
2780 W2BYTE(L_CLKGEN0(0x63),0x1000); //[7:4]reg_ckg_odclk_a in MHal_PNL_Init_XC_Clk()
2782 W2BYTEMSK(L_CLKGEN0(0x56),0x0000, 0x000F); //[7:4]reg_ckg_odclk_a in MHal_PNL_Init_XC_Clk()
2787 … W2BYTE(L_CLKGEN0(0x63),0x1000); //[15:12]reg_ckg_nossc_odclk[11:8]ckg_tx_mod [5:0]ckg_osd2mod in MHal_PNL_Init_XC_Clk()
2809 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0010, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
2819 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x00A0, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
2828 …W2BYTEMSK(L_CLKGEN0(0x7E), 0x0030, 0x00FC); //LPLL_ODCLK setting reg_ckg_odclk = reg_cl… in MHal_PNL_Init_XC_Clk()
3914 W2BYTE(L_CLKGEN0(0x5A),0x8800); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode in MHal_PNL_SetOSDCOutputType()
3958 W2BYTE(L_CLKGEN0(0x5A),0x9900); //[15:12]reg_ckg_vby1_omode [11:8]reg_ckg_vby1_vmode in MHal_PNL_SetOSDCOutputType()