1 //<MStar Software>
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76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _HAL_PNL_C_
79 #define _HAL_PNL_C_
80
81 //-------------------------------------------------------------------------------------------------
82 // Include Files
83 //-------------------------------------------------------------------------------------------------
84
85 #include "MsCommon.h"
86 #include "MsTypes.h"
87 #include "utopia.h"
88 #include "utopia_dapi.h"
89 #include "apiPNL.h"
90 #include "apiPNL_v2.h"
91 #include "drvPNL.h"
92 #include "halPNL.h"
93 #include "PNL_private.h"
94 #include "pnl_hwreg_utility2.h"
95 #include "Macan_pnl_lpll_tbl.h"
96 #include "Macan_pnl_lpll_ext_tbl.h"
97
98 #ifdef MSOS_TYPE_LINUX_KERNEL
99 #include <linux/string.h>
100 #include <linux/delay.h>
101 #include <asm/div64.h>
102 #else
103 #include "string.h"
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114
115 #define UNUSED(x) (x=x)
116 #if 1
117 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { if((_dbgSwitch_ & _u16PnlDbgSwitch) != 0) printf("PNL:"_fmt, ##_args); }
118 #define HAL_MOD_CAL_DBG(x) //x
119 #else
120 #define HAL_PNL_DBG(_dbgSwitch_, _fmt, _args...) { }
121 #endif
122
123 #define DAC_LPLL_ICTRL 0x0002
124 #define LVDS_LPLL_ICTRL 0x0001
125
126 //Get MOD calibration time
127 #define MOD_CAL_TIMER FALSE
128
129 //if mboot read eFuse and fill the register, then add this define to mark utopia efuse code flow
130 #define MOD_EFUSE_IN_MBOOT
131
132 //for LVDS HW Calibration ICON limitation
133 #define MOD_LVDS_ICON_HIGH_LIMIT 0x2E
134 #define MOD_LVDS_ICON_LOW_LIMIT 0x06
135 #define MOD_LVDS_ICON_DEFAULT 0x19
136
137 //for LVDS HW Calibration timeout (i.e. retry times after hw calibration failed)
138 #define MOD_LVDS_HW_CALI_TIME_OUT 3
139
140 #define LANE_NUM_EACH_PINMAPPING_GROUP1 4
141 #define LANE_NUM_EACH_PINMAPPING_GROUP2 4
142 #define LANE_NUM_EACH_PINMAPPING_GROUP3 4
143 #define LANE_NUM_EACH_PINMAPPING_GROUP4 2
144
145 #define PINMAPPING_EXP 16
146
147 //-------------------------------------------------------------------------------------------------
148 // Local Structurs
149 //-------------------------------------------------------------------------------------------------
150
151 //-------------------------------------------------------------------------------------------------
152 // Global Variables
153 //-------------------------------------------------------------------------------------------------
154
155 //-------------------------------------------------------------------------------------------------
156 // Local Variables
157 //-------------------------------------------------------------------------------------------------
158 MS_U8 LANE_AND_CLK_TBL[VBY1_CLK_TBL_ROW][3]=
159 { //lane(from) lane(to) bit(mask)
160 { 0, 3, 0x02, },
161 { 4, 7, 0x04, },
162 { 8, 10, 0x08, },
163 { 11, 21, 0x10, }
164 };
165 //-------------------------------------------------------------------------------------------------
166 // Debug Functions
167 //-------------------------------------------------------------------------------------------------
168
169 //-------------------------------------------------------------------------------------------------
170 // Local Functions
171 //-------------------------------------------------------------------------------------------------
172 static MS_BOOL _Hal_MOD_External_eFuse(void);
173 static MS_U16 _Hal_MOD_Refine_ICON(MS_U16 u16ICON);
174 static void _MHal_PNL_Auto_Set_Config(void *pInstance,
175 MS_U16 u16OutputOrder0_3,
176 MS_U16 u16OutputOrder4_7,
177 MS_U16 u16OutputOrder8_11,
178 MS_U16 u16OutputOrder12_13);
179
180 static void _MHal_PNL_Set_Clk(void *pInstance,
181 MS_U8 u8LaneNum,
182 MS_U16 u16OutputOrder0_3,
183 MS_U16 u16OutputOrder4_7,
184 MS_U16 u16OutputOrder8_11,
185 MS_U16 u16OutputOrder12_13);
186
187 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance);
188 //-------------------------------------------------------------------------------------------------
189 // Global Function
190 //-------------------------------------------------------------------------------------------------
191 /**
192 * @brief: Power On MOD. but not mutex protected
193 *
194 */
MHal_MOD_PowerOn(void * pInstance,MS_BOOL bEn,MS_U8 u8LPLL_Type,MS_U8 DualModeType,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)195 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
196 {
197 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
198 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
199 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
200 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
201
202 if( bEn )
203 {
204 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x00, BIT(8));
205
206 //analog MOD power down. 1: power down, 0: power up
207 // For Mod2 no output signel
208 ///////////////////////////////////////////////////
209
210 //2. Power on MOD (current and regulator)
211 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00 , BIT(0));
212 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(8) , BIT(8));
213
214
215 // 3. 4. 5.
216 MHal_Output_LVDS_Pair_Setting(pInstance, DualModeType, u16OutputCFG0_7, u16OutputCFG8_15, u16OutputCFG16_21);
217
218
219 //enable ib, enable ck
220 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, (BIT(1) | BIT(0)), (BIT(1) | BIT(0)));
221
222 // clock gen of dot-mini
223 if(u8LPLL_Type == E_PNL_TYPE_MINILVDS)
224 {
225 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x4400);
226 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x4400);
227 }
228 else if((u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
229 (u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)||
230 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE) ||
231 (u8LPLL_Type == E_PNL_LPLL_VBY1_8BIT_2LANE))
232
233 {
234 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
235 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
236 // [7:4]reg_ckg_dot_mini_pre_osd
237 }
238 //// for osd dedicated output port, 1 port for video and 1 port for osd
239 else if((u8LPLL_Type == E_PNL_TYPE_HS_LVDS)&&
240 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
241 {
242 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0400); // [11:8]reg_ckg_dot_mini_pre2_osd
243 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); // [3:0]reg_ckg_dot_mini_osd
244 // [7:4]reg_ckg_dot_mini_pre_osd
245 }
246 else if(u8LPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
247 {
248 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0000); // [11:8]reg_ckg_dot_mini_pre2_osd
249 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0000); // [3:0]reg_ckg_dot_mini_osd
250 }
251 else
252 {
253 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0000);
254 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0000);
255 }
256 }
257 else
258 {
259 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, BIT(8), BIT(8));
260 if(u8LPLL_Type !=E_PNL_TYPE_MINILVDS)
261 {
262 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: power up
263 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(8));
264 }
265
266 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0, (BIT(1) | BIT(0) )); //enable ib, enable ck
267
268 // clock gen of dot-mini
269 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x1100);
270 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x1100);
271
272 if((u8LPLL_Type>=E_PNL_LPLL_VBY1_10BIT_4LANE)&&(u8LPLL_Type<=E_PNL_LPLL_VBY1_8BIT_8LANE))
273 {
274 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
275 MsOS_DelayTask(1);
276 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
277 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
278 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
279 }
280 }
281 return 1;
282 }
283
284 /**
285 * @brief: Setup the PVDD power 1:2.5V, 0:3.3V
286 *
287 */
MHal_MOD_PVDD_Power_Setting(void * pInstance,MS_BOOL bIs2p5)288 void MHal_MOD_PVDD_Power_Setting(void *pInstance, MS_BOOL bIs2p5)
289 {
290 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, ((bIs2p5)? BIT(6):0), BIT(6)); //MOD PVDD=1: 0.9
291 }
292
MHal_PNL_TCON_Init(void * pInstance)293 void MHal_PNL_TCON_Init(void *pInstance)
294 {
295
296 }
297
MHal_Shift_LVDS_Pair(void * pInstance,MS_U8 Type)298 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type)
299 {
300 if(Type == 1)
301 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LVDS Mode3
302 else
303 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6)));
304
305 }
306
MHal_Output_LVDS_Pair_Setting(void * pInstance,MS_U8 Type,MS_U16 u16OutputCFG0_7,MS_U16 u16OutputCFG8_15,MS_U16 u16OutputCFG16_21)307 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21)
308 {
309
310 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
311 {
312 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0555);
313 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x1554);
314 }
315 else if(Type == LVDS_SINGLE_OUTPUT_A)
316 {
317 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
318 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
319 }
320 else if( Type == LVDS_SINGLE_OUTPUT_B)
321 {
322 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
323 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
324 }
325 else if( Type == LVDS_OUTPUT_User)
326 {
327 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16OutputCFG0_7);
328 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16OutputCFG8_15);
329 }
330 else
331 {
332 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x5550, 0xFFF0);
333 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0555);
334 }
335
336 MsOS_DelayTask(2);
337
338
339 }
340
MHal_Output_Channel_Order(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)341 void MHal_Output_Channel_Order(void *pInstance,
342 MS_U8 Type,
343 MS_U16 u16OutputOrder0_3,
344 MS_U16 u16OutputOrder4_7,
345 MS_U16 u16OutputOrder8_11,
346 MS_U16 u16OutputOrder12_13)
347 {
348 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
349 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
350 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
351 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
352
353 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
354 {
355 MOD_W2BYTE(REG_MOD_BK00_08_L, u16OutputOrder0_3);
356 MOD_W2BYTE(REG_MOD_BK00_09_L, u16OutputOrder4_7);
357 MOD_W2BYTE(REG_MOD_BK00_0A_L, u16OutputOrder8_11);
358 MOD_W2BYTE(REG_MOD_BK00_0B_L, u16OutputOrder12_13);
359 }
360 else
361 {
362 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
363 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
364 {
365 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // 2 Divisoin
366 {
367 MOD_W2BYTE(REG_MOD_BK00_08_L, 0xBA98);
368 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x6420);
369 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7531);
370 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
371 }
372 else
373 {
374 MOD_W2BYTE(REG_MOD_BK00_08_L, 0xBA98);
375 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x3210);
376 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7654);
377 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
378 }
379 }
380 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)||
381 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE)||
382 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)||
383 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
384 {
385 MOD_W2BYTE(REG_MOD_BK00_08_L, 0xBA98);
386 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x3210);
387 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x7654);
388 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0000);
389 }
390 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
391 {//LVDS
392 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x10DC);
393 MOD_W2BYTE(REG_MOD_BK00_09_L, 0x5432);
394 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x9876);
395 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x00BA);
396 }
397 else
398 {
399 MOD_W2BYTE(REG_MOD_BK00_08_L, 0x76DC);
400 MOD_W2BYTE(REG_MOD_BK00_09_L, 0xBA98);
401 MOD_W2BYTE(REG_MOD_BK00_0A_L, 0x3210);
402 MOD_W2BYTE(REG_MOD_BK00_0B_L, 0x0054);
403 }
404 }
405
406 }
407
MHal_PQ_Clock_Gen_For_Gamma(void * pInstance)408 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance)
409 {
410 W2BYTEMSK(REG_CLKGEN0_52_L, 0x00, 0x07);
411 }
412
MHal_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)413 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping)
414 {
415 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
416 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
417
418 if(u8Mapping & GAMMA_MAPPING)
419 {
420 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_74_L, (u8Mapping & GAMMA_10BIT_MAPPING)? BIT(15):0, BIT(15));
421 }
422 else
423 {
424 PNL_ASSERT(0, "Invalid eSupportGammaMapMode [%d] Passed to [%s], please make sure the u8Mapping[%d] is valid\n.",
425 u8Mapping, __FUNCTION__, u8Mapping);
426 }
427 }
428
Hal_VOP_Is_GammaMappingMode_enable(void * pInstance)429 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance)
430 {
431 // Only support 1024 entry
432 return TRUE;
433 }
434
435 // After A5, 8 bit mode only support burst write!!!
Hal_VOP_Is_GammaSupportSignalWrite(void * pInstance,DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)436 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping)
437 {
438 if( u8Mapping == E_DRVPNL_GAMMA_10BIT_MAPPING )
439 return TRUE;
440 else
441 return FALSE;
442 }
443
444 /////////////////////////////////////////////////////////////////////////////
445 // Gamma format (12 bit LUT)
446 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
447 // 1 set uses 2 bytes of memory.
448 //
449 // [T2 and before ] N = 256
450 // [T3] N = 256 or 1024
451 // ______________________________________________________________________________
452 // Byte | 0 1 2 n-1 n
453 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
454 // 3:0 3:0 11:4 11:4 3:0 11:4
455 //
456 #ifdef MONACO_SC2
Hal_PNL_Set12BitGammaPerChannel_SC2(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)457 void Hal_PNL_Set12BitGammaPerChannel_SC2(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
458 {
459 MS_U16 u16Addr = 0;
460 MS_U16 u16CodeTableIndex = u16Addr/2*3;
461 MS_U16 u16GammaValue = 0;
462 MS_U16 u16MaxGammaValue = 0;
463 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
464 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
465 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
466 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
467
468 // Go to burst write if not support
469 if ( bUsingBurstWrite )
470 {
471 // 1. initial burst write address, LUT_ADDR[7:0]
472 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6C_L, 0x00 , 0x3FF);
473
474 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
475 switch(u8Channel)
476 {
477 case 0: // Red
478 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(3) | BIT(2) );
479 break;
480
481 case 1: // Green
482 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(2) , BIT(3) | BIT(2) );
483 break;
484
485 case 2: // Blue
486 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(3) , BIT(3) | BIT(2) );
487 break;
488 }
489
490 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
491 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, BIT(0) , BIT(0)); // Burst write enable
492
493 }
494
495 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
496 // write gamma table per one channel
497 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
498 {
499 // gamma x
500 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
501 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
502
503 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
504 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
505
506 if(u16MaxGammaValue < u16GammaValue)
507 {
508 u16MaxGammaValue = u16GammaValue;
509 }
510
511 // write gamma value
512 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
513 u16Addr++;
514
515 // gamma x+1
516 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
517 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
518
519 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
520
521 if(u16MaxGammaValue < u16GammaValue)
522 {
523 u16MaxGammaValue = u16GammaValue;
524 }
525
526 // write gamma value
527 hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
528 u16Addr++;
529 }
530
531 if ( bUsingBurstWrite )
532 {
533 // 5. after finish burst write data of one channel, disable burst write mode
534 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0x00 , BIT(0));
535 }
536
537 hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
538 }
539 #endif
540
541 #ifdef USE_PANEL_GAMMA
_hal_PNL_WriteGamma12Bit_PanelGamma(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)542 static void _hal_PNL_WriteGamma12Bit_PanelGamma(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
543 {
544 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
545 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
546
547 MS_U16 u16Delay = 0xFFFF;
548
549 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write [ch %d][addr 0x%x]: 0x%x \n", u8Channel, u16Addr, u16GammaValue);
550
551 if (!bBurstWrite )
552 {
553 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, 0x0C) && (--u16Delay)); // Check whether the Write chanel is ready
554 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
555
556 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_1B_L, u16Addr, 0xFF); // set address port
557 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK24_1D_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
558
559 // kick off write
560 switch(u8Channel)
561 {
562 case 0: // Red
563 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, 0x00 , BIT(3) | BIT(2) );
564 break;
565
566 case 1: // Green
567 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, BIT(2) , BIT(3) | BIT(2) );
568 break;
569
570 case 2: // Blue
571 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, BIT(3) , BIT(3) | BIT(2) );
572 break;
573
574 }
575
576 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_1C_L, 0x0C) && (--u16Delay)); // Check whether the Write chanel is ready
577 }
578 else
579 {
580
581 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1D_L, u16GammaValue, 0xFFF);
582 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK00_7F_L, 0x00); // make little time delay
583 }
584
585
586 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
587 }
588
_hal_PNL_SetMaxGammaValue_PanelGamma(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)589 static void _hal_PNL_SetMaxGammaValue_PanelGamma(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
590 {
591 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
592 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
593
594 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of SC%tu %d is 0x%x\n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16MaxGammaValue);
595 switch(u8Channel)
596 {
597 case 0: // max. Red
598 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_2C_L , u16MaxGammaValue, 0xFFF); // max. base 0
599 break;
600
601 case 1: // max. Green
602 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_2E_L , u16MaxGammaValue, 0xFFF); // max. base 1
603 break;
604
605 case 2: //max. Blue
606 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_30_L , u16MaxGammaValue, 0xFFF); // max. base 1
607 break;
608 }
609 }
610
_Hal_PNL_Set12BitGammaPerChannel_PanelGamma(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)611 static void _Hal_PNL_Set12BitGammaPerChannel_PanelGamma(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode )
612 {
613 MS_U16 u16Addr = 0;
614 MS_U16 u16CodeTableIndex = u16Addr/2*3;
615 MS_U16 u16GammaValue = 0;
616 MS_U16 u16MaxGammaValue = 0;
617 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
618 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
619 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
620 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
621
622 // Go to burst write if not support
623 if ( bUsingBurstWrite )
624 {
625 // 1. initial burst write address, LUT_ADDR[7:0]
626 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1B_L, 0x00 , 0xFF);
627
628 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
629 switch(u8Channel)
630 {
631 case 0: // Red
632 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, 0x00 , BIT(3) | BIT(2) );
633 break;
634
635 case 1: // Green
636 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, BIT(2) , BIT(3) | BIT(2) );
637 break;
638
639 case 2: // Blue
640 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, BIT(3) , BIT(3) | BIT(2) );
641 break;
642 }
643
644 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
645 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, BIT(0) , BIT(0)); // Burst write enable
646
647 }
648
649 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
650 // write gamma table per one channel
651 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
652 {
653 // gamma x
654 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
655 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
656
657 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
658 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
659
660 if(u16MaxGammaValue < u16GammaValue)
661 {
662 u16MaxGammaValue = u16GammaValue;
663 }
664
665 // write gamma value
666 _hal_PNL_WriteGamma12Bit_PanelGamma(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
667 u16Addr++;
668
669 // gamma x+1
670 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
671 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
672
673 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
674
675 if(u16MaxGammaValue < u16GammaValue)
676 {
677 u16MaxGammaValue = u16GammaValue;
678 }
679
680 // write gamma value
681 _hal_PNL_WriteGamma12Bit_PanelGamma(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
682 u16Addr++;
683 }
684
685 if ( bUsingBurstWrite )
686 {
687 // 5. after finish burst write data of one channel, disable burst write mode
688 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK24_1C_L, 0x00 , BIT(0));
689 }
690 _hal_PNL_SetMaxGammaValue_PanelGamma(pInstance,u8Channel, u16MaxGammaValue);
691 }
692
693 #endif
694
_hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)695 static void _hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
696 {
697 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
698 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
699
700 MS_U16 u16Delay = 0xFFFF;
701
702 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Write [ch %d][addr 0x%x]: 0x%x \n", u8Channel, u16Addr, u16GammaValue);
703
704 if (!bBurstWrite )
705 {
706 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
707 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
708
709 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6C_L, u16Addr, 0x3FF); // set address port
710 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_6E_L + u8Channel *2), u16GammaValue, 0xFFF); // Set channel data
711
712 // kick off write
713 switch(u8Channel)
714 {
715 case 0: // Red
716 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(5), BIT(5));
717 break;
718
719 case 1: // Green
720 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(6), BIT(6));
721 break;
722
723 case 2: // Blue
724 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, BIT(7), BIT(7));
725 break;
726 }
727
728 while (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_6D_L, 0xE0) && (--u16Delay)); // Check whether the Write chanel is ready
729 }
730 else
731 {
732
733 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_72_L, u16GammaValue, 0xFFF);
734 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK00_7F_L, 0x00); // make little time delay
735 }
736
737
738 PNL_ASSERT(u16Delay > 0, "%s\n", "WriteGamma timeout");
739 }
740
741
_hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)742 static void _hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
743 {
744 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
745 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
746
747 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Max gamma of SC%tu %d is 0x%x\n", (ptrdiff_t)pPNLInstancePrivate->u32DeviceID, u8Channel, u16MaxGammaValue);
748 #ifdef MONACO_SC2
749 if(pPNLInstancePrivate->u32DeviceID == 0)
750 {
751 #endif
752 switch(u8Channel)
753 {
754 case 0: // max. Red
755 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 0
756 break;
757
758 case 1: // max. Green
759 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 1
760 break;
761
762 case 2: //max. Blue
763 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
764 break;
765 }
766 #ifdef MONACO_SC2
767 }else //Nike
768 {
769 switch(u8Channel)
770 {
771 case 0: // max. Red
772 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7A_L , u16MaxGammaValue, 0xFFF); // max. base 0
773 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7B_L , u16MaxGammaValue, 0xFFF); // max. base 1
774 break;
775
776 case 1: // max. Green
777 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7C_L , u16MaxGammaValue, 0xFFF); // max. base 0
778 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7D_L , u16MaxGammaValue, 0xFFF); // max. base 1
779 break;
780
781 case 2: //max. Blue
782 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7E_L , u16MaxGammaValue, 0xFFF); // max. base 0
783 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_7F_L , u16MaxGammaValue, 0xFFF); // max. base 1
784 break;
785 }
786
787 }
788 #endif
789 }
790
791 /////////////////////////////////////////////////////////////////////////////
792 // Gamma format (12 bit LUT)
793 // 0, 1, 2, 3, ..., NumOfLevel, totally N Sets of tNormalGammaR/G/B[],
794 // 1 set uses 2 bytes of memory.
795 //
796 // [T2 and before ] N = 256
797 // [T3] N = 256 or 1024
798 // ______________________________________________________________________________
799 // Byte | 0 1 2 n-1 n
800 // [G1|G0] [G0] [G1] . ...... . [Gmax] [Gmax]
801 // 3:0 3:0 11:4 11:4 3:0 11:4
802 //
_Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)803 static void _Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
804 {
805 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
806 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
807
808 MS_U16 u16Addr = 0;
809 MS_U16 u16CodeTableIndex = u16Addr/2*3;
810 MS_U16 u16GammaValue = 0;
811 MS_U16 u16MaxGammaValue = 0;
812 MS_U16 u16NumOfLevel = GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING ? 256 : 1024;
813 MS_BOOL bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance,GammaMapMode);
814
815 // Go to burst write if not support
816 if ( bUsingBurstWrite )
817 {
818 // 1. initial burst write address, LUT_ADDR[7:0]
819 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_71_L, 0x00 , 0x3FF);
820
821 // 2. select burst write channel, REG_LUT_BW_CH_SEL[1:0]
822 switch(u8Channel)
823 {
824 case 0: // Red
825 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, 0x00 , BIT(6) | BIT(5) );
826 break;
827
828 case 1: // Green
829 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(5) , BIT(6) | BIT(5) );
830 break;
831
832 case 2: // Blue
833 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(6) , BIT(6) | BIT(5) );
834 break;
835 }
836
837 // 3. enable burst write mode, REG_LUT_BW_MAIN_EN
838 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, BIT(7) , BIT(7)); // Burst write enable
839
840 }
841
842 //printf("\33[0;31m Gamma Mapping mode %d \n \33[m",GammaMapMode );
843 // write gamma table per one channel
844 for(; u16Addr < u16NumOfLevel; u16CodeTableIndex += 3)
845 {
846 // gamma x
847 u16GammaValue = u8Tab[u16CodeTableIndex] & 0x0F;
848 u16GammaValue |= u8Tab[u16CodeTableIndex+1] << 4;
849
850 PNL_DBG(PNL_DBGLEVEL_GAMMA,"Gamma x: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x, GammaLvl=%d\n",
851 u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+1, u8Tab[u16CodeTableIndex+1], u16GammaValue, u16NumOfLevel);
852
853 if(u16MaxGammaValue < u16GammaValue)
854 {
855 u16MaxGammaValue = u16GammaValue;
856 }
857
858 // write gamma value
859 _hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
860 u16Addr++;
861
862 // gamma x+1
863 u16GammaValue = (u8Tab[u16CodeTableIndex] & 0xF0) >> 4;
864 u16GammaValue |= u8Tab[u16CodeTableIndex+2] << 4;
865
866 PNL_DBG(PNL_DBGLEVEL_GAMMA, "Gamma x+1: SrcGTbl[%d] = 0x%x, [%d] = 0x%x, Gamma = 0x%x\n", u16CodeTableIndex, u8Tab[u16CodeTableIndex], u16CodeTableIndex+2, u8Tab[u16CodeTableIndex+2], u16GammaValue);
867
868 if(u16MaxGammaValue < u16GammaValue)
869 {
870 u16MaxGammaValue = u16GammaValue;
871 }
872
873 // write gamma value
874 _hal_PNL_WriteGamma12Bit(pInstance,u8Channel,bUsingBurstWrite, u16Addr, u16GammaValue);
875 u16Addr++;
876 }
877
878 if ( bUsingBurstWrite )
879 {
880 // 5. after finish burst write data of one channel, disable burst write mode
881 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK10_70_L, 0x00 , BIT(7));
882 }
883
884 _hal_PNL_SetMaxGammaValue(pInstance,u8Channel, u16MaxGammaValue);
885 }
886
hal_PNL_WriteGamma12Bit(void * pInstance,MS_U8 u8Channel,MS_BOOL bBurstWrite,MS_U16 u16Addr,MS_U16 u16GammaValue)887 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue)
888 {
889 #ifdef USE_PANEL_GAMMA
890 _hal_PNL_WriteGamma12Bit_PanelGamma(pInstance, u8Channel, bBurstWrite, u16Addr, u16GammaValue);
891 #endif
892 _hal_PNL_WriteGamma12Bit(pInstance, u8Channel, bBurstWrite, u16Addr, u16GammaValue);
893
894 }
895
hal_PNL_SetMaxGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16MaxGammaValue)896 void hal_PNL_SetMaxGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue)
897 {
898 #ifdef USE_PANEL_GAMMA
899 _hal_PNL_SetMaxGammaValue_PanelGamma(pInstance, u8Channel, u16MaxGammaValue);
900 #endif
901 _hal_PNL_SetMaxGammaValue(pInstance, u8Channel, u16MaxGammaValue);
902 }
903
Hal_PNL_Set12BitGammaPerChannel(void * pInstance,MS_U8 u8Channel,MS_U8 * u8Tab,DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)904 void Hal_PNL_Set12BitGammaPerChannel(void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
905 {
906 #ifdef USE_PANEL_GAMMA
907 _Hal_PNL_Set12BitGammaPerChannel_PanelGamma(pInstance, u8Channel, u8Tab, GammaMapMode);
908 #endif
909 _Hal_PNL_Set12BitGammaPerChannel(pInstance, u8Channel, u8Tab, GammaMapMode);
910 }
911
912 // src : 1 (scaler lpll)
913 // src : 0 (frc lpll)
MHal_PNL_FRC_lpll_src_sel(void * pInstance,MS_U8 u8src)914 MS_U8 MHal_PNL_FRC_lpll_src_sel(void *pInstance, MS_U8 u8src)
915 {
916 if (u8src > 1)
917 {
918 return FALSE;
919 }
920 else
921 {
922 //Not support two LPLL (frc lpll) for Manhattan
923 #if 0
924 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F);
925 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8));
926
927 if(u8src==0)
928 {
929 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F);
930 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8));
931 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0
932 }
933 #endif
934 return TRUE;
935 }
936
937 }
938
_MHal_PNL_GetSupportedLPLLIndex(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz,PNL_LPLL_TYPE_SEL lpll_type_sel)939 static MS_U8 _MHal_PNL_GetSupportedLPLLIndex(void *pInstance,
940 PNL_TYPE eLPLL_Type,
941 PNL_MODE eLPLL_Mode,
942 MS_U64 ldHz, PNL_LPLL_TYPE_SEL lpll_type_sel)
943 {
944 MS_U8 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
945 #if defined (__aarch64__)
946 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
947 #else
948 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu, lpll_type_sel=%u\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz, lpll_type_sel);
949 #endif
950
951 /// Mini LVDS, EPI34/28, LVDS_1CH, Vx1_1P are 1P structure
952 if(!((eLPLL_Type == E_PNL_TYPE_TTL)||
953 ((eLPLL_Type == E_PNL_TYPE_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
954 ((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(eLPLL_Mode==E_PNL_MODE_SINGLE))||
955 (eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_1LANE)||(eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_1LANE)||
956 ((eLPLL_Type >= E_PNL_LPLL_MINILVDS_2CH_3P_8BIT)&&(eLPLL_Type <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT))||
957 ((eLPLL_Type >= E_PNL_LPLL_EPI34_2P)&&(eLPLL_Type <= E_PNL_LPLL_EPI28_4P))))
958 {
959 ldHz/=2;
960 }
961
962 switch(lpll_type_sel)
963 {
964 default:
965 case E_PNL_LPLL_VIDEO:
966 {
967 switch (eLPLL_Type)
968 {
969 case E_PNL_TYPE_TTL:
970 if (ldHz < 250000000UL)
971 {
972 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to25MHz;
973 }
974 else if ((ldHz >= 250000000UL) && (ldHz < 500000000UL))
975 {
976 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_25to50MHz;
977 }
978 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
979 {
980 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_50to100MHz;
981 }
982 else
983 {
984 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_TTL_100to150MHz;
985 }
986 break;
987
988 case E_PNL_TYPE_LVDS:
989 switch (eLPLL_Mode)
990 {
991 case E_PNL_MODE_SINGLE:
992 if (ldHz < 500000000UL)
993 {
994 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz;
995 }
996 else
997 {
998 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz;
999 }
1000 break;
1001
1002 default:
1003 case E_PNL_MODE_DUAL:
1004 if (ldHz < 250000000UL)
1005 {
1006 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz;
1007 }
1008 else if ((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1009 {
1010 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz;
1011 }
1012 else
1013 {
1014 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz;
1015 }
1016 break;
1017 }
1018 break;
1019
1020 case E_PNL_TYPE_HS_LVDS:
1021
1022 switch (eLPLL_Mode)
1023 {
1024 case E_PNL_MODE_SINGLE:
1025 if(ldHz < 500000000UL)
1026 {
1027 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz;
1028 }
1029 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1030 {
1031 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz;
1032 }
1033 else
1034 {
1035 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz;
1036 }
1037 break;
1038
1039 default:
1040 case E_PNL_MODE_DUAL:
1041 if(ldHz < 250000000UL)
1042 {
1043 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz;
1044 }
1045 else if((ldHz >= 250000000UL) && (ldHz < 500000000UL))
1046 {
1047 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz;
1048 }
1049 else if((ldHz >= 500000000UL) && (ldHz < 1000000000UL))
1050 {
1051 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz;
1052 }
1053 else
1054 {
1055 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz;
1056 }
1057 break;
1058 }
1059 break;
1060 ///Not Support
1061 #if 0
1062 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
1063 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz;
1064 break;
1065
1066 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
1067 if((ldHz >= 500000000) && (ldHz < 1000000000))
1068 {
1069 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz;
1070 }
1071 else
1072 {
1073 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz;
1074 }
1075 break;
1076
1077 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
1078 if((ldHz >= 500000000) && (ldHz < 1000000000))
1079 {
1080 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz;
1081 }
1082 else
1083 {
1084 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz;
1085 }
1086 break;
1087
1088 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
1089 if((ldHz >= 500000000) && (ldHz < 666700000))
1090 {
1091 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz;
1092 }
1093 else
1094 {
1095 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz;
1096 }
1097 break;
1098
1099 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
1100 if ((ldHz <= 500000000) && (ldHz < 666700000))
1101 {
1102 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz;
1103 }
1104 else if((ldHz >= 666700000) && (ldHz < 1333300000))
1105 {
1106 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz;
1107 }
1108 else
1109 {
1110 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz;
1111 }
1112 break;
1113
1114 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
1115 if ((ldHz <= 500000000) && (ldHz < 670000000))
1116 {
1117 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz;
1118 }
1119 else if((ldHz >= 670000000) && (ldHz < 1330000000))
1120 {
1121 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz;
1122 }
1123 else
1124 {
1125 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz;
1126 }
1127 break;
1128
1129 case E_PNL_LPLL_EPI34_4P:
1130 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_95to150MHz;
1131 break;
1132
1133 case E_PNL_LPLL_EPI34_6P:
1134 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz;
1135 break;
1136
1137 case E_PNL_LPLL_EPI34_8P:
1138 if((ldHz >= 800000000) && (ldHz < 940000000))
1139 {
1140 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to94MHz;
1141 }
1142 else if((ldHz >= 940000000) && (ldHz < 1880000000))
1143 {
1144 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_94to188MHz;
1145 }
1146 else
1147 {
1148 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz;
1149 }
1150 break;
1151
1152 case E_PNL_LPLL_EPI28_4P:
1153 if((ldHz >= 800000000) && (ldHz < 1140000000))
1154 {
1155 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz;
1156 }
1157 else
1158 {
1159 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz;
1160 }
1161 break;
1162 #endif
1163
1164 case E_PNL_LPLL_EPI28_6P:
1165 if(ldHz < 1500000000UL)
1166 {
1167 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to150MHz;
1168 }
1169 else if((ldHz >= 1500000000UL) && (ldHz < 1800000000UL))
1170 {
1171 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to180MHz;
1172 }
1173 else
1174 {
1175 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_180to300MHz;
1176 }
1177 break;
1178
1179 case E_PNL_LPLL_EPI28_8P:
1180 if(ldHz < 1500000000UL)
1181 {
1182 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to150MHz;
1183 }
1184 else if((ldHz >= 1500000000UL) && (ldHz < 2400000000UL))
1185 {
1186 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to240MHz;
1187 }
1188 else
1189 {
1190 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_240to300MHz;
1191 }
1192 break;
1193
1194 case E_PNL_LPLL_EPI28_12P:
1195 if(ldHz < 1500000000UL)
1196 {
1197 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to150MHz;
1198 }
1199 else
1200 {
1201 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to300MHz;
1202 }
1203 break;
1204
1205 case E_PNL_LPLL_EPI24_12P:
1206 if(ldHz < 1500000000UL)
1207 {
1208 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to150MHz;
1209 }
1210 else
1211 {
1212 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to300MHz;
1213 }
1214 break;
1215
1216 case E_PNL_LPLL_ISP_8BIT_6P_D:
1217 if(ldHz < 1500000000UL)
1218 {
1219 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to150MHz;
1220 }
1221 else
1222 {
1223 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to300MHz;
1224 }
1225 break;
1226
1227 case E_PNL_LPLL_ISP_8BIT_12P:
1228 if(ldHz < 1500000000UL)
1229 {
1230 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz;
1231 }
1232 else
1233 {
1234 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz;
1235 }
1236 break;
1237
1238 case E_PNL_LPLL_USI_T_8BIT_12P:
1239 if(ldHz < 1500000000UL)
1240 {
1241 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to150MHz;
1242 }
1243 else
1244 {
1245 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to300MHz;
1246 }
1247 break;
1248
1249 case E_PNL_LPLL_CMPI24_10BIT_12P:
1250 if(ldHz < 1500000000UL)
1251 {
1252 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz;
1253 }
1254 else
1255 {
1256 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz;
1257 }
1258 break;
1259
1260 case E_PNL_LPLL_CMPI27_8BIT_12P:
1261 if(ldHz < 1500000000UL)
1262 {
1263 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz;
1264 }
1265 else
1266 {
1267 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz;
1268 }
1269 break;
1270
1271 case E_PNL_LPLL_VBY1_10BIT_8LANE:
1272 if(ldHz < 1500000000UL)
1273 {
1274 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz;
1275 }
1276 else
1277 {
1278 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to300MHz;
1279 }
1280 printf("@@11=%u\n",u8SupportedLPLLIndex);
1281 break;
1282
1283 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1284 if(ldHz < 750000000UL)
1285 {
1286 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz;
1287 }
1288 else
1289 {
1290 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz;
1291 }
1292 break;
1293
1294 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1295 if(ldHz < 375000000UL)
1296 {
1297 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz;
1298 }
1299 else
1300 {
1301 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz;
1302 }
1303 break;
1304
1305 case E_PNL_LPLL_VBY1_8BIT_8LANE:
1306 if(ldHz < 1500000000UL)
1307 {
1308 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz;
1309 }
1310 else if((ldHz >= 1500000000UL) && (ldHz < 2000000000UL))
1311 {
1312 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz;
1313 }
1314 else
1315 {
1316 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to300MHz;
1317 }
1318 break;
1319
1320 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1321 if(ldHz < 750000000UL)
1322 {
1323 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz;
1324 }
1325 else if((ldHz >= 750000000UL) && (ldHz < 1000000000UL))
1326 {
1327 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz;
1328 }
1329 else
1330 {
1331 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz;
1332 }
1333 break;
1334
1335 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1336 if(ldHz < 375000000UL)
1337 {
1338 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz;
1339 }
1340 else if((ldHz >= 375000000UL) && (ldHz < 500000000UL))
1341 {
1342 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz;
1343 }
1344 else
1345 {
1346 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz;
1347 }
1348 break;
1349
1350 default:
1351 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1352 break;
1353 }
1354 }
1355 break;
1356 case E_PNL_LPLL_OSD:
1357 {
1358 switch (eLPLL_Type)
1359 {
1360 case E_PNL_TYPE_HS_LVDS:
1361 {
1362 if(ldHz < 250000000)
1363 {
1364 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1ch_25to25MHz;
1365 }
1366 else if((ldHz >= 250000000) && (ldHz < 500000000))
1367 {
1368 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1ch_25to50MHz;
1369 }
1370 else if((ldHz >= 500000000) && (ldHz < 1000000000))
1371 {
1372 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1ch_50to100MHz;
1373 }
1374 else
1375 {
1376 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1ch_100to150MHz;
1377 }
1378 }
1379 break;
1380
1381 case E_PNL_LPLL_VBY1_10BIT_4LANE:
1382 if(ldHz < 1500000000)
1383 {
1384 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10bit_4lane_150to150MHz;
1385 }
1386 else
1387 {
1388 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10bit_4lane_150to340MHz;
1389 }
1390 break;
1391
1392 case E_PNL_LPLL_VBY1_10BIT_2LANE:
1393 if(ldHz < 750000000)
1394 {
1395 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10bit_2lane_75to75MHz;
1396 }
1397 else
1398 {
1399 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10bit_2lane_75to150MHz;
1400 }
1401 break;
1402
1403 case E_PNL_LPLL_VBY1_10BIT_1LANE:
1404 if(ldHz < 375000000)
1405 {
1406 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10bit_1lane_37_5to37_5MHz;
1407 }
1408 else
1409 {
1410 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_10bit_1lane_37_5to75MHz;
1411 }
1412 break;
1413
1414 case E_PNL_LPLL_VBY1_8BIT_4LANE:
1415 if(ldHz < 1500000000UL)
1416 {
1417 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_4lane_150to150MHz;
1418 }
1419 else if((ldHz >= 1500000000UL) && (ldHz < 2000000000UL))
1420 {
1421 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_4lane_150to200MHz;
1422 }
1423 else
1424 {
1425 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_4lane_200to340MHz;
1426 }
1427 break;
1428
1429 case E_PNL_LPLL_VBY1_8BIT_2LANE:
1430 if(ldHz < 750000000)
1431 {
1432 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_2lane_75to75MHz;
1433 }
1434 else if((ldHz >= 750000000) && (ldHz < 1000000000))
1435 {
1436 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_2lane_75to100MHz;
1437 }
1438 else
1439 {
1440 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_2lane_100to150MHz;
1441 }
1442 break;
1443
1444 case E_PNL_LPLL_VBY1_8BIT_1LANE:
1445 if(ldHz < 375000000)
1446 {
1447 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_1lane_37_5to37_5MHz;
1448 }
1449 else if((ldHz >= 375000000) && (ldHz < 500000000))
1450 {
1451 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_1lane_37_5to50MHz;
1452 }
1453 else
1454 {
1455 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_VBY1_8bit_1lane_50to75MHz;
1456 }
1457 break;
1458
1459 default:
1460 u8SupportedLPLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
1461 break;
1462 }
1463 }
1464 break;
1465 }
1466 return u8SupportedLPLLIndex;
1467 }
1468
_MHal_PNL_DumpLPLLTable(void * pInstance,MS_U8 LPLLTblIndex,PNL_LPLL_TYPE_SEL lpll_type_sel)1469 static void _MHal_PNL_DumpLPLLTable(void *pInstance, MS_U8 LPLLTblIndex, PNL_LPLL_TYPE_SEL lpll_type_sel)
1470 {
1471 if(lpll_type_sel == E_PNL_LPLL_VIDEO)
1472 {
1473 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_MAX)
1474 {
1475 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1476 return;
1477 }
1478
1479 int indexCounter = 0;
1480
1481 for(indexCounter = 0 ; indexCounter<LPLL_REG_NUM; indexCounter++)
1482 {
1483 if (LPLLSettingTBL[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1484 {
1485 MsOS_DelayTaskUs(LPLLSettingTBL[LPLLTblIndex][indexCounter].value);
1486 continue; // step forward to next register setting.
1487 }
1488
1489 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address),
1490 LPLLSettingTBL[LPLLTblIndex][indexCounter].value,
1491 LPLLSettingTBL[LPLLTblIndex][indexCounter].mask);
1492 }
1493 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1494 }
1495 else
1496 {
1497 if (LPLLTblIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
1498 {
1499 printf("[%s,%5d] Unspported LPLL Type, skip LPLL setting\n",__FUNCTION__,__LINE__);
1500 return;
1501 }
1502
1503 int indexCounter = 0;
1504
1505 for(indexCounter = 0 ; indexCounter<LPLL_EXT_REG_NUM; indexCounter++)
1506 {
1507 if (LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address == 0xFF) //delay in micro second
1508 {
1509 MsOS_DelayTaskUs(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value);
1510 continue; // step forward to next register setting.
1511 }
1512
1513 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address),
1514 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].value,
1515 LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].mask);
1516 }
1517 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]LPLLTblIndex=%u\n", __FUNCTION__, __LINE__, LPLLTblIndex);
1518 }
1519 }
1520
MHal_PNL_Init_LPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)1521 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
1522 {
1523 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1524 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1525 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1526 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1527 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1528 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1529
1530 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_VIDEO);
1531
1532 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1533 {
1534 printf("Not Supported LPLL Type, skip LPLL Init\n");
1535 return;
1536 }
1537
1538 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_VIDEO);
1539
1540
1541 MHal_MOD_PVDD_Power_Setting(pInstance, pPNLResourcePrivate->sthalPNL._bPVDD_2V5); // Einstein is always use 3.3V PVDD Power.
1542 }
1543
MHal_PNL_Get_Loop_DIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1544 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1545 {
1546 MS_U16 u16loop_div = 0;
1547 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1548 #if defined (__aarch64__)
1549 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1550 #else
1551 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, u8LPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, u8LPLL_Mode, ldHz);
1552 #endif
1553 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1554
1555 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1556 {
1557 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1558 u16loop_div = 0 ;
1559 }
1560 else
1561 {
1562 u16loop_div = u16LoopDiv[u8SupportedLPLLLIndex];
1563 }
1564 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_div=%u\n", u16loop_div);
1565
1566 u16loop_div *= 2;
1567 return u16loop_div;
1568 }
1569
MHal_PNL_Get_LPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)1570 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
1571 {
1572 MS_U16 u16loop_gain = 0;
1573 E_PNL_SUPPORTED_LPLL_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_MAX;
1574 #if defined (__aarch64__)
1575 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%lu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1576 #else
1577 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]E_PNL_LPLL_VIDEO : eLPLL_Type=%u, eLPLL_Mode=%u, ldHz=%llu\n", __FUNCTION__, __LINE__, eLPLL_Type, eLPLL_Mode, ldHz);
1578 #endif
1579 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_VIDEO);
1580
1581 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_MAX)
1582 {
1583 printf("[%s,%5d] Error LPLL type\n",__FUNCTION__,__LINE__);
1584 u16loop_gain = 0 ;
1585 }
1586 else
1587 {
1588 u16loop_gain = u16LoopGain[u8SupportedLPLLLIndex];
1589 }
1590 PNL_DBG(PNL_DBGLEVEL_INIT, "E_PNL_LPLL_VIDEO : u16loop_gain=%u\n", u16loop_gain);
1591 return u16loop_gain;
1592 }
1593
1594 #define SKIP_TIMING_CHANGE_CAP TRUE
Hal_PNL_SkipTimingChange_GetCaps(void * pInstance)1595 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance)
1596 {
1597 #if (SKIP_TIMING_CHANGE_CAP)
1598 return TRUE;
1599 #else
1600 return FALSE;
1601 #endif
1602 }
1603
MHal_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1604 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1605 {
1606 if (bSetMode == TRUE)
1607 {
1608 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0, BIT(15));
1609 }
1610 else
1611 {
1612 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15));
1613 }
1614 }
1615
MHal_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)1616 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo)
1617 {
1618 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1619 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1620 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1621 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1622
1623 if (lvdsresinfo.bEnable)
1624 {
1625 if (lvdsresinfo.u16channel & BIT(0)) // Channel A
1626 {
1627 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1628 {
1629 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15));
1630 }
1631 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1632 {
1633 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14));
1634 }
1635 }
1636 if (lvdsresinfo.u16channel & BIT(1)) // Channel B
1637 {
1638 if (lvdsresinfo.u32pair & BIT(3)) // pair 3
1639 {
1640 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13));
1641 }
1642 if (lvdsresinfo.u32pair & BIT(4)) // pair 4
1643 {
1644 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12));
1645 }
1646 }
1647
1648 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)
1649 &&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
1650 {
1651 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14));
1652 }
1653 }
1654 else
1655 {
1656 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12)));
1657
1658 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)
1659 &&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
1660 {
1661 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14));
1662 }
1663 }
1664 }
1665
1666 ////////////////////////////////////////////////////////////////////////
1667 // Turn OD function
1668 ////////////////////////////////////////////////////////////////////////
MHal_PNL_OverDriver_Init(void * pInstance,MS_PHY u32OD_MSB_Addr,MS_PHY u32OD_MSB_limit,MS_U32 u32OD_LSB_Addr,MS_U32 u32OD_LSB_limit,MS_U8 u8MIUSel)1669 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_U32 u32OD_LSB_Addr, MS_U32 u32OD_LSB_limit, MS_U8 u8MIUSel)
1670 {
1671 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1672 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1673 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID,REG_SC_BK16_61_L,u8MIUSel<<8,BIT(8)|BIT(9)); // OD MIU select
1674
1675 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_15_L, (MS_U16)(u32OD_MSB_Addr & 0xFFFF)); // OD MSB request base address
1676 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_16_L, (MS_U16)((u32OD_MSB_Addr >> 16) & 0x00FF), 0x00FF); // OD MSB request base address
1677 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_Addr >> 24) & 0x0003), 0x0003); // OD MSB request base address
1678 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_17_L, (MS_U16)(u32OD_MSB_limit & 0xFFFF)); // OD MSB request address limit
1679 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_18_L, (MS_U16)((u32OD_MSB_limit >> 16) & 0x00FF), 0x00FF); // OD MSB request address limit
1680 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_60_L, (MS_U16)((u32OD_MSB_limit >> 24) & 0x0003)<<2, 0x000C); // OD MSB request address limit
1681 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_39_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer write address limit
1682 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer write address limit
1683 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3B_L, (MS_U16)(u32OD_LSB_limit & 0xFFFF)); // OD frame buffer read address limit
1684 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3C_L, (MS_U16)((u32OD_LSB_limit >> 16) & 0x00FF), 0x00FF); // OD frame buffer read address limit
1685 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_4F_L, (MS_U16)(u32OD_LSB_Addr & 0xFFFF)); // OD LSB request base address
1686 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_Addr >> 16) & 0x00FF), 0x00FF); // OD LSB request base address
1687 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_50_L, (MS_U16)((u32OD_LSB_limit & 0x00FF) << 8), 0xFF00); // OD LSB request limit address
1688 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_51_L, (MS_U16)((u32OD_LSB_limit >> 8) & 0xFFFF)); // OD LSB request limit address
1689
1690 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1A_L, 0x4020); // OD request rFIFO limit threshold, priority threshold
1691 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_1C_L, 0x4020); // OD request wFIFO limit threshold, priority threshold
1692 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x00, BIT(14)); // OD strength gradually bypass
1693 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_3A_L, 0x2F00, 0x3F00); // OD strength gradually slop
1694 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_12_L, 0x0C, 0xFF); // OD active threshold
1695
1696 }
1697
MHal_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1698 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable)
1699 {
1700 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1701 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1702
1703 // OD mode
1704 // OD used user weight to output blending directly
1705 // OD Enable
1706 if (bEnable)
1707 {
1708 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2D, 0x2F);
1709 }
1710 else
1711 {
1712 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x2C, 0x2F);
1713 }
1714 }
1715
MHal_PNL_OverDriver_TBL(void * pInstance,MS_U8 u8ODTbl[1056])1716 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056])
1717 {
1718 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1719 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1720
1721 MS_U16 i;
1722 MS_U8 u8target;
1723 MS_BOOL bEnable;
1724
1725 bEnable = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, BIT(0));
1726 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, 0x00, BIT(0)); // OD enable
1727 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x0E, 0x0E); // OD table SRAM enable, RGB channel
1728
1729 u8target= u8ODTbl[9];
1730 for (i=0; i<272; i++)
1731 {
1732 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_03_L, (i == 9)?u8target:(u8target ^ u8ODTbl[i]), 0x00FF);
1733 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, (i|0x8000), 0x81FF);
1734 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_02_L, BIT(15)));
1735 }
1736
1737 u8target= u8ODTbl[(272+19)];
1738 for (i=0; i<272; i++)
1739 {
1740 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_06_L, (i == 19)?u8target:(u8target ^ u8ODTbl[(272+i)]), 0x00FF);
1741 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, (i|0x8000), 0x81FF);
1742 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_05_L, BIT(15)));
1743 }
1744
1745 u8target= u8ODTbl[(272*2+29)];
1746 for (i=0; i<256; i++)
1747 {
1748 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_09_L, (i == 29)?u8target:(u8target ^ u8ODTbl[(272*2+i)]), 0x00FF);
1749 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, (i|0x8000), 0x81FF);
1750 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_08_L, BIT(15)));
1751 }
1752
1753 u8target= u8ODTbl[(272*2+256+39)];
1754 for (i=0; i<256; i++)
1755 {
1756 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0C_L, (i == 39)?u8target:(u8target ^ u8ODTbl[(272*2+256+i)]), 0x00FF);
1757 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0B_L, (i|0x8000), 0x81FF);
1758 while(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_0D_L, BIT(15)));
1759 }
1760
1761 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_01_L, 0x00, 0x0E); // OD table SRAM enable, RGB channel
1762 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK16_10_L, bEnable, BIT(0)); // OD enable
1763 }
1764
_MHal_PNL_MOD_Swing_Refactor_AfterCAL(void * pInstance,MS_U16 u16Swing_Level)1765 MS_U16 _MHal_PNL_MOD_Swing_Refactor_AfterCAL(void *pInstance, MS_U16 u16Swing_Level)
1766 {
1767 MS_U8 u8ibcal = 0x00;
1768 MS_U16 u16AfterCal_value = 0;
1769 MS_U16 u16Cus_value = 0;
1770
1771 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1772 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1773 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1774 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1775 // =========
1776 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1777 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1778 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1779 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1780 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1781 // =========
1782 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1783 {
1784 default:
1785 case 0:
1786 u8ibcal = 0x15;
1787 break;
1788 case 1:
1789 u8ibcal = 0x1F;
1790 break;
1791 case 2:
1792 u8ibcal = 0x1A;
1793 break;
1794 case 3:
1795 u8ibcal = 0x10;
1796 break;
1797 }
1798 u16Cus_value = (u16Swing_Level) * (pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4)/(u8ibcal + 4);
1799 u16AfterCal_value = (u16Cus_value-40)/10+2;
1800
1801 HAL_MOD_CAL_DBG(printf("\r\n--Swing value after refactor = %d\n", u16AfterCal_value));
1802
1803 return u16AfterCal_value;
1804 }
1805
MHal_PNL_MODSwingRegToRealLevelValue(void * pInstance,MS_U16 u16SwingRegValue)1806 MS_U16 MHal_PNL_MODSwingRegToRealLevelValue(void *pInstance, MS_U16 u16SwingRegValue)
1807 {
1808 MS_U8 u8ibcal = 0x00;
1809 MS_U16 u16SwingRealLevelValue = 0;
1810 MS_U16 u16CusValue = 0;
1811 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1812 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1813 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1814 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1815 // =========
1816 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
1817 // 2'b00 250mV ' GCR_ICON_CHx[5:0]=2'h15 (decimal 21)
1818 // 2'b01 350mV ' GCR_ICON_CHx[5:0]=2'h1F (decimal 31)
1819 // 2'b10 300mV ' GCR_ICON_CHx[5:0]=2'h1A (decimal 26)
1820 // 2'b11 200mV ' GCR_ICON_CHx[5:0]=2'h10 (decimal 16)
1821 // =========
1822 switch(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET)
1823 {
1824 default:
1825 case 0:
1826 u8ibcal = 0x15;
1827 break;
1828 case 1:
1829 u8ibcal = 0x1F;
1830 break;
1831 case 2:
1832 u8ibcal = 0x1A;
1833 break;
1834 case 3:
1835 u8ibcal = 0x10;
1836 break;
1837 }
1838
1839 u16CusValue = ((u16SwingRegValue-2)*10)+40;
1840 u16SwingRealLevelValue=(u16CusValue*(u8ibcal + 4))/(pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE + 4);
1841
1842 HAL_MOD_CAL_DBG(printf("\r\n--Swing Real Level Value = %d\n", u16SwingRealLevelValue));
1843
1844 return u16SwingRealLevelValue;
1845 }
1846
MHal_PNL_MOD_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)1847 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level)
1848 {
1849 MS_BOOL bStatus = FALSE;
1850
1851 MS_U16 u16ValidSwing = 0;
1852 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1853 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1854 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1855 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1856
1857 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)||
1858 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS))
1859 {
1860 if(u16Swing_Level>600)
1861 u16Swing_Level=600;
1862 if(u16Swing_Level<40)
1863 u16Swing_Level=40;
1864
1865 u16ValidSwing = _MHal_PNL_MOD_Swing_Refactor_AfterCAL(pInstance, u16Swing_Level);
1866 }
1867 else
1868 {
1869 u16ValidSwing = u16Swing_Level;
1870 }
1871
1872 // Disable HW calibration keep mode first, to make SW icon value can write into register.
1873 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
1874
1875 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
1876 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
1877 {
1878 u16ValidSwing &=0x0F;
1879 // vby1 vreg
1880 // ch0+ch1+ch2+ch3
1881 MOD_A_W2BYTE(REG_MOD_A_BK00_20_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
1882 // ch4+ch5+ch6+ch7
1883 MOD_A_W2BYTE(REG_MOD_A_BK00_21_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
1884 // ch8+ch9+ch10+ch11
1885 MOD_A_W2BYTE(REG_MOD_A_BK00_22_L, (u16ValidSwing << 12 | u16ValidSwing << 8 | u16ValidSwing << 4 | u16ValidSwing));
1886 // ch12+ch13
1887 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_23_L, (u16ValidSwing << 4 | u16ValidSwing), 0x00ff);
1888 }
1889 else
1890 {
1891 u16ValidSwing &=0xFF;
1892 // LVDS fill ICON
1893 // ch0+ch1
1894 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, (u16ValidSwing << 8 | u16ValidSwing));
1895 // ch2+ch3
1896 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, (u16ValidSwing << 8 | u16ValidSwing));
1897 // ch4+ch5
1898 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, (u16ValidSwing << 8 | u16ValidSwing));
1899 // ch6+ch7
1900 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, (u16ValidSwing << 8 | u16ValidSwing));
1901 // ch8+ch9
1902 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, (u16ValidSwing << 8 | u16ValidSwing));
1903 // ch10+ch11
1904 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, (u16ValidSwing << 8 | u16ValidSwing));
1905 // ch12+ch13
1906 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, (u16ValidSwing << 8 | u16ValidSwing));
1907 }
1908 bStatus = TRUE;
1909
1910 return bStatus;
1911 }
1912
1913 ////////////////////////////////////////////////////////////////////////
1914 // Turn Pre-Emphasis Current function
1915 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_PE_Current(void * pInstance,MS_U16 u16Current_Level)1916 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level)
1917 {
1918 MS_BOOL bStatus = FALSE;
1919 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
1920
1921 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,
1922 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1923 |(u16ValidCurrent << 12 )));
1924
1925 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,
1926 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1927 |(u16ValidCurrent << 12 )));
1928
1929 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,
1930 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1931 |(u16ValidCurrent << 12 )));
1932
1933 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,
1934 ( (u16ValidCurrent ) |(u16ValidCurrent << 4 )|(u16ValidCurrent << 8 )
1935 |(u16ValidCurrent << 12 )));
1936
1937 bStatus = TRUE;
1938
1939 return bStatus;
1940 }
1941
MHal_PNL_MOD_PECurrent_Setting(void * pInstance,MS_U16 u16Current_Level,MS_U16 u16Channel_Select)1942 void MHal_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select)
1943 {
1944 MS_U16 u16ValidCurrent = u16Current_Level & 0x0F;
1945 MS_U16 u16Ch00_03_mask,u16Ch04_07_mask,u16Ch08_11_mask,u16Ch12_15_mask = 0;
1946
1947 u16Ch00_03_mask = (((u16Channel_Select & BIT(0))? 0x000F:0x00)|((u16Channel_Select & BIT(1))? 0x00F0:0x00)
1948 |((u16Channel_Select & BIT(2))? 0x0F00:0x00)|((u16Channel_Select & BIT(3))? 0xF000:0x00));
1949 u16Ch04_07_mask = (((u16Channel_Select & BIT(4))? 0x000F:0x00)|((u16Channel_Select & BIT(5))? 0x00F0:0x00)
1950 |((u16Channel_Select & BIT(6))? 0x0F00:0x00)|((u16Channel_Select & BIT(7))? 0xF000:0x00));
1951 u16Ch08_11_mask = (((u16Channel_Select & BIT(8))? 0x000F:0x00)|((u16Channel_Select & BIT(9))? 0x00F0:0x00)
1952 |((u16Channel_Select & BIT(10))? 0x0F00:0x00)|((u16Channel_Select & BIT(11))? 0xF000:0x00));
1953 u16Ch12_15_mask = (((u16Channel_Select & BIT(12))? 0x000F:0x00)|((u16Channel_Select & BIT(13))? 0x00F0:0x00)
1954 |((u16Channel_Select & BIT(14))? 0x0F00:0x00)|((u16Channel_Select & BIT(15))? 0xF000:0x00));
1955
1956 if(u16Ch00_03_mask)
1957 {
1958 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L,
1959 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch00_03_mask);
1960 }
1961 else
1962 {
1963 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x00);
1964 }
1965
1966 if(u16Ch04_07_mask)
1967 {
1968 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_19_L,
1969 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch04_07_mask);
1970 }
1971 else
1972 {
1973 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x00);
1974 }
1975
1976 if(u16Ch08_11_mask)
1977 {
1978 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1A_L,
1979 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch08_11_mask);
1980 }
1981 else
1982 {
1983 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x00);
1984 }
1985
1986 if(u16Ch12_15_mask)
1987 {
1988 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_1B_L,
1989 ((u16ValidCurrent)|(u16ValidCurrent << 4)|(u16ValidCurrent << 8)|(u16ValidCurrent << 12 )), u16Ch12_15_mask);
1990 }
1991 else
1992 {
1993 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x00);
1994 }
1995 }
1996
1997 ////////////////////////////////////////////////////////////////////////
1998 // 1.Turn TTL low-power mode function
1999 // 2.Turn internal termination function
2000 // 3.Turn DRIVER BIAS OP function
2001 ////////////////////////////////////////////////////////////////////////
MHal_PNL_MOD_Control_Out_TTL_Resistor_OP(void * pInstance,MS_BOOL bEnble)2002 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL bEnble)
2003 {
2004 MS_BOOL bStatus = FALSE;
2005 if(bEnble)
2006 {
2007 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode
2008 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x001E, 0x001E);
2009
2010 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open)
2011 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F);
2012
2013 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP
2014 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F);
2015 }
2016 else
2017 {
2018 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode
2019 // MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0x0000, 0x001E);
2020
2021 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close)
2022 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F);
2023
2024 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP
2025 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F);
2026 }
2027
2028 bStatus = TRUE;
2029 return bStatus;
2030 }
2031
MHal_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)2032 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam)
2033 {
2034 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2035 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2036 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2037 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2038 pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions = eParam;
2039 }
2040
MHal_PNL_Get_Output_MODE(void * pInstance)2041 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance)
2042 {
2043 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2044 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2045 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2046 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2047 PNL_OUTPUT_MODE eParam = pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions;
2048
2049 return eParam;
2050 }
2051
msReadEfuse(void * pInstance,MS_U8 u8Bank,MS_U32 u32Mask)2052 MS_U32 msReadEfuse(void *pInstance, MS_U8 u8Bank, MS_U32 u32Mask)
2053 {
2054 MS_U32 u32Result = 0;
2055 MS_U8 u8Count = 0;
2056
2057 W2BYTEMSK(0x2050, u8Bank<<2, BMASK(8:2)); /// reg28[8:2]Addr 6~0
2058 W2BYTEMSK(0x2050, BIT(13), BIT(13)); /// Reg28[13] Margin Read
2059 while(R2BYTEMSK(0x2050, BIT(13)) == BIT(13))
2060 {
2061 MsOS_DelayTask(1);
2062 u8Count ++;
2063
2064 if (u8Count >10)
2065 break;
2066 }
2067
2068 u32Result = (R4BYTE(0x2058)& u32Mask); /// reg2C,2D read value
2069 printf("[%s][%d]u32Result=%tx, after mask u32Result=%tx\n", __FUNCTION__, __LINE__,(ptrdiff_t) R4BYTE(0x2058), (ptrdiff_t)u32Result);
2070 return u32Result;
2071
2072 }
2073
msSetVBY1RconValue(void * pInstance)2074 void msSetVBY1RconValue(void *pInstance)
2075 {
2076 MS_U16 u16DefaultICON_Max = 40, u16DefaultICON_Min = 7;
2077 MS_U16 u16DefaultICON = 18;
2078 MS_U32 u32Mask = 0x3F;
2079 MS_BOOL bEfuseMode = FALSE;
2080 MS_U16 u16SwingOffset = 0; // by HW RD request
2081 MS_U16 u16temp = 0;
2082 if(!(_Hal_MOD_External_eFuse()))
2083 {
2084 if (msReadEfuse(pInstance, 0x4E, BIT(6)) == BIT(6))
2085 bEfuseMode = TRUE;
2086
2087
2088 // Disable HW calibration keep mode first, to make SW icon value can write into register.
2089 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0, BIT(15));
2090
2091 if (bEfuseMode)
2092 {
2093 if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) > u16DefaultICON_Max)
2094 u16temp = u16DefaultICON;
2095 else if(((MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset) < u16DefaultICON_Min)
2096 u16temp = u16DefaultICON;
2097 else
2098 u16temp = (MS_U16)msReadEfuse(pInstance, 0x4E, u32Mask) + u16SwingOffset;
2099 }
2100 else
2101 {
2102 u16temp = u16DefaultICON;
2103 }
2104
2105 //ch0~ch13 rcon setting
2106 u16temp &= (u16temp&(MS_U16)u32Mask);
2107 printf("[%s][%d]u16temp= %x\n", __FUNCTION__, __LINE__, u16temp);
2108
2109 MOD_A_W2BYTE(REG_MOD_A_BK00_10_L, (u16temp<<8|u16temp));
2110 MOD_A_W2BYTE(REG_MOD_A_BK00_11_L, (u16temp<<8|u16temp));
2111 MOD_A_W2BYTE(REG_MOD_A_BK00_12_L, (u16temp<<8|u16temp));
2112 MOD_A_W2BYTE(REG_MOD_A_BK00_13_L, (u16temp<<8|u16temp));
2113 MOD_A_W2BYTE(REG_MOD_A_BK00_14_L, (u16temp<<8|u16temp));
2114 MOD_A_W2BYTE(REG_MOD_A_BK00_15_L, (u16temp<<8|u16temp));
2115 MOD_A_W2BYTE(REG_MOD_A_BK00_16_L, (u16temp<<8|u16temp));
2116 }
2117 }
2118
MHal_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)2119 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
2120 {
2121 MS_U16 u16ValidSwing2 = 0;
2122 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2123 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2124 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2125 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2126 if( eLPLL_Type == E_PNL_TYPE_TTL)
2127 {
2128 // select pair output to be TTL
2129 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2130 MsOS_DelayTask(1);
2131 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2132 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2133 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2134
2135 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair
2136
2137 // other TTL setting
2138 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x0000); // TTL output enable
2139
2140 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0x0000);
2141 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2142 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000);
2143
2144 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x3FF, 0x3FF); // TTL skew
2145
2146 // GPO gating
2147 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating
2148 }
2149 else if(( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)||
2150 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)||
2151 ( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE))
2152 {
2153 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2
2154
2155 // rcon
2156 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE)
2157 {
2158 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
2159 MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel);
2160 }
2161 else
2162 {
2163 HAL_MOD_CAL_DBG(printf("Use RconValue\n", __FUNCTION__, __LINE__));
2164 msSetVBY1RconValue(pInstance);
2165 }
2166
2167 // rint
2168 MOD_A_W2BYTE(REG_MOD_A_BK00_32_L, 0x0000);
2169
2170 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003f);
2171
2172 //-------------------------------------
2173 //## pe
2174 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
2175 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
2176 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
2177 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
2178
2179 // VBY1 setting
2180 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0xFFFF);
2181
2182 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8F3F); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
2183 // MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2184
2185 MOD_A_W2BYTE(REG_MOD_A_BK00_40_L, 0xFFFF);
2186 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2187 MOD_A_W2BYTE(REG_MOD_A_BK00_48_L, 0xFFFF);
2188 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2189 MOD_A_W2BYTE(REG_MOD_A_BK00_42_L, 0xFFFF);
2190 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0xFFFF);
2191
2192 switch(eOutputMode)
2193 {
2194 case E_PNL_OUTPUT_NO_OUTPUT:
2195 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2196 MsOS_DelayTask(1);
2197 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2198 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2199 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2200 if(1)//( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2201 {
2202 //-------------------------------------
2203 //## icon (Swing)
2204 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
2205 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
2206
2207 //-------------------------------------
2208 //vby1
2209 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
2210 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2211 }
2212 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2213 {
2214 //-------------------------------------
2215 //## icon (Swing)
2216 MOD_A_W2BYTE(REG_MOD_A_BK00_08_L, 0x0000);
2217 MOD_A_W2BYTE(REG_MOD_A_BK00_09_L, 0x0000);
2218
2219 //vby1
2220 MOD_W2BYTE(REG_MOD_BK00_61_L, 0x8f3f);
2221 //MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xa040, 0xFDCF);
2222 }
2223 break;
2224
2225 case E_PNL_OUTPUT_CLK_ONLY:
2226 case E_PNL_OUTPUT_DATA_ONLY:
2227 case E_PNL_OUTPUT_CLK_DATA:
2228 default:
2229 if(eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
2230 {
2231 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC100);
2232 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2233 {
2234 _MHal_PNL_Auto_Set_Config(pInstance,
2235 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2236 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2237 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2238 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2239 }
2240 else
2241 {
2242 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x5555); //[15:0]reg_output_conf[15:0]
2243 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000); //[15:0]reg_output_conf[15:0]
2244 }
2245 }
2246 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
2247 {
2248 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2249 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0002); //[1]reg_dualmode[0]abswitch
2250 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2251 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x7f7f);
2252
2253 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2254 {
2255 _MHal_PNL_Auto_Set_Config(pInstance,
2256 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2257 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2258 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2259 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2260 }
2261 else
2262 {
2263 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x5500); //[15:0]reg_output_conf[15:0]
2264 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000); //[15:0]reg_output_conf[15:0]
2265 }
2266 }
2267 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
2268 {
2269 //MOD_A_W2BYTE(REG_MOD_A_BK00_3A_L, 0xC000);
2270 MOD_W2BYTE(REG_MOD_BK00_4A_L, 0x0000);
2271 MOD_A_W2BYTE(REG_MOD_A_BK00_0A_L, 0x7f7f);
2272 MOD_A_W2BYTE(REG_MOD_A_BK00_0B_L, 0x0000);
2273
2274 if( APIPNL_OUTPUT_CHANNEL_ORDER_USER == pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType )
2275 {
2276 _MHal_PNL_Auto_Set_Config(pInstance,
2277 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2278 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2279 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2280 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2281 }
2282 else
2283 {
2284 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0500);
2285 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000); //[15:0]reg_output_conf[15:0]
2286 }
2287 }
2288 break;
2289 }
2290 }
2291 //// for osd dedicated output port, 1 port for video and 1 port for osd
2292 else if((eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&
2293 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode == E_PNL_MODE_SINGLE))
2294 {
2295 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0xC01F , 0xFFFF); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2296 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path
2297 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
2298 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0xC000 , 0xF000); // enable clk_dot_mini_pre_osd & clk_dot_mini_osd
2299 }
2300 else
2301 {
2302 switch(eOutputMode)
2303 {
2304 case E_PNL_OUTPUT_NO_OUTPUT:
2305 // if MOD_45[5:0] = 0x3F && XC_MOD_EXT_DATA_EN_L = 0x0,
2306 // then if XC_MOD_OUTPUT_CONF_L = 0x0 ---> output TTL as tri-state
2307 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0020,0x0020);
2308 MsOS_DelayTask(1);
2309 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0x0000);
2310 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0000);
2311 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3B_L, 0x0000,0x0020);
2312
2313 //----------------------------------
2314 // Purpose: Set the output to be the GPO, and let it's level to Low
2315 // 1. External Enable, Pair 0~5
2316 // 2. GPIO Enable, pair 0~5
2317 // 3. GPIO Output data : All low, pair 0~5
2318 // 4. GPIO OEZ: output piar 0~5
2319 //----------------------------------
2320
2321 //1.External Enable, Pair 0~5
2322 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0FFF, 0x0FFF);
2323 //2.GPIO Enable, pair 0~5
2324 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0FFF, 0x0FFF);
2325 //3.GPIO Output data : All low, pair 0~5
2326 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0x0FFF);
2327 //4.GPIO OEZ: output piar 0~5
2328 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0x0FFF);
2329
2330 //1.External Enable, Pair 6~15
2331 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0xF000, 0xF000);
2332 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0xFFFF);
2333 //2.GPIO Enable, pair 6~15
2334 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0xF000, 0xF000);
2335 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0xFFFF);
2336 //3.GPIO Output data : All low, pair 6~15
2337 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_44_L, 0x0000, 0xF000);
2338 MOD_A_W2BYTE(REG_MOD_A_BK00_45_L, 0x0000);
2339 //4.GPIO OEZ: output piar 6~15
2340 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_42_L, 0x0000, 0xF000);
2341 MOD_A_W2BYTE(REG_MOD_A_BK00_43_L, 0x0000);
2342
2343 //1234.External Enable, Pair 16~17
2344 MOD_W2BYTE(REG_MOD_BK00_7E_L, 0xFF00);
2345
2346 //1.External Enable, Pair 18~20, 2.GPIO Enable, pair 18~20
2347 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F);
2348 //3.GPIO Output data : All low, pair 18~20
2349 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00);
2350 //4.GPIO OEZ: output piar 18~20
2351 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00);
2352 break;
2353
2354 case E_PNL_OUTPUT_CLK_ONLY:
2355 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0, 0xF000);
2356 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x4004);
2357 break;
2358
2359 case E_PNL_OUTPUT_DATA_ONLY:
2360 case E_PNL_OUTPUT_CLK_DATA:
2361 default:
2362
2363 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_48_L, 0x0000, 0xF000);
2364 MOD_A_W2BYTE(REG_MOD_A_BK00_49_L, 0x0000);
2365 //1. set GCR_PVDD_2P5=1¡¦b1; MOD PVDD power: 1: 2.5V
2366 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_39_L, 0, BIT(6));
2367 //2. set PD_IB_MOD=1¡¦b0;
2368 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x00, BIT(0));
2369 // save ch6 init value
2370 u16ValidSwing2 = (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0B_L, 0x3F00)>>8);
2371 //3. set Desired Pairs: GCR_ICON[5:0]=6h3f (current all open);
2372 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, 0x3F));
2373 //4. set Desired Pairs: GCR_PE_ADJ[2:0]=3h7 (pre-emphasis current all open )
2374 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x07);
2375
2376 //Should not execute this task while output config is enabled, otherwise it causes clk pull down for 3ms.
2377 if((MOD_A_R2BYTE(REG_MOD_A_BK00_00_L)==0x0000)&&(MOD_A_R2BYTE(REG_MOD_A_BK00_01_L)==0x0000))
2378 {
2379 //5. Enable low-power modeinternal termination Open, Enable OP
2380 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 1);
2381 }
2382 MsOS_DelayTask(1);
2383
2384 //6. Enable low-power modeinternal termination Open, Enable OP
2385 MHal_Output_LVDS_Pair_Setting(pInstance,
2386 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
2387 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
2388 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
2389 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
2390 MHal_Shift_LVDS_Pair(pInstance, pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift);
2391
2392 //7. set Desired Pairs: GCR_PE_ADJ[2:0]=3¡¦h0 (pre-emphasis current all Close)
2393 MHal_PNL_MOD_Control_Out_PE_Current (pInstance, 0x00);
2394 //8. set Desired Pairs: GCR_ICON[5:0] (current all init);
2395 MHal_PNL_MOD_Control_Out_Swing(pInstance, MHal_PNL_MODSwingRegToRealLevelValue(pInstance, u16ValidSwing2));
2396 //9. Disable low-power modeinternal termination Close, Disable OP
2397 MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (pInstance, 0);
2398
2399 // other TTL setting
2400 MOD_A_W2BYTE(REG_MOD_A_BK00_68_L, 0x003F); // LVDS output enable, [5:4] Output enable: PANEL_LVDS/ PANEL_miniLVDS/ PANEL_RSDS
2401
2402 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_40_L, 0x0000, 0xF000);
2403 MOD_A_W2BYTE(REG_MOD_A_BK00_41_L, 0x0000);
2404 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F);
2405
2406 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, 0x000, 0x3FF); // TTL skew
2407
2408 // GPO gating
2409 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating
2410
2411 break;
2412 }
2413 }
2414
2415 // MHal_PNL_Bringup(pInstance);
2416 }
2417
Mhal_PNL_Flock_LPLLSet(void * pInstance,MS_U64 ldHz)2418 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz)
2419 {
2420 UNUSED(ldHz);
2421 }
2422
MHal_PNL_MISC_Control(void * pInstance,MS_U32 u32PNL_MISC)2423 void MHal_PNL_MISC_Control(void *pInstance, MS_U32 u32PNL_MISC)
2424 {
2425 if(u32PNL_MISC & E_DRVPNL_MISC_MFC_ENABLE)
2426 {
2427 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair
2428 }
2429 }
2430
MHal_PNL_Init_XC_Clk(void * pInstance,PNL_InitData * pstPanelInitData)2431 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData)
2432 {
2433 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2434 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2435 MS_U16 u16_fifo_odclk_mask = 0;
2436 MS_U16 u16_fifo_odclk_data = 0;
2437
2438 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2439 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2440
2441 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2442
2443 // setup output dot clock
2444 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
2445 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL_DIV_2, CKG_ODCLK_MASK); // select source tobe LPLL clock
2446 else
2447 W2BYTEMSK(L_CLKGEN0(0x53), CKG_ODCLK_CLK_LPLL, CKG_ODCLK_MASK); // select source tobe LPLL clock
2448 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert
2449 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock
2450 W2BYTEMSK(L_CLKGEN0(0x53), 0xC0, 0xF0); // reg_ckg_odclk_mft
2451
2452 W2BYTE(L_CLKGEN0(0x58),0x0000); //[3:0]ckg_tx_mod
2453 W2BYTE(L_CLKGEN1(0x31), 0x0000); //[11:8]ckg_odclk_frc
2454
2455 if((pstPanelInitData->eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2456 (pstPanelInitData->eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
2457 {
2458
2459 W2BYTE(REG_CLKGEN0_57_L,0x0008); //[3:0]ckg_fifo
2460 W2BYTE(L_CLKGEN0(0x63), 0x0001); //[11:8]ckg_tx_mod_osd[4:0]osd2mod
2461 W2BYTE(REG_RVD_09_L, 0x0100); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2462 W2BYTEMSK(L_CLKGEN0(0x55), 0x00, 0xF00); //[11:8] reg_ckg_osdc
2463
2464 // merge clk (1)
2465 // 7A[3:0]:Vby1 LPLL_CLK replace by LPLL_FIFO
2466 // 1. for vby1 10 bit mode ( 4 bytes mode ), not vby1 3 bytes mode
2467 // 2. replace process start toggle
2468
2469 // merge clk (2)
2470 // 7A[7:4]:CLK_ODCLK_A clock setting
2471 // separate mod analog clk
2472 // default follow odclk_mft
2473 // be used in TTL
2474
2475 // merge clk (3)
2476 // 7A[11:8]:reg_ckg_nossc_odclk
2477 // be used in TCON
2478 u16_fifo_odclk_mask = (CKG_VBY1_VMODE_MASK | CKG_ODCLK_A_GATED | CKG_NOSSC_ODCLK_GATED);
2479 if( E_PNL_LPLL_VBY1_10BIT_8LANE == pstPanelInitData->eLPLL_Type)
2480 {
2481 u16_fifo_odclk_data = (CKG_VBY1_VMODE_LPLL_FIFO | CKG_ODCLK_A_GATED | CKG_NOSSC_ODCLK_GATED);
2482 W2BYTEMSK(REG_CKG_VBY1_VMODE, u16_fifo_odclk_data, u16_fifo_odclk_mask);
2483 }
2484 else if( E_PNL_LPLL_VBY1_10BIT_4LANE == pstPanelInitData->eLPLL_Type)
2485 {
2486 u16_fifo_odclk_data = (CKG_VBY1_VMODE_LPLL_FIFO_DIV2 | CKG_ODCLK_A_GATED | CKG_NOSSC_ODCLK_GATED);
2487 W2BYTEMSK(REG_CKG_VBY1_VMODE, u16_fifo_odclk_data, u16_fifo_odclk_mask);
2488 }
2489 else if( E_PNL_LPLL_VBY1_10BIT_2LANE == pstPanelInitData->eLPLL_Type)
2490 {
2491 u16_fifo_odclk_data = (CKG_VBY1_VMODE_LPLL_FIFO_DIV4 | CKG_ODCLK_A_GATED | CKG_NOSSC_ODCLK_GATED);
2492 W2BYTEMSK(REG_CKG_VBY1_VMODE, u16_fifo_odclk_data, u16_fifo_odclk_mask);
2493 }
2494 else
2495 {
2496 // 7A[3:0]:Vby1 LPLL_CLK replace by LPLL_FIFO, default clk from scaler
2497 u16_fifo_odclk_data = (CKG_VBY1_VMODE_LPLL_CLK | CKG_ODCLK_A_GATED | CKG_NOSSC_ODCLK_GATED);
2498 W2BYTEMSK(REG_CKG_VBY1_VMODE, u16_fifo_odclk_data, u16_fifo_odclk_mask);
2499 }
2500 }
2501 else
2502 {
2503 if(pstPanelInitData->eLPLL_Type == E_PNL_LPLL_ISP_8BIT_12P)
2504 {
2505 W2BYTE(REG_CLKGEN0_57_L,0x0008);
2506 W2BYTE(0x101EA0,0x0010);
2507 W2BYTE(L_CLKGEN0(0x7A),0x01C0);
2508 }
2509 else
2510 {
2511 W2BYTE(REG_CLKGEN0_57_L,0x0000); //[3:0]ckg_fifo
2512 }
2513
2514 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
2515 {
2516 W2BYTE(L_CLKGEN0(0x63), 0x0410); //[11:8]ckg_tx_mod_osd[4:0]osd2mod
2517 W2BYTE(REG_RVD_09_L, 0x1000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo+
2518 }
2519 else
2520 {
2521 W2BYTE(L_CLKGEN0(0x63),0x0001); //[11:8]ckg_tx_mod [3:0]ckg_osd2mod
2522 W2BYTE(REG_RVD_09_L, 0x0000); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
2523 }
2524 }
2525 }
2526
MHal_PNL_Init_MOD(void * pInstance,PNL_InitData * pstPanelInitData)2527 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData)
2528 {
2529 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2530 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2531 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2532 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2533
2534 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2535
2536 //------------------------------------------------------------------------
2537
2538 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL0 = %x\n", pstPanelInitData->u16MOD_CTRL0);
2539 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRL9 = %x\n", pstPanelInitData->u16MOD_CTRL9);
2540 PNL_DBG(PNL_DBGLEVEL_INIT, "u16MOD_CTRLA = %x\n", pstPanelInitData->u16MOD_CTRLA);
2541 PNL_DBG(PNL_DBGLEVEL_INIT, "u8MOD_CTRLB = %x\n", pstPanelInitData->u8MOD_CTRLB);
2542
2543 //-------------------------------------------------------------------------
2544 // Set MOD registers
2545 //-------------------------------------------------------------------------
2546
2547 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK);
2548
2549 // GPIO is controlled in drvPadConf.c
2550 // MDrv_Write2Byte(L_BK_MOD(0x46), 0x0000); //EXT GPO disable
2551 // MDrv_Write2Byte(L_BK_MOD(0x47), 0x0000); //EXT GPO disable
2552 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2553 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
2554 {
2555 ///u16MOD_CTRL9 [6] : 62[9]reg_vby1_pair_swap
2556 ///u16MOD_CTRL9 [12:11] : 62[5:4]reg_vby1_pair_mirror
2557 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xA000, 0xFD8F); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_vby1[9]swap
2558
2559 // SC4 reg62[6]reg_vby1_4ch:enable 4ch vx1mode
2560 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
2561 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1
2562 else
2563 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1
2564
2565 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9));
2566 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|BIT(4));
2567
2568 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2569 {
2570 if(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
2571 {
2572 // 2 divison just be supported in monet vby1 8 lane
2573 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2574 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode
2575
2576 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value
2577 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize
2578 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len
2579 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage
2580 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask
2581 }
2582 else
2583 {
2584 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode
2585 }
2586 }
2587 else
2588 {
2589 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2590 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_1LANE)||
2591 (pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_1LANE))
2592 {
2593 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007);
2594 }
2595 else
2596 {
2597 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);
2598 }
2599
2600 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask
2601 }
2602
2603
2604
2605
2606 ///u16MOD_CTRL9 [7] : 63[13]reg_vby1_pair_swap_osd
2607 ///u16MOD_CTRL9 [14:13] : 63[11:10]reg_vby1_pair_mirror2
2608 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13));
2609 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|BIT(10));
2610
2611 if((pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)||(pstPanelInitData->eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
2612 {
2613 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1
2614
2615 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
2616 {
2617 // 2 Divisoin
2618 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2
2619 }
2620 else
2621 {
2622 // 1 Division
2623 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2
2624 }
2625 }
2626 else //if ///E_PNL_LPLL_VBY1_10BIT_4LANE, E_PNL_LPLL_VBY1_10BIT_2LANE
2627 {
2628 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x0000, BIT(12)); // [12] enable 8ch vx1 mode : 0
2629 }
2630
2631 MHal_Output_Channel_Order(pInstance,
2632 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2633 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2634 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2635 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2636 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2637
2638
2639 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
2640 {
2641 printf("\n[%s][%d]Vx1 2 division\n", __FUNCTION__, __LINE__);
2642 }
2643 else
2644 {
2645 printf("\n[%s][%d]Vx1 1 division\n", __FUNCTION__, __LINE__);
2646 }
2647
2648 ////per RD's suggestion ---Start
2649 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, 0x3FFF, 0x3FFF); //reg_gcr_pe_en_ch
2650 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, 0x0000, 0x3FFF); //reg_gcr_en_rint_ch
2651 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3C_L, 0x0FFF, 0x3FFF); //reg_gcr_test_ch
2652
2653 /// reg_gcr_pe_adj ch0~ch13
2654 MOD_A_W2BYTE(REG_MOD_A_BK00_18_L,0x2222);
2655 MOD_A_W2BYTE(REG_MOD_A_BK00_19_L,0x2222);
2656 MOD_A_W2BYTE(REG_MOD_A_BK00_1A_L,0x2222);
2657 MOD_A_W2BYTE(REG_MOD_A_BK00_1B_L,0x2222);
2658
2659 // [0] reg_vby1_8v4o_mode, [3]reg_vby1_ext_ptr_en
2660 // [4] reg_vby1_8vlo_mode: vby1 8 video + hslvds osd mode
2661 // [5] reg_vby1_proc_auto_fix: vby1 hw auto gen proc_st trig
2662 // [6] reg_vby1_ext_fsm_en: config each vby1 set use same FSM state (split video/osd path)
2663 // [7] reg_vby1_hw_lock: set Vby1 lock sequence by HW mode
2664 // [8] reg_vby1_fifo_rptr_align: When toggle proc_st, Rptr run to Byte mode boundary, then jump to ini value.
2665 // [15] reg_vby1_disparity_mode
2666 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(3), BIT(0)|BIT(3));
2667 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, (BIT(5)|BIT(6)|BIT(7)), (BIT(4)|BIT(5)|BIT(6)|BIT(7)) );
2668 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x0000, BIT(8) );
2669 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, BIT(15), BIT(15));
2670
2671 //The threshold value be set too strict ( ori: MOD_5C =0x0 )
2672 //And this reg should be set before enable serializer function
2673 //[15]reg_sw_rptr_fix_en: pointer fix by sw mode enable
2674 //[14:12]reg_sw_wptr_check: sw mode to decision write point check point
2675 //[10:8]reg_sw_rptr_fix_ini: sw mode to decision read point initial value
2676 //[6:4]reg_sw_rptr_fix_hi_th: sw mode to decision read pointer hi boundary
2677 //[2:0]reg_sw_rptr_fix_lo_th: sw mode to decision read pointer low boundary
2678 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF);
2679 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF);
2680
2681 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
2682 //[1]enable serializer auto fix read/write point mis-balance
2683 //[2]enable osd serializer auto fix read/write point mis-balance
2684 //[7]for OSD, switch chanel 8~13 as OSD path
2685 }
2686 else
2687 {
2688 if((pstPanelInitData->eLPLL_Type == E_PNL_TYPE_LVDS)&&(pstPanelInitData->eLPLL_Mode == E_PNL_MODE_SINGLE))
2689 {
2690 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007);//[2:0]reg_mft_mode, 2p to 1p mode
2691 }
2692 else
2693 {
2694 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode
2695 }
2696
2697 MOD_W2BYTE(REG_MOD_BK00_49_L, pstPanelInitData->u16MOD_CTRL9); //{L_BK_MOD(0x49), 0x00}, // [7,6] : output formate selction 10: 8bit, 01: 6bit :other 10bit, bit shift
2698 MHal_Output_Channel_Order(pInstance,
2699 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2700 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2701 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2702 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2703 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2704 }
2705
2706 MOD_W2BYTE(REG_MOD_BK00_4A_L, pstPanelInitData->u16MOD_CTRLA);
2707 MOD_W2BYTE(REG_MOD_BK00_4B_L, pstPanelInitData->u8MOD_CTRLB); //[1:0]ti_bitmode 10:8bit 11:6bit 0x:10bit
2708
2709 //dual port lvds _start_//
2710 // output configure for 26 pair output 00: TTL, 01: LVDS/RSDS/mini-LVDS data differential pair, 10: mini-LVDS clock output, 11: RSDS clock output
2711 _MHal_PNL_Set_Clk(pInstance,
2712 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u8OutputOrderType,
2713 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder0_3,
2714 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder4_7,
2715 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder8_11,
2716 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputOrder12_13);
2717 //dual port lvds _end_//
2718
2719 //MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, (_u8PnlDiffSwingLevel << 1), 0xFE); //differential output swing level
2720 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2721 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
2722 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_3A_L, 0x0000, 0xF000); //bank selection for skew clock
2723
2724 //if(!MHal_PNL_MOD_Control_Out_Swing(_u8PnlDiffSwingLevel))
2725 // printf(">>Swing Level setting error!!\n");
2726 if(pstPanelInitData->eLPLL_Type != E_PNL_TYPE_MINILVDS)
2727 {
2728 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07);
2729 }
2730
2731 //// Patch for Vx1 and it should be control by panel ini
2732 if(((pstPanelInitData->eLPLL_Type_Ext>= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
2733 (pstPanelInitData->eLPLL_Type_Ext<= E_PNL_LPLL_VBY1_8BIT_8LANE)))
2734 {
2735 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, 0x0FFF, 0x3FFF);
2736 }
2737 else
2738 {
2739 MOD_A_W2BYTE(REG_MOD_A_BK00_31_L, pstPanelInitData->u16LVDSTxSwapValue);
2740 }
2741
2742
2743 // TODO: move from MDrv_Scaler_Init(), need to double check!
2744 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0));
2745
2746
2747 //--------------------------------------------------------------
2748 //Depend On Bitmode to set Dither
2749 //--------------------------------------------------------------
2750
2751
2752 // always enable noise dither and disable TAILCUT
2753 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, ((pstPanelInitData->u8PanelNoiseDith ? XC_PAFRC_DITH_NOISEDITH_EN : (1 - XC_PAFRC_DITH_NOISEDITH_EN)) <<3) , BIT(3));
2754 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, XC_PAFRC_DITH_TAILCUT_DISABLE, BIT(4));
2755
2756 switch(pstPanelInitData->u8MOD_CTRLB & 0x03)//[1:0]ti_bitmode b'10:8bit 11:6bit 0x:10bit
2757 {
2758 case HAL_TI_6BIT_MODE:
2759 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
2760 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(2), BIT(2));
2761 break;
2762
2763 case HAL_TI_8BIT_MODE:
2764 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, BIT(0), BIT(0));
2765 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
2766 break;
2767
2768 case HAL_TI_10BIT_MODE:
2769 default:
2770 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(0));
2771 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_3F_L, 0x00, BIT(2));
2772 break;
2773 }
2774
2775
2776 //-----depend on bitmode to set Dither------------------------------
2777 MHal_PNL_SetOutputType(pInstance, pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type); // TTL to Ursa
2778 //MHal_PNL_Bringup(pInstance);
2779
2780 MHal_PNL_MISC_Control(pInstance, pstPanelInitData->u32PNL_MISC);
2781
2782 PNL_DBG(PNL_DBGLEVEL_INIT, "OutputType = %x, eLPLL_Type = %x\n", pPNLResourcePrivate->sthalPNL._eDrvPnlInitOptions, pstPanelInitData->eLPLL_Type);
2783 PNL_DBG(PNL_DBGLEVEL_INIT, "u32PNL_MISC = %tx\n", (ptrdiff_t)pstPanelInitData->u32PNL_MISC);
2784
2785 }
2786
MHal_PNL_DumpMODReg(void * pInstance,MS_U32 u32Addr,MS_U16 u16Value,MS_BOOL bHiByte,MS_U16 u16Mask)2787 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask)
2788 {
2789 if (bHiByte)
2790 {
2791 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
2792 }
2793 else
2794 {
2795 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask);
2796 }
2797 }
2798
MHal_MOD_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)2799 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
2800 {
2801 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2802 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2803 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2804 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2805 // Setup the default swing level
2806 pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel = pstModCaliInitData->u16ExpectSwingLevel; //mv
2807 #if 0
2808 // Pair setting
2809 // =========
2810 // Select calibration source pair, 00: ch2, 01: ch6, 10:ch8, 11:ch12
2811 //MOD_7D_L[3:2]
2812 // =========
2813 //in msModCurrentCalibration, it will transfer to the real data
2814
2815 switch(pstModCaliInitData->u8ModCaliPairSel)
2816 {
2817 default:
2818 case 0:
2819 //ch 2
2820 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x00; // ch2
2821 break;
2822 case 1:
2823 //ch 6
2824 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x01; // ch6, calibration initialized value
2825 break;
2826 case 2:
2827 //ch 8
2828 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x02;
2829 break;
2830 case 3:
2831 //ch 12
2832 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_PAIR_SEL = 0x03;
2833 break;
2834 }
2835 #endif
2836 // Target setting
2837 // =========
2838 // GCR_CAL_LEVEL[1:0] : REG_MOD_A_BK00_70_L =>
2839 // =========
2840 //in msModCurrentCalibration, it will transfer to the real data
2841 switch(pstModCaliInitData->u8ModCaliTarget)
2842 {
2843 default:
2844 case 0:
2845 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 0;
2846 break;
2847 case 1:
2848 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 1;
2849 break;
2850 case 2:
2851 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 2;
2852 break;
2853 case 3:
2854 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET = 3;
2855 break;
2856 }
2857 // Offset setting, for fine tune
2858 //_usMOD_CALI_OFFSET = pstModCaliInitData->s8ModCaliOffset;
2859 // _u8MOD_CALI_VALUE is a real value; the _u8MOD_CALI_VALUE is an idea value
2860 // Target value should be the same with _u8MOD_CALI_VALUE to be a default value
2861 pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE= pstModCaliInitData->u8ModCaliTarget;
2862 // PVDD setting
2863 pPNLResourcePrivate->sthalPNL._bPVDD_2V5 = pstModCaliInitData->bPVDD_2V5;
2864
2865 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2866 PNL_DBG(PNL_DBGLEVEL_INIT, "u16ExpectSwingLevel = %u\n", pstModCaliInitData->u16ExpectSwingLevel);
2867 PNL_DBG(PNL_DBGLEVEL_INIT, "u8ModCaliTarget = %x\n", pstModCaliInitData->u8ModCaliTarget);
2868 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_TARGET = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET);
2869 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_CALI_VALUE = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_CALI_VALUE);
2870 PNL_DBG(PNL_DBGLEVEL_INIT, "bPVDD_2V5 = %x\n", pstModCaliInitData->bPVDD_2V5);
2871
2872 }
2873
MHal_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)2874 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type)
2875 {
2876 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2877 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2878 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2879 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2880 if(Type == LVDS_DUAL_OUTPUT_SPECIAL )
2881 {
2882 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Shift = LVDS_DUAL_OUTPUT_SPECIAL;
2883 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = 1;
2884 }
2885 else
2886 {
2887 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type = Type;
2888 }
2889 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
2890 PNL_DBG(PNL_DBGLEVEL_INIT, "_u8MOD_LVDS_Pair_Type = %u\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
2891
2892 }
2893
msModCalDDAOUT(void)2894 MS_BOOL msModCalDDAOUT(void)
2895 {
2896 // W2BYTEMSK(BK_MOD(0x7D), ENABLE, 8:8);
2897 // MsOS_DelayTask(10); //10ms
2898 return (MS_BOOL)((MOD_R2BYTEMSK(REG_MOD_A_BK00_74_L, BIT(8))) >> 8);
2899 }
2900
msModCurrentCalibration(void * pInstance)2901 MS_U8 msModCurrentCalibration(void *pInstance)
2902 {
2903 #if MOD_CAL_TIMER
2904 MS_U32 delay_start_time;
2905 delay_start_time=MsOS_GetSystemTime();
2906 #endif
2907
2908 #if (!ENABLE_Auto_ModCurrentCalibration)
2909 return 0x60;
2910 #else
2911 MS_U8 u8cur_ibcal=0;
2912 MS_U16 u16reg_32da = 0, u16reg_32dc = 0;
2913 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
2914 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
2915 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
2916 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
2917 u16reg_32da = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
2918 u16reg_32dc = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
2919
2920 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s][%d]\n", __FUNCTION__, __LINE__);
2921
2922 // (1) Set keep mode to auto write calibration result into register.
2923 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, BIT(15), BIT(15));
2924
2925 // (2) Set calibration step waiting time
2926 MOD_A_W2BYTE(REG_MOD_A_BK00_71_L, 0x0080); // (about 5us)
2927 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, 0x00FF);
2928
2929 // (3) Set calibration toggle time
2930 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0500, 0x0F00);
2931
2932 // (4) Select calibration level (LVDS is 250mV)
2933 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(1)|BIT(0)); // Select calibration target voltage, 00: 250mV, 01:350mV, 10: 300mV, 11: 200mV
2934
2935 // (5) Enable Calibration mode
2936 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, BIT(7), BIT(7)); // Enable calibration function
2937
2938 // (6) Store output configuration value and Enable each pair test mode
2939 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, 0xFFFF);
2940 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0FFF);
2941
2942 MS_U8 u8CheckTimes = 0;
2943 while(1)
2944 {
2945 // (7) Enable Hardware calibration
2946 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, BIT(15), BIT(15));
2947
2948 // (8) Wait 2ms
2949 MsOS_DelayTask(2);
2950
2951 // (10) Disable Hardware calibration
2952 MOD_W2BYTEMSK(REG_MOD_BK00_3D_L, 0x00, BIT(15));
2953
2954 // (9)Check Finish and Fail flag bit
2955 //BK1032, 0x3D[14], Finish flag=1
2956 //BK1032, 0x3D[13], Fail flag=0
2957 if (MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000) == 0x4000)
2958 {
2959 //printf("\033[0;31m [%s][%d] cal ok, break \033[0m\n", __FUNCTION__, __LINE__);
2960 MS_U16 u16ICONtempCH0_1 = 0;
2961 MS_U16 u16ICONtempCH2_3 = 0;
2962 MS_U16 u16ICONtempCH4_5 = 0;
2963 MS_U16 u16ICONtempCH6_7 = 0;
2964 MS_U16 u16ICONtempCH8_9 = 0;
2965 MS_U16 u16ICONtempCH10_11 = 0;
2966 MS_U16 u16ICONtempCH12_13 = 0;
2967
2968 u16ICONtempCH0_1 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_08_L, 0xFFFF) );
2969 u16ICONtempCH2_3 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_09_L, 0xFFFF) );
2970 u16ICONtempCH4_5 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0A_L, 0xFFFF) );
2971 u16ICONtempCH6_7 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0B_L, 0xFFFF) );
2972 u16ICONtempCH8_9 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0C_L, 0xFFFF) );
2973 u16ICONtempCH10_11 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0D_L, 0xFFFF) );
2974 u16ICONtempCH12_13 = _Hal_MOD_Refine_ICON( MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0E_L, 0xFFFF) );
2975
2976 //close reg_keep_cal_value
2977 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x0000, BIT(15));
2978
2979 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, u16ICONtempCH0_1, 0xFFFF);
2980 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_09_L, u16ICONtempCH2_3, 0xFFFF);
2981 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0A_L, u16ICONtempCH4_5, 0xFFFF);
2982 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0B_L, u16ICONtempCH6_7, 0xFFFF);
2983 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0C_L, u16ICONtempCH8_9, 0xFFFF);
2984 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0D_L, u16ICONtempCH10_11, 0xFFFF);
2985 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0E_L, u16ICONtempCH12_13, 0xFFFF);
2986
2987 break;
2988 }
2989 else
2990 {
2991 u8CheckTimes ++;
2992 //printf("\033[0;31m [%s][%d] cal ng, u8CheckTimes: %d \033[0m\n", __FUNCTION__, __LINE__, u8CheckTimes);
2993 }
2994
2995 if (u8CheckTimes > MOD_LVDS_HW_CALI_TIME_OUT)
2996 {
2997 // (13) If 3 times all fail, set all pair to nominal value by disable keep mode
2998 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_72_L, 0x00, BIT(15));
2999
3000 MS_U16 u16ICONtempDefault = ( (MOD_LVDS_ICON_DEFAULT<<8) | (MOD_LVDS_ICON_DEFAULT) );
3001 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, u16ICONtempDefault, 0xFFFF);
3002 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_09_L, u16ICONtempDefault, 0xFFFF);
3003 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0A_L, u16ICONtempDefault, 0xFFFF);
3004 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0B_L, u16ICONtempDefault, 0xFFFF);
3005 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0C_L, u16ICONtempDefault, 0xFFFF);
3006 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0D_L, u16ICONtempDefault, 0xFFFF);
3007 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0E_L, u16ICONtempDefault, 0xFFFF);
3008 //printf("\033[0;31m [%s][%d] If 3 times all fail, set all pair to nominal value by disable keep mode \033[0m\n", __FUNCTION__, __LINE__);
3009 break;
3010 }
3011 }
3012
3013 if (u8CheckTimes <=MOD_LVDS_HW_CALI_TIME_OUT)
3014 {
3015 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration ok \n");
3016 }
3017 else
3018 {
3019 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n----- Calibration fail: 0x%x \n", MOD_R2BYTEMSK(REG_MOD_BK00_3D_L, 0x6000));
3020 }
3021
3022 // Wait 2ms to make sure HW auto write calibration result into register
3023 MsOS_DelayTask(2);
3024
3025 // (14) Restore each pair output configuration
3026 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16reg_32da);
3027 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16reg_32dc);
3028
3029 // (15) Disable calibration mode
3030 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Disable calibration function
3031
3032 // With HW calibration mode, HW would cal for each channel, and each channel would get different value
3033 // Return channel 2 vaule
3034 u8cur_ibcal = MOD_A_R2BYTEMSK(REG_MOD_A_BK00_09_L, 0x007F); // return ch2 calibration result
3035
3036 #if MOD_CAL_TIMER
3037 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "[%s] takes %ld ms\n", __FUNCTION__, (MsOS_GetSystemTime()-delay_start_time));
3038 #endif
3039 PNL_DBG(PNL_DBGLEVEL_CALIBRATION, "\r\n Calibration result= %x\n", u8cur_ibcal);
3040
3041 return (u8cur_ibcal&0x7F);//MOD_A_R2BYTEMSK(REG_MOD_A_BK00_0D_L, 0x003F);
3042 #endif
3043 }
3044
MHal_PNL_MOD_Calibration(void * pInstance)3045 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance)
3046 {
3047 MS_U8 u8Cab;
3048 MS_U8 u8BackUSBPwrStatus;
3049 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3050 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3051 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3052 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3053
3054 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
3055
3056 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
3057
3058 u8Cab = msModCurrentCalibration(pInstance);
3059
3060 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
3061
3062 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type !=E_PNL_TYPE_MINILVDS)
3063 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07);
3064
3065 return E_PNL_OK;
3066
3067 }
3068
MHal_PNL_PowerDownLPLL(void * pInstance,MS_BOOL bEnable)3069 static void MHal_PNL_PowerDownLPLL(void *pInstance, MS_BOOL bEnable)
3070 {
3071 if(bEnable)
3072 {
3073 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5));
3074 }
3075 else
3076 {
3077 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5));
3078 }
3079 }
3080
MHal_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)3081 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn)
3082 {
3083 MS_U8 u8Cab;
3084 MS_U8 u8BackUSBPwrStatus;
3085 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3086 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3087 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3088 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3089
3090 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "[%s][%d]\n", __FUNCTION__, __LINE__);
3091
3092 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u32PNL_MISC = %tx\n", (ptrdiff_t)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC);
3093 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "bPanelOn = %x\n", bPanelOn);
3094 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "eLPLL_Type = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type);
3095 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "_u8MOD_LVDS_Pair_Type = %x\n", pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type);
3096 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
3097 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
3098 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3099
3100 MS_U16 u16PortA = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3101 MS_U16 u16PortB = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3102
3103 if(u16PortA!=0)
3104 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7 = MOD_A_R2BYTE(REG_MOD_A_BK00_00_L);
3105 if(u16PortB!=0)
3106 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15 = MOD_A_R2BYTE(REG_MOD_A_BK00_01_L);
3107
3108 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "==========================\n\n");
3109 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG0_7 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7);
3110 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG8_15 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15);
3111 PNL_DBG(PNL_DBGLEVEL_PANEL_EN, "u16OutputCFG16_21 = %x\n", pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3112
3113
3114 if(bPanelOn)
3115 {
3116 // The order is PanelVCC -> delay pnlGetOnTiming1() -> VOP -> MOD
3117 // VOP
3118 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x4000, HBMASK);
3119
3120 // For Napoli compatible
3121 // need to wait 1ms to wait LDO stable before MOD power on
3122 MsOS_DelayTask(1);
3123
3124 // turn on LPLL
3125 MHal_PNL_PowerDownLPLL(pInstance, FALSE);
3126
3127 // mod power on
3128 MHal_MOD_PowerOn(pInstance
3129 , ENABLE
3130 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
3131 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
3132 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
3133 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
3134 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3135
3136 if(bCalEn)
3137 {
3138
3139 u8BackUSBPwrStatus = R2BYTEMSK(L_BK_UTMI1(0x04), BIT(7));
3140
3141 W2BYTEMSK(L_BK_UTMI1(0x04), 0x00, BIT(7));
3142
3143 u8Cab = msModCurrentCalibration(pInstance);
3144
3145 W2BYTEMSK(L_BK_UTMI1(0x04), u8BackUSBPwrStatus, BIT(7));
3146
3147 }
3148 else
3149 {
3150 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type>=E_PNL_LPLL_VBY1_10BIT_4LANE)&&
3151 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type<=E_PNL_LPLL_VBY1_8BIT_8LANE) &&
3152 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC & (MS_U32)E_APIPNL_MISC_SKIP_ICONVALUE) == FALSE))
3153 {
3154 HAL_MOD_CAL_DBG(printf("Use RCON value \n", __FUNCTION__, __LINE__));
3155 msSetVBY1RconValue(pInstance);
3156 }
3157 else
3158 {
3159 HAL_MOD_CAL_DBG(printf("User define Swing Value=%u\n", __FUNCTION__, __LINE__, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel));
3160
3161 if(!MHal_PNL_MOD_Control_Out_Swing(pInstance, pPNLResourcePrivate->sthalPNL._u16PnlDefault_SwingLevel))
3162 printf(">>Swing Level setting error!!\n");
3163 }
3164 }
3165
3166 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
3167 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE, ENABLE);
3168 }
3169 else
3170 {
3171 // The order is LPLL -> MOD -> VOP -> delay for MOD power off -> turn off VCC
3172
3173 // LPLL
3174 // MHal_PNL_PowerDownLPLL(TRUE); //Remove to keep op vsync if panel off
3175
3176 MHal_MOD_PowerOn(pInstance
3177 , DISABLE
3178 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type
3179 , pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type
3180 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7
3181 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15
3182 , pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3183 // VOP
3184 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS ||
3185 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_I ||
3186 pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_DAC_P)//(bIsLVDS)
3187 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0xFF, LBMASK);
3188 else
3189 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, 0x00, 0xFF);
3190 }
3191
3192 return E_PNL_OK;
3193 }
3194
MHal_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)3195 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
3196 {
3197 if (bEnable)
3198 {
3199 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF);
3200 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF);
3201 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF);
3202 MsOS_DelayTask(10);
3203 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15));
3204 }
3205 else
3206 {
3207 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15));
3208 }
3209
3210 }
3211
MHal_PNL_Switch_LPLL_SubBank(void * pInstance,MS_U16 u16Bank)3212 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank)
3213 {
3214 UNUSED(u16Bank);
3215 }
3216
MHal_PNL_Switch_TCON_SubBank(void * pInstance,MS_U16 u16Bank)3217 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank)
3218 {
3219 W2BYTEMSK(L_BK_TCON(0x00), u16Bank&0xff, 0xFF);
3220 }
3221
MHal_PNL_Read_TCON_SubBank(void * pInstance)3222 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance)
3223 {
3224 return (MS_U16)R2BYTEMSK(L_BK_TCON(0x00),0xFF);
3225 }
3226
MHal_PNL_Is_VBY1_Locked(void * pInstance)3227 MS_BOOL MHal_PNL_Is_VBY1_Locked(void *pInstance)
3228 {
3229 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0300) == 0x00)
3230 {
3231 return TRUE;
3232 }
3233 else
3234 {
3235 return FALSE;
3236 }
3237 }
3238
MHal_PNL_Is_VBY1_LockN_Locked(void * pInstance)3239 MS_BOOL MHal_PNL_Is_VBY1_LockN_Locked(void *pInstance)
3240 {
3241 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0100) == 0x00)
3242 {
3243 return TRUE;
3244 }
3245 else
3246 {
3247 return FALSE;
3248 }
3249 }
3250
MHal_PNL_VBY1_Handshake(void * pInstance)3251 MS_BOOL MHal_PNL_VBY1_Handshake(void *pInstance)
3252 {
3253 MS_BOOL bIsLock = FALSE;
3254
3255 if (MHal_PNL_Is_VBY1_Locked(pInstance) == FALSE)
3256 {
3257 MS_U16 u16CheckTimes = 0;
3258 //MS_U16 u16DeboundTimes = 0;
3259
3260 // need to toggle vby1 packer process start first
3261 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11));
3262 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11));
3263
3264 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0F56); // set reg. initial value
3265 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by
3266 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition
3267 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
3268 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance
3269
3270 while(u16CheckTimes < 10)
3271 {
3272 #if 0
3273 u16DeboundTimes = 2;
3274 while ((!MHal_PNL_Is_VBY1_LockN_Locked()) && (u16DeboundTimes --))
3275 {
3276 MsOS_DelayTask(1); // can't remove
3277 }
3278 #endif
3279 if(MHal_PNL_Is_VBY1_LockN_Locked(pInstance))
3280 {
3281 //-------------------------------------------------------------------
3282 // step1. Toggle clock when training
3283 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
3284 //--------------------------------------------------------------------
3285 bIsLock = TRUE;
3286 // pass 2 times debound to make sure VBY1 is locked
3287 break;
3288 }
3289
3290 u16CheckTimes++;
3291 MsOS_DelayTaskUs(40);
3292 }
3293
3294 if(bIsLock)
3295 {
3296 // step3. Disable HW check when lock done, Enable when loss lock
3297 //MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
3298
3299 /// Add the delay to increase time to send
3300 //MDrv_TIMER_Delayms(10);
3301 }
3302 }
3303 else
3304 {
3305 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0x0FAE)
3306 {
3307 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0FAE);
3308 }
3309 bIsLock = TRUE;
3310 }
3311
3312 return bIsLock;
3313 }
3314
MHal_PNL_Is_VBY1_OC_Locked(void * pInstance)3315 MS_BOOL MHal_PNL_Is_VBY1_OC_Locked(void *pInstance)
3316 {
3317 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0C00) == 0x00) // MOD_BK00_56_L[11:10] for OSD
3318 {
3319 return TRUE;
3320 }
3321 else
3322 {
3323 return FALSE;
3324 }
3325 }
3326
MHal_PNL_Is_VBY1_OC_LockN_Locked(void * pInstance)3327 MS_BOOL MHal_PNL_Is_VBY1_OC_LockN_Locked(void *pInstance)
3328 {
3329 if (MOD_A_R2BYTEMSK(REG_MOD_A_BK00_47_L, 0x0400) == 0x00) // MOD_BK00_56_L[11:10] for OSD
3330 {
3331 return TRUE;
3332 }
3333 else
3334 {
3335 return FALSE;
3336 }
3337 }
3338
MHal_PNL_VBY1_OC_Handshake(void * pInstance)3339 MS_BOOL MHal_PNL_VBY1_OC_Handshake(void *pInstance)
3340 {
3341 MS_BOOL bIsLock = FALSE;
3342
3343 if (MHal_PNL_Is_VBY1_OC_Locked(pInstance) == FALSE)
3344 {
3345 MS_U16 u16CheckTimes = 0;
3346 // MS_U16 u16DeboundTimes = 0;
3347
3348 // need to toggle vby1 packer process start first
3349 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11));
3350 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11));
3351
3352
3353 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0F56); // set reg. initial value
3354 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by
3355 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition
3356 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR training
3357 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance
3358
3359 while(u16CheckTimes < 10)
3360 {
3361 #if 0
3362 u16DeboundTimes = 2;
3363 while ((!MHal_PNL_Is_VBY1_OC_LockN_Locked()) && (u16DeboundTimes --))
3364 {
3365 MsOS_DelayTask(1);
3366 }
3367 #endif
3368 if(MHal_PNL_Is_VBY1_OC_LockN_Locked(pInstance))
3369 {
3370 //-------------------------------------------------------------------
3371 // step1. Toggle clock when training
3372
3373 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
3374 bIsLock = TRUE;
3375 // pass 2 times debound to make sure VBY1 is locked
3376 break;
3377 }
3378
3379 u16CheckTimes++;
3380 MsOS_DelayTaskUs(40);
3381 }
3382
3383 if(bIsLock)
3384 {
3385 // step3. Disable HW check when lock done, Enable when loss lock
3386 // MOD_W2BYTEMSK(REG_MOD_BK00_33_L, 0x00, BIT15);
3387 }
3388 }
3389 else
3390 {
3391 if(MOD_R2BYTEMSK(REG_MOD_BK00_64_L, 0x0FFF) != 0x0FAE)
3392 {
3393 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0FAE);
3394 }
3395 bIsLock = TRUE;
3396 }
3397
3398 return bIsLock;
3399 }
3400
MHal_PNL_IsYUVOutput(void * pInstance)3401 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance)
3402 {
3403 return FALSE;
3404 }
3405
MHal_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)3406 MS_BOOL MHal_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
3407 {
3408 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3409 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3410
3411 if (bEnable == TRUE)
3412 {
3413 //interlace output vtotal modify
3414 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9), BIT(9));
3415
3416 // two different interlace information through channel A reserved bit
3417 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7));
3418 // two different interlace information through channel B reserved bit
3419 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11));
3420 }
3421 else
3422 {
3423 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L , 0, BIT(9));
3424 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7));
3425 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11));
3426 }
3427
3428 return TRUE;
3429 }
3430
MHal_PNL_GetOutputInterlaceTiming(void * pInstance)3431 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance)
3432 {
3433 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3434 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3435
3436 MS_BOOL bIsInterlaceOutput = FALSE;
3437 //interlace output vtotal modify
3438 if (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, BIT(9)) == BIT(9))
3439 {
3440 if ((MOD_R2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7)) == (BIT(4) | BIT(7)))
3441 || (MOD_R2BYTEMSK(REG_MOD_BK00_42_L, BIT(10) | BIT(11)) == (BIT(10)|BIT(11))))
3442 {
3443 bIsInterlaceOutput = TRUE;
3444 }
3445 }
3446 else
3447 {
3448 bIsInterlaceOutput = FALSE;
3449 }
3450 return bIsInterlaceOutput;
3451 }
3452
3453 ////Ext LPLL setting
_MHal_PNL_Init_ExtLPLL(void * pInstance,PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)3454 static void _MHal_PNL_Init_ExtLPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz)
3455 {
3456 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3457
3458 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz, E_PNL_LPLL_OSD);
3459
3460 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3461 {
3462 printf("Not Supported LPLL Type, skip LPLL Init\n");
3463 return;
3464 }
3465
3466 _MHal_PNL_DumpLPLLTable(pInstance, u8SupportedLPLLLIndex, E_PNL_LPLL_OSD);
3467 }
3468
_MHal_PNL_Get_ExtLPLL_LoopDIV(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3469 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopDIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3470 {
3471 MS_U16 u16loop_div = 0;
3472 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3473 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,u8LPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3474
3475 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3476 {
3477 u16loop_div = 0 ;
3478 }
3479 else
3480 {
3481 u16loop_div = u16EXT_LoopDiv[u8SupportedLPLLLIndex];
3482 }
3483
3484 u16loop_div *= 2;
3485 return u16loop_div;
3486 }
3487
_MHal_PNL_Get_ExtLPLL_LoopGain(void * pInstance,MS_U8 eLPLL_Mode,MS_U8 eLPLL_Type,MS_U64 ldHz)3488 static MS_U8 _MHal_PNL_Get_ExtLPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz)
3489 {
3490 MS_U16 u16loop_gain = 0;
3491 E_PNL_SUPPORTED_LPLL_EXT_TYPE u8SupportedLPLLLIndex = E_PNL_SUPPORTED_LPLL_EXT_MAX;
3492 u8SupportedLPLLLIndex = _MHal_PNL_GetSupportedLPLLIndex(pInstance, eLPLL_Type,eLPLL_Mode,ldHz,E_PNL_LPLL_OSD);
3493
3494 if (u8SupportedLPLLLIndex == E_PNL_SUPPORTED_LPLL_EXT_MAX)
3495 {
3496 u16loop_gain = 0 ;
3497 }
3498 else
3499 {
3500 u16loop_gain = u16EXT_LoopGain[u8SupportedLPLLLIndex];
3501 }
3502 return u16loop_gain;
3503 }
3504
3505
3506 // Output Dclk
MHal_PNL_CalExtLPLLSETbyDClk(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U64 ldHz)3507 void MHal_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz)
3508 {
3509
3510 MS_U64 u64LdPllSet = 0;
3511 MS_U64 u64DclkFactor = 0;
3512 MS_U32 u32Div = 0;
3513 // loop div and loop gain use default parameters to avoid dclk floating out of range and getting wrong value
3514 MS_U32 u32Factor = 10;
3515
3516 _MHal_PNL_Init_ExtLPLL(pInstance, u8LPLL_Type, u8LPLL_Mode, ldHz);
3517
3518 //the first " *2 " is from the dual mode
3519 u32Div=(MS_U32)(_MHal_PNL_Get_ExtLPLL_LoopDIV(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3520 u64DclkFactor=((MS_U64)LVDS_MPLL_CLOCK_MHZ * (MS_U64)524288 * (MS_U64)_MHal_PNL_Get_ExtLPLL_LoopGain(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz));
3521 u64LdPllSet = (u64DclkFactor * 1000000 * u32Factor *2) + ((ldHz * u32Div) >> 1);
3522 do_div(u64LdPllSet, ldHz);
3523 do_div(u64LdPllSet, u32Div);
3524
3525 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet);
3526 //printf("MHal_PNL_CalExtLPLLSETbyDClk u32KHz = %u, u32LpllSet = %x\n", ldHz, (MS_U32)u64LdPllSet);
3527
3528 }
3529
MHal_PNL_SetOSDCOutputType(void * pInstance,PNL_TYPE eLPLL_Type,E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)3530 void MHal_PNL_SetOSDCOutputType(void *pInstance, PNL_TYPE eLPLL_Type, E_PNL_OSDC_OUTPUT_FORMAT eOC_OutputFormat)
3531 {
3532 // VBy1 co-registers
3533 if ((eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)
3534 && (eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))
3535 {
3536 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1008); //[3]enable osd lvds channel
3537 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_69_L, BIT(15), BIT(15)); //[15]sw_rst
3538
3539 //-------------------------------------
3540 //## pe
3541 // MOD_A_W2BYTE(REG_MOD_A_BK00_30_L, 0x3fff);
3542 // MOD_W2BYTE(REG_MOD_BK00_23_L, 0x7000);
3543 // MOD_W2BYTE(REG_MOD_BK00_24_L, 0x7fff);
3544 // MOD_W2BYTE(REG_MOD_BK00_25_L, 0x003f);
3545
3546 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f); //[15]all dk scr[13:8]aln_de_cnt [7:0] aln_pix_cnt
3547
3548 }
3549
3550 if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE)
3551 {
3552 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14),BIT(14)|BIT(15)); //[15]enskew_path2[14]enclk_path2[4]ck_pd[3]ck_pc[2]ck_pb[1]ck_pa[0]en_ck
3553 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0055); //[7:0]reg_output_conf[27:16]
3554 W2BYTE(REG_CLKGEN0_53_L,0x00CC); //[13:8] clk_bt656 -> clk_lpll_buf
3555 W2BYTE(REG_CLKGEN0_63_L,0x0410); //[11:8] clk_tx_mod_osd, [4:0] osd2mod
3556 W2BYTE(REG_RVD_09_L, 0x1800); //[12:8]ckg_vby1_fifo_osd [3:0]clk_vby1_fifo
3557
3558 MOD_W2BYTE(REG_MOD_BK00_42_L, 0x1000); //[12]sw_rst, [3]enable osd lvds channel
3559 MOD_A_W2BYTE(REG_MOD_A_BK00_38_L, 0xc01f);
3560 MOD_A_W2BYTE(REG_MOD_A_BK00_58_L, 0x0440); //[3:0] reg_ckg_tx_mod
3561 MOD_A_W2BYTE(REG_MOD_A_BK00_59_L, 0x0044); //reg_ckg_dot
3562
3563 MOD_W2BYTE(REG_MOD_BK00_71_L, 0xffff);
3564 MOD_W2BYTE(REG_MOD_BK00_5B_L, 0x0087); //[0]enable serializer function ,
3565 //[1]enable serializer auto fix read/write point mis-balance
3566 //[2]enable osd serializer auto fix read/write point mis-balance
3567 //[7]for OSD, switch chanel 8~13 as OSD path
3568 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd000);
3569 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd330);
3570 MOD_W2BYTE(REG_MOD_BK00_64_L, 0xd320);
3571 MOD_W2BYTE(REG_MOD_BK00_65_L, 0x8f3f);
3572 //-------------------------------------
3573 //## icon (Swing)
3574 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3575 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x7f7f);
3576 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3577
3578 // vby1 osd 4 lane
3579 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa260); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap
3580 }
3581 else if( eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_2LANE)
3582 {
3583 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, BIT(14) ,BIT(14)|BIT(15));
3584 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, 0x0005);
3585
3586 //-------------------------------------
3587 //## icon (Swing)
3588 MOD_A_W2BYTE(REG_MOD_A_BK00_0C_L, 0x7f7f);
3589 MOD_A_W2BYTE(REG_MOD_A_BK00_0D_L, 0x0000);
3590 MOD_A_W2BYTE(REG_MOD_A_BK00_0E_L, 0x0000);
3591
3592 //vby1 osd 2 lane
3593 MOD_W2BYTE(REG_MOD_BK00_66_L, 0xa240); //[15]proc_st[13:12]byte_mode 4 byte mode[6]2ch_vby1_osd[9]swap[5]vby1_osd_4ch
3594 }
3595
3596 // Control VBY1 output format and bit orders
3597 switch(eOC_OutputFormat)
3598 {
3599 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB1:
3600 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3601 break;
3602
3603 case E_PNL_OSDC_OUTPUT_FORMAT_VBY1_ARGB2:
3604 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1));
3605 break;
3606
3607 default:
3608 printf("OSDC output format uses default value\n");
3609 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1));
3610 break;
3611 }
3612
3613
3614 }
3615
MHal_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)3616 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
3617 {
3618 MS_U16 u16Span;
3619 MS_U16 u16Step;
3620 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
3621
3622 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
3623 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
3624 // Set SPAN
3625 if(u16Fmodulation < 200 || u16Fmodulation > 400)
3626 u16Fmodulation = 300;
3627 u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) / ((MS_U32)u32PLL_SET) ) ;
3628
3629 // Set STEP
3630 if(u16Rdeviation > 300)
3631 u16Rdeviation = 300;
3632 u16Step = ((MS_U32)u32PLL_SET*u16Rdeviation) / ((MS_U32)u16Span*10000);
3633
3634 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP
3635 W2BYTE(L_BK_LPLL(0x4F), u16Span & 0x3FFF);// LPLL_SPAN
3636 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
3637
3638
3639 return TRUE;
3640 }
3641
MHal_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)3642 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
3643 {
3644 //printf("bEnable = %d\n", bEnable);
3645 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
3646 W2BYTEMSK((L_BK_LPLL(0x4E)), (bEnable << 15), BIT(15)); // Enable ssc
3647 }
3648
MHal_PNL_Set_T3D_Setting(void * pInstance)3649 void MHal_PNL_Set_T3D_Setting(void *pInstance)
3650 {
3651 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3652 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3653
3654 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
3655 }
3656
MHal_PNL_Set_Device_Bank_Offset(void * pInstance)3657 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance)
3658 {
3659 UNUSED(pInstance);
3660 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM);
3661 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg bank offset
3662 u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg bank offset
3663 }
3664
MHal_PNL_Init(void * pInstance)3665 void MHal_PNL_Init(void *pInstance)
3666 {
3667 // Do nothing
3668 UNUSED(pInstance);
3669 }
3670
MHal_PNL_Bringup(void * pInstance)3671 void MHal_PNL_Bringup(void *pInstance)
3672 {
3673 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3674 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3675 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3676 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3677
3678 ///patch for bring up
3679 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
3680 {
3681 }
3682 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_8LANE)
3683 {
3684 //==========================//
3685 //= Setting LPLL =//
3686 //==========================//
3687 //==========================//
3688 //= ICON RCON PE =//
3689 //==========================//
3690 //W2BYTE(0x111e10, 0xffff);
3691 //W2BYTE(0x111e12, 0xffff);
3692 //W2BYTE(0x111e14, 0xffff);
3693 //W2BYTE(0x111e16, 0xffff);
3694 //W2BYTE(0x111e18, 0xffff);
3695 //W2BYTE(0x111e1a, 0xffff);
3696 //W2BYTE(0x111e1c, 0xffff);
3697
3698 //==========================//
3699 //= Setting MOD =//
3700 //==========================//
3701 //W2BYTE(0x103210, 0x5410);
3702 //W2BYTE(0x103212, 0x7632);
3703 W2BYTE(0x111ee2, 0xffff);
3704 W2BYTE(0x1032c0, 0xd000);
3705 W2BYTE(0x1032c0, 0xd330);
3706 W2BYTE(0x1032c0, 0xd320);
3707 W2BYTE(0x1032c2, 0x8f3f);
3708 // W2BYTE(0x1032c4, 0xac40); //Addr:62; bit[11:10] = 2'b11; => reg_vby1_w_r_ini[1:0]
3709 //W2BYTE(0x1032cc, 0xac40); //Addr:66; bit[11:10] = 2'b11; => reg_vby1_w_r_ini_osd[1:0]
3710 //==========================//
3711 //= GPIO =//
3712 //==========================//
3713 W2BYTE(0x111e80, 0xffff);
3714 W2BYTE(0x111e82, 0xffff);
3715 W2BYTE(0x111e84, 0xffff);
3716 W2BYTE(0x111e86, 0xffff);
3717 W2BYTE(0x111e90, 0xffff);
3718 W2BYTE(0x111e92, 0xffff);
3719
3720 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1)) // use Dual port to decide the Vx1 1 or 2 devision config
3721 {
3722 printf("Vx1 2 division\n");
3723 //==========================//
3724 //= Setting MOD =//
3725 //==========================//
3726 W2BYTE(0x103240, 0x0002); //[2:0]reg_mft_mode
3727 W2BYTE(0x103242, 0x1002); //[11:0]reg_dly_value
3728 W2BYTE(0x103244, 0x0f00); //[12:0]reg_hsize
3729 W2BYTE(0x10324c, 0x0780); //[12:0]reg_div_len
3730 W2BYTE(0x1032fe, 0x0002); //[2:0]reg_sram_usage
3731 W2BYTE(0x1032a6, 0x4000); //[14]reg_vfde_mask
3732 //W2BYTE(0x103210, 0x6420); //vby1 swap
3733 //W2BYTE(0x103212, 0x7531);
3734 //W2BYTE(0x1032c6, 0x1800); //[12]vby1_8ch[11:10]pair_mirror2
3735 }
3736 }
3737
3738 }
3739
MHal_PNL_GetPanelVStart(void)3740 MS_U16 MHal_PNL_GetPanelVStart(void)
3741 {
3742 return 8;
3743 }
3744
MHal_PNL_Check_VBY1_Handshake_Status(void * pInstance)3745 MS_BOOL MHal_PNL_Check_VBY1_Handshake_Status(void *pInstance)
3746 {
3747 if(MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF) != 0xFAE)
3748 {
3749 //printf("VBY1 handshake return because the reg value is 0x%u, not 0xFAE.\n", MOD_R2BYTEMSK(REG_MOD_BK00_60_L, 0x0FFF));
3750 return FALSE;
3751 }
3752 else
3753 {
3754 //printf("VBY handshake check success.\n");
3755 return TRUE;
3756 }
3757 }
3758
MHal_PNL_ChannelFIFOPointerADjust(void * pInstance)3759 void MHal_PNL_ChannelFIFOPointerADjust(void *pInstance)
3760 {
3761 // 0 to 1 then will do write and read point capture to
3762 // Read : REG_MOD_BK00_5F_L[14:12]
3763 // write : REG_MOD_BK00_5F_L[10:8]
3764 // it takes 3 ticks to capture and riu takes 5 ticks to write
3765 // so we don't have to do any delay between rising capture and
3766 // read/write pointer recognition
3767 MsOS_DelayTaskUs(500);
3768 MOD_A_W2BYTE(REG_MOD_A_BK00_5C_L, 0x3300);
3769
3770 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
3771 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
3772
3773 //split Video & OSD process start bit
3774 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
3775 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
3776 {
3777 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
3778 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
3779 }
3780
3781 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
3782 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
3783
3784 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
3785 MS_U16 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3786 MS_S8 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3787 MS_S8 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3788
3789 //OSD part
3790 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
3791 MS_U16 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3792 MS_S8 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3793 MS_S8 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3794
3795 MS_BOOL bOSDC = ((MOD_A_R2BYTE(REG_MOD_A_BK00_58_L)&0x00F0) == 0x0040)?TRUE:FALSE;
3796 while (((abs(u8WritePointer-u8ReadPointer) >4) && (abs(u8WritePointer-u8ReadPointer)<2))
3797 ||(((abs(OSDu8WritePointer-OSDu8ReadPointer) >4) && (abs(OSDu8WritePointer-OSDu8ReadPointer)<2))&&bOSDC))
3798 {
3799 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(0));
3800 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(0), BIT(0));
3801
3802 //split Video & OSD process start bit
3803 //if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
3804 if((R2BYTEMSK(REG_CHIP_REVISION, 0xFF00)>>8) >=1)
3805 {
3806 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, 0, BIT(14));
3807 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(14), BIT(14));
3808 }
3809
3810 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0 , BIT(1));
3811 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(1), BIT(1));
3812
3813 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, 0, BIT(2)|BIT(3));
3814 u16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3815 u8WritePointer = (u16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3816 u8ReadPointer = (u16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3817
3818 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_5D_L, BIT(2)|BIT(3), BIT(2)|BIT(3));
3819 OSDu16name = MOD_A_R2BYTE(REG_MOD_A_BK00_5D_L);
3820 OSDu8WritePointer = (OSDu16name & 0x0700) >> 8; // REG_MOD_BK00_5F_L[10:8]
3821 OSDu8ReadPointer = (OSDu16name & 0x7000) >> 12; // REG_MOD_BK00_5F_L[14:12]
3822 printf("bOSDC [%d]\n",bOSDC);
3823
3824 }
3825
3826 }
3827
MHal_PNL_VBY1_Hardware_TrainingMode_En(void * pInstance,MS_BOOL bIsVideoMode,MS_BOOL bEnable)3828 void MHal_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable)
3829 {
3830 if(bIsVideoMode)
3831 {
3832 if(bEnable)
3833 {
3834 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AAE);
3835 }
3836 else
3837 {
3838 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0AA6);
3839 }
3840 }
3841 else
3842 {
3843 if(bEnable)
3844 {
3845 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AAE);
3846 }
3847 else
3848 {
3849 MOD_W2BYTE(REG_MOD_BK00_64_L, 0x0AA6);
3850 }
3851 }
3852 }
3853
MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void * pInstance)3854 MS_BOOL MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(void *pInstance)
3855 {
3856 #ifdef SUPPORT_VBY1_HWTRAINING_MODE
3857 return TRUE;
3858 #else
3859 return FALSE;
3860 #endif
3861 }
3862
MHal_PNL_TCON_Patch(void)3863 void MHal_PNL_TCON_Patch(void)
3864 {
3865 // MOD sw reset
3866 MOD_W2BYTE(REG_MOD_BK00_42_L,0x0000);
3867 MOD_W2BYTE(REG_MOD_BK00_42_L,0x1000);
3868 }
3869
_Hal_MOD_Refine_ICON(MS_U16 u16ICON)3870 static MS_U16 _Hal_MOD_Refine_ICON(MS_U16 u16ICON)
3871 {
3872 MS_U16 u16ICON_L = (u16ICON & 0x00FF);
3873 MS_U16 u16ICON_H = ((u16ICON & 0xFF00)>>8);
3874 MS_U16 u16Result = 0;
3875 if( (u16ICON_L > MOD_LVDS_ICON_HIGH_LIMIT) || (u16ICON_L < MOD_LVDS_ICON_LOW_LIMIT) )
3876 {
3877 u16Result = MOD_LVDS_ICON_DEFAULT;
3878 }
3879 else
3880 {
3881 u16Result = u16ICON_L;
3882 }
3883
3884 if( (u16ICON_H > MOD_LVDS_ICON_HIGH_LIMIT) || (u16ICON_H < MOD_LVDS_ICON_LOW_LIMIT) )
3885 {
3886 u16Result |= (MOD_LVDS_ICON_DEFAULT<<8);
3887 }
3888 else
3889 {
3890 u16Result |= (u16ICON_H<<8);
3891 }
3892 return u16Result;
3893 }
3894
_Hal_MOD_External_eFuse(void)3895 static MS_BOOL _Hal_MOD_External_eFuse(void)
3896 {
3897 #ifdef MOD_EFUSE_IN_MBOOT
3898 return TRUE;
3899 #else
3900 return FALSE;
3901 #endif
3902 }
3903
_MHal_PNL_Get_LaneNum(void * pInstance)3904 static MS_U8 _MHal_PNL_Get_LaneNum(void *pInstance)
3905 {
3906 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3907 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3908 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3909 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3910
3911 MS_U8 u8LaneNum = 0;
3912 //check lane num
3913 if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
3914 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
3915 {
3916 u8LaneNum = 8;
3917 }
3918 else if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
3919 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
3920 {
3921 u8LaneNum = 4;
3922 }
3923 else if((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)
3924 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
3925 {
3926 u8LaneNum = 2;
3927 }
3928 else
3929 {
3930 u8LaneNum = 0;
3931 }
3932 return u8LaneNum;
3933 }
3934
3935
_MHal_PNL_Auto_Set_Config(void * pInstance,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)3936 static void _MHal_PNL_Auto_Set_Config(void *pInstance,
3937 MS_U16 u16OutputOrder0_3,
3938 MS_U16 u16OutputOrder4_7,
3939 MS_U16 u16OutputOrder8_11,
3940 MS_U16 u16OutputOrder12_13)
3941 {
3942 //attention : This function just support vby1 now.
3943 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
3944 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
3945 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
3946 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
3947
3948
3949 MS_U8 u8OutputConfigCount = 0;
3950 MS_U16 u16Config =0;
3951 MS_U8 u8Count = 0;
3952 MS_U8 u8LaneNum = 0;
3953 MS_BOOL bSkip = TRUE;
3954
3955 //check lane num
3956 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
3957 if(u8LaneNum!=0)
3958 {
3959 bSkip = FALSE;
3960 }
3961 else
3962 {
3963 bSkip = TRUE;
3964
3965 //use default config
3966 MHal_Output_LVDS_Pair_Setting(pInstance,
3967 pPNLResourcePrivate->sthalPNL._u8MOD_LVDS_Pair_Type,
3968 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG0_7,
3969 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG8_15,
3970 pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16OutputCFG16_21);
3971 }
3972
3973 if(!bSkip)
3974 {
3975 //set output config
3976 u16Config = 0;
3977 u8OutputConfigCount = 0;
3978 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP1 ; u8Count++ )
3979 {
3980 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
3981 {
3982 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
3983 }
3984 u16OutputOrder0_3 = u16OutputOrder0_3 / PINMAPPING_EXP;
3985 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
3986 }
3987 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP2 ; u8Count++ )
3988 {
3989 if( (u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
3990 {
3991 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
3992 }
3993 u16OutputOrder4_7 = u16OutputOrder4_7 / PINMAPPING_EXP;
3994 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
3995 }
3996 MOD_A_W2BYTE(REG_MOD_A_BK00_00_L, u16Config);
3997
3998 u16Config =0;
3999 u8OutputConfigCount = 0;
4000 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP3 ; u8Count++ )
4001 {
4002 if( (u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
4003 {
4004 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
4005 }
4006 u16OutputOrder8_11 = u16OutputOrder8_11 / PINMAPPING_EXP;
4007 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
4008 }
4009 for( u8Count = 0 ; u8Count < LANE_NUM_EACH_PINMAPPING_GROUP4 ; u8Count++ )
4010 {
4011 if( (u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
4012 {
4013 u16Config += CONFIG_FOR_VBY1_DATA<<u8OutputConfigCount;
4014 }
4015 u16OutputOrder12_13 = u16OutputOrder12_13 / PINMAPPING_EXP;
4016 u8OutputConfigCount += CONFIG_FOR_VBY1_DATA_BIT_NUM;
4017 }
4018 MOD_A_W2BYTE(REG_MOD_A_BK00_01_L, u16Config);
4019 }
4020 }
4021
_MHal_PNL_Set_Clk(void * pInstance,MS_U8 Type,MS_U16 u16OutputOrder0_3,MS_U16 u16OutputOrder4_7,MS_U16 u16OutputOrder8_11,MS_U16 u16OutputOrder12_13)4022 static void _MHal_PNL_Set_Clk(void *pInstance,
4023 MS_U8 Type,
4024 MS_U16 u16OutputOrder0_3,
4025 MS_U16 u16OutputOrder4_7,
4026 MS_U16 u16OutputOrder8_11,
4027 MS_U16 u16OutputOrder12_13)
4028 {
4029 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
4030 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
4031 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
4032 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
4033
4034 if(Type == APIPNL_OUTPUT_CHANNEL_ORDER_USER )
4035 {
4036 MS_U8 u8Clk = 0;
4037 MS_U8 u8LaneNum = 0;
4038 MS_BOOL bSkip = TRUE;
4039 MS_U8 u8Count = 0;
4040 MS_U8 u8Count1 = 0;
4041 MS_U8 u8StartLane = 0;
4042
4043 //check lane num
4044 u8LaneNum = _MHal_PNL_Get_LaneNum(pInstance);
4045 if(u8LaneNum!=0)
4046 {
4047 bSkip = FALSE;
4048 }
4049 else
4050 {
4051 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F); //open all clk
4052 bSkip = TRUE;
4053 }
4054
4055 //count clk
4056 if(!bSkip)
4057 {
4058 u8Clk = 0;
4059 u8StartLane = 0;
4060 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP1) ; u8Count++ )
4061 {//lane 0 - lane 3
4062 if( ( u16OutputOrder0_3 % PINMAPPING_EXP ) < u8LaneNum)
4063 {
4064 u8Count1 = 0;
4065 do
4066 {
4067 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
4068 {
4069 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
4070 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
4071 break;
4072 }
4073 u8Count1 ++;
4074 }
4075 while(u8Count1<VBY1_CLK_TBL_ROW);
4076 }
4077 u16OutputOrder0_3 /= PINMAPPING_EXP;
4078 }
4079
4080 u8StartLane = 4;
4081 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP2) ; u8Count++ )
4082 {//lane 4 - lane 7
4083 if( ( u16OutputOrder4_7 % PINMAPPING_EXP ) < u8LaneNum)
4084 {
4085 u8Count1 = 0;
4086 do
4087 {
4088 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
4089 {
4090 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
4091 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
4092 break;
4093 }
4094 u8Count1 ++;
4095 }
4096 while(u8Count1<VBY1_CLK_TBL_ROW);
4097 }
4098 u16OutputOrder4_7 /= PINMAPPING_EXP;
4099 }
4100
4101 u8StartLane = 8;
4102 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP3) ; u8Count++ )
4103 {//lane 8 - lane 11
4104 if( ( u16OutputOrder8_11 % PINMAPPING_EXP ) < u8LaneNum)
4105 {
4106 u8Count1 = 0;
4107 do
4108 {
4109 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
4110 {
4111 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
4112 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
4113 break;
4114 }
4115 u8Count1 ++;
4116 }
4117 while(u8Count1<VBY1_CLK_TBL_ROW);
4118 }
4119 u16OutputOrder8_11 /= PINMAPPING_EXP;
4120
4121 }
4122
4123 u8StartLane = 12;
4124 for( u8Count = u8StartLane ; u8Count < (u8StartLane+LANE_NUM_EACH_PINMAPPING_GROUP4) ; u8Count++ )
4125 {//lane 12 - lane 13
4126 if( ( u16OutputOrder12_13 % PINMAPPING_EXP ) < u8LaneNum)
4127 {
4128 u8Count1 = 0;
4129 do
4130 {
4131 if(u8Count>=LANE_AND_CLK_TBL[u8Count1][0] && u8Count<=LANE_AND_CLK_TBL[u8Count1][1])
4132 {
4133 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
4134 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
4135 break;
4136 }
4137 u8Count1 ++;
4138 }
4139 while(u8Count1<VBY1_CLK_TBL_ROW);
4140 }
4141 u16OutputOrder12_13 /= PINMAPPING_EXP;
4142 }
4143
4144 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, u8Clk, 0x1F);
4145 }
4146 }
4147 else
4148 {
4149 if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_8LANE)
4150 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_8LANE))
4151 {
4152 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16MOD_CTRLA & BIT(1))
4153 {
4154 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1D, 0x1F);
4155 }
4156 else
4157 {
4158 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1D, 0x1F);
4159 }
4160 }
4161 else if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)
4162 {//LVDS
4163 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
4164 }
4165 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_4LANE)
4166 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_4LANE))
4167 {
4168 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x0D, 0x1F);
4169 }
4170 else if( (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_10BIT_2LANE)
4171 ||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type_Ext == E_PNL_LPLL_VBY1_8BIT_2LANE))
4172 {
4173 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x05, 0x1F);
4174 }
4175 else
4176 {
4177 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_38_L, 0x1F, 0x1F);
4178 }
4179 }
4180 }
4181
4182 #endif
4183
4184