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Searched refs:wr_cfg (Results 1 – 25 of 47) sorted by relevance

12

/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c1022 MppDevRegWrCfg wr_cfg; in vdpu34x_h264d_start() local
1025 wr_cfg.reg = &regs->common; in vdpu34x_h264d_start()
1026 wr_cfg.size = sizeof(regs->common); in vdpu34x_h264d_start()
1027 wr_cfg.offset = OFFSET_COMMON_REGS; in vdpu34x_h264d_start()
1029 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu34x_h264d_start()
1035 wr_cfg.reg = &regs->h264d_param; in vdpu34x_h264d_start()
1036 wr_cfg.size = sizeof(regs->h264d_param); in vdpu34x_h264d_start()
1037 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in vdpu34x_h264d_start()
1039 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu34x_h264d_start()
1045 wr_cfg.reg = &regs->common_addr; in vdpu34x_h264d_start()
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H A Dhal_h264d_vdpu382.c1076 MppDevRegWrCfg wr_cfg; in vdpu382_h264d_start() local
1079 wr_cfg.reg = &regs->common; in vdpu382_h264d_start()
1080 wr_cfg.size = sizeof(regs->common); in vdpu382_h264d_start()
1081 wr_cfg.offset = OFFSET_COMMON_REGS; in vdpu382_h264d_start()
1083 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu382_h264d_start()
1089 wr_cfg.reg = &regs->h264d_param; in vdpu382_h264d_start()
1090 wr_cfg.size = sizeof(regs->h264d_param); in vdpu382_h264d_start()
1091 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in vdpu382_h264d_start()
1093 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu382_h264d_start()
1099 wr_cfg.reg = &regs->common_addr; in vdpu382_h264d_start()
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H A Dhal_h264d_vdpu384a.c885 MppDevRegWrCfg wr_cfg; in vdpu384a_h264d_start() local
888 wr_cfg.reg = &regs->ctrl_regs; in vdpu384a_h264d_start()
889 wr_cfg.size = sizeof(regs->ctrl_regs); in vdpu384a_h264d_start()
890 wr_cfg.offset = OFFSET_CTRL_REGS; in vdpu384a_h264d_start()
891 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu384a_h264d_start()
897 wr_cfg.reg = &regs->common_addr; in vdpu384a_h264d_start()
898 wr_cfg.size = sizeof(regs->common_addr); in vdpu384a_h264d_start()
899 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in vdpu384a_h264d_start()
900 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu384a_h264d_start()
906 wr_cfg.reg = &regs->h264d_paras; in vdpu384a_h264d_start()
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H A Dhal_h264d_vdpu383.c939 MppDevRegWrCfg wr_cfg; in vdpu383_h264d_start() local
942 wr_cfg.reg = &regs->ctrl_regs; in vdpu383_h264d_start()
943 wr_cfg.size = sizeof(regs->ctrl_regs); in vdpu383_h264d_start()
944 wr_cfg.offset = OFFSET_CTRL_REGS; in vdpu383_h264d_start()
945 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu383_h264d_start()
951 wr_cfg.reg = &regs->common_addr; in vdpu383_h264d_start()
952 wr_cfg.size = sizeof(regs->common_addr); in vdpu383_h264d_start()
953 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in vdpu383_h264d_start()
954 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu383_h264d_start()
960 wr_cfg.reg = &regs->h264d_paras; in vdpu383_h264d_start()
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/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu541_common.c267 MppDevRegWrCfg wr_cfg; in vepu541_set_osd() local
269 wr_cfg.reg = plt_cfg->plt; in vepu541_set_osd()
270 wr_cfg.size = sizeof(MppEncOSDPlt); in vepu541_set_osd()
271 wr_cfg.offset = VEPU541_REG_BASE_OSD_PLT; in vepu541_set_osd()
273 mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vepu541_set_osd()
466 MppDevRegWrCfg wr_cfg; in vepu540_set_osd() local
468 wr_cfg.reg = plt_cfg->plt; in vepu540_set_osd()
469 wr_cfg.size = sizeof(MppEncOSDPlt); in vepu540_set_osd()
470 wr_cfg.offset = VEPU541_REG_BASE_OSD_PLT; in vepu540_set_osd()
471 mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in vepu540_set_osd()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c823 MppDevRegWrCfg wr_cfg; in hal_avs2d_rkv_start() local
826 wr_cfg.reg = &regs->common; in hal_avs2d_rkv_start()
827 wr_cfg.size = sizeof(regs->common); in hal_avs2d_rkv_start()
828 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_avs2d_rkv_start()
830 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_avs2d_rkv_start()
837 wr_cfg.reg = &regs->avs2d_param; in hal_avs2d_rkv_start()
838 wr_cfg.size = sizeof(regs->avs2d_param); in hal_avs2d_rkv_start()
839 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_avs2d_rkv_start()
841 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_avs2d_rkv_start()
848 wr_cfg.reg = &regs->common_addr; in hal_avs2d_rkv_start()
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H A Dhal_avs2d_vdpu382.c889 MppDevRegWrCfg wr_cfg; in hal_avs2d_vdpu382_start() local
892 wr_cfg.reg = &regs->common; in hal_avs2d_vdpu382_start()
893 wr_cfg.size = sizeof(regs->common); in hal_avs2d_vdpu382_start()
894 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_avs2d_vdpu382_start()
896 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_avs2d_vdpu382_start()
903 wr_cfg.reg = &regs->avs2d_param; in hal_avs2d_vdpu382_start()
904 wr_cfg.size = sizeof(regs->avs2d_param); in hal_avs2d_vdpu382_start()
905 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_avs2d_vdpu382_start()
907 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_avs2d_vdpu382_start()
914 wr_cfg.reg = &regs->common_addr; in hal_avs2d_vdpu382_start()
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H A Dhal_avs2d_vdpu383.c733 MppDevRegWrCfg wr_cfg; in hal_avs2d_vdpu383_start() local
736 wr_cfg.reg = &regs->ctrl_regs; in hal_avs2d_vdpu383_start()
737 wr_cfg.size = sizeof(regs->ctrl_regs); in hal_avs2d_vdpu383_start()
738 wr_cfg.offset = OFFSET_CTRL_REGS; in hal_avs2d_vdpu383_start()
739 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_avs2d_vdpu383_start()
745 wr_cfg.reg = &regs->common_addr; in hal_avs2d_vdpu383_start()
746 wr_cfg.size = sizeof(regs->common_addr); in hal_avs2d_vdpu383_start()
747 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_avs2d_vdpu383_start()
748 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_avs2d_vdpu383_start()
754 wr_cfg.reg = &regs->avs2d_paras; in hal_avs2d_vdpu383_start()
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/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu382.c982 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu382_start() local
985 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu382_start()
986 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu382_start()
987 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_h265d_vdpu382_start()
989 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
995 wr_cfg.reg = &hw_regs->h265d_param; in hal_h265d_vdpu382_start()
996 wr_cfg.size = sizeof(hw_regs->h265d_param); in hal_h265d_vdpu382_start()
997 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_h265d_vdpu382_start()
999 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1005 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu382_start()
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H A Dhal_h265d_vdpu34x.c1189 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu34x_start() local
1192 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu34x_start()
1193 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu34x_start()
1194 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_h265d_vdpu34x_start()
1196 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1202 wr_cfg.reg = &hw_regs->h265d_param; in hal_h265d_vdpu34x_start()
1203 wr_cfg.size = sizeof(hw_regs->h265d_param); in hal_h265d_vdpu34x_start()
1204 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_h265d_vdpu34x_start()
1206 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1212 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu34x_start()
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H A Dhal_h265d_vdpu384a.c1207 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu384a_start() local
1210 wr_cfg.reg = &hw_regs->ctrl_regs; in hal_h265d_vdpu384a_start()
1211 wr_cfg.size = sizeof(hw_regs->ctrl_regs); in hal_h265d_vdpu384a_start()
1212 wr_cfg.offset = OFFSET_CTRL_REGS; in hal_h265d_vdpu384a_start()
1213 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1219 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu384a_start()
1220 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu384a_start()
1221 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_h265d_vdpu384a_start()
1222 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1228 wr_cfg.reg = &hw_regs->h265d_paras; in hal_h265d_vdpu384a_start()
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H A Dhal_h265d_vdpu383.c1269 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu383_start() local
1272 wr_cfg.reg = &hw_regs->ctrl_regs; in hal_h265d_vdpu383_start()
1273 wr_cfg.size = sizeof(hw_regs->ctrl_regs); in hal_h265d_vdpu383_start()
1274 wr_cfg.offset = OFFSET_CTRL_REGS; in hal_h265d_vdpu383_start()
1275 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1281 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu383_start()
1282 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu383_start()
1283 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_h265d_vdpu383_start()
1284 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1290 wr_cfg.reg = &hw_regs->h265d_paras; in hal_h265d_vdpu383_start()
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/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu1_v2.c391 MppDevRegWrCfg wr_cfg; in hal_jpege_vepu1_start() local
395 wr_cfg.reg = ctx->regs; in hal_jpege_vepu1_start()
396 wr_cfg.size = reg_size; in hal_jpege_vepu1_start()
397 wr_cfg.offset = 0; in hal_jpege_vepu1_start()
399 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_jpege_vepu1_start()
526 MppDevRegWrCfg wr_cfg; in hal_jpege_vepu1_part_start() local
530 wr_cfg.reg = ctx->regs; in hal_jpege_vepu1_part_start()
531 wr_cfg.size = reg_size; in hal_jpege_vepu1_part_start()
532 wr_cfg.offset = 0; in hal_jpege_vepu1_part_start()
534 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_jpege_vepu1_part_start()
H A Dhal_jpege_vepu2_v2.c692 MppDevRegWrCfg wr_cfg; in multi_core_start() local
695 wr_cfg.reg = regs; in multi_core_start()
696 wr_cfg.size = reg_size; in multi_core_start()
697 wr_cfg.offset = 0; in multi_core_start()
699 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in multi_core_start()
814 MppDevRegWrCfg wr_cfg; in hal_jpege_vepu2_start() local
820 wr_cfg.reg = regs; in hal_jpege_vepu2_start()
821 wr_cfg.size = reg_size; in hal_jpege_vepu2_start()
822 wr_cfg.offset = 0; in hal_jpege_vepu2_start()
824 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_jpege_vepu2_start()
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/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_vdpu34x.c902 MppDevRegWrCfg wr_cfg; in hal_vp9d_vdpu34x_start() local
905 wr_cfg.reg = &hw_regs->common; in hal_vp9d_vdpu34x_start()
906 wr_cfg.size = sizeof(hw_regs->common); in hal_vp9d_vdpu34x_start()
907 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_vp9d_vdpu34x_start()
909 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu34x_start()
915 wr_cfg.reg = &hw_regs->vp9d_param; in hal_vp9d_vdpu34x_start()
916 wr_cfg.size = sizeof(hw_regs->vp9d_param); in hal_vp9d_vdpu34x_start()
917 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_vp9d_vdpu34x_start()
919 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu34x_start()
925 wr_cfg.reg = &hw_regs->common_addr; in hal_vp9d_vdpu34x_start()
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H A Dhal_vp9d_vdpu382.c936 MppDevRegWrCfg wr_cfg; in hal_vp9d_vdpu382_start() local
939 wr_cfg.reg = &hw_regs->common; in hal_vp9d_vdpu382_start()
940 wr_cfg.size = sizeof(hw_regs->common); in hal_vp9d_vdpu382_start()
941 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_vp9d_vdpu382_start()
943 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()
949 wr_cfg.reg = &hw_regs->vp9d_param; in hal_vp9d_vdpu382_start()
950 wr_cfg.size = sizeof(hw_regs->vp9d_param); in hal_vp9d_vdpu382_start()
951 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_vp9d_vdpu382_start()
953 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()
959 wr_cfg.reg = &hw_regs->common_addr; in hal_vp9d_vdpu382_start()
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H A Dhal_vp9d_vdpu383.c1145 MppDevRegWrCfg wr_cfg; in hal_vp9d_vdpu383_start() local
1148 wr_cfg.reg = &hw_regs->ctrl_regs; in hal_vp9d_vdpu383_start()
1149 wr_cfg.size = sizeof(hw_regs->ctrl_regs); in hal_vp9d_vdpu383_start()
1150 wr_cfg.offset = OFFSET_CTRL_REGS; in hal_vp9d_vdpu383_start()
1151 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu383_start()
1157 wr_cfg.reg = &hw_regs->common_addr; in hal_vp9d_vdpu383_start()
1158 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_vp9d_vdpu383_start()
1159 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_vp9d_vdpu383_start()
1160 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu383_start()
1166 wr_cfg.reg = &hw_regs->vp9d_paras; in hal_vp9d_vdpu383_start()
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/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu2.c248 MppDevRegWrCfg wr_cfg; in hal_vpu2_h263d_start() local
251 wr_cfg.reg = regs; in hal_vpu2_h263d_start()
252 wr_cfg.size = sizeof(Vpu2H263dRegSet_t); in hal_vpu2_h263d_start()
253 wr_cfg.offset = 0; in hal_vpu2_h263d_start()
255 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vpu2_h263d_start()
H A Dhal_h263d_vdpu1.c247 MppDevRegWrCfg wr_cfg; in hal_vpu1_h263d_start() local
250 wr_cfg.reg = regs; in hal_vpu1_h263d_start()
251 wr_cfg.size = sizeof(Vpu1H263dRegSet_t); in hal_vpu1_h263d_start()
252 wr_cfg.offset = 0; in hal_vpu1_h263d_start()
254 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vpu1_h263d_start()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu540c.c1521 MppDevRegWrCfg wr_cfg; in hal_h264e_vepu540c_start() local
1524 wr_cfg.reg = &ctx->regs_set->reg_ctl; in hal_h264e_vepu540c_start()
1525 wr_cfg.size = sizeof(ctx->regs_set->reg_ctl); in hal_h264e_vepu540c_start()
1526 wr_cfg.offset = VEPU540C_CTL_OFFSET; in hal_h264e_vepu540c_start()
1530 RK_U32 *reg = (RK_U32)wr_cfg.reg; in hal_h264e_vepu540c_start()
1538 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu540c_start()
1543 wr_cfg.reg = &ctx->regs_set->reg_base; in hal_h264e_vepu540c_start()
1544 wr_cfg.size = sizeof(ctx->regs_set->reg_base); in hal_h264e_vepu540c_start()
1545 wr_cfg.offset = VEPU540C_BASE_OFFSET; in hal_h264e_vepu540c_start()
1547 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu540c_start()
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H A Dhal_h264e_vepu580.c2199 MppDevRegWrCfg wr_cfg; in hal_h264e_vepu580_start() local
2202 wr_cfg.reg = &regs->reg_ctl; in hal_h264e_vepu580_start()
2203 wr_cfg.size = sizeof(regs->reg_ctl); in hal_h264e_vepu580_start()
2204 wr_cfg.offset = VEPU580_CONTROL_CFG_OFFSET; in hal_h264e_vepu580_start()
2208 RK_U32 *reg = (RK_U32)wr_cfg.reg; in hal_h264e_vepu580_start()
2216 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu580_start()
2221 wr_cfg.reg = &regs->reg_base; in hal_h264e_vepu580_start()
2222 wr_cfg.size = sizeof(regs->reg_base); in hal_h264e_vepu580_start()
2223 wr_cfg.offset = VEPU580_BASE_CFG_OFFSET; in hal_h264e_vepu580_start()
2225 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu580_start()
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H A Dhal_h264e_vepu511.c2191 MppDevRegWrCfg wr_cfg; in hal_h264e_vepu511_start() local
2194 wr_cfg.reg = &regs->reg_ctl; in hal_h264e_vepu511_start()
2195 wr_cfg.size = sizeof(regs->reg_ctl); in hal_h264e_vepu511_start()
2196 wr_cfg.offset = VEPU511_CTL_OFFSET; in hal_h264e_vepu511_start()
2200 RK_U32 *reg = (RK_U32)wr_cfg.reg; in hal_h264e_vepu511_start()
2207 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2213 wr_cfg.reg = &regs->reg_frm; in hal_h264e_vepu511_start()
2214 wr_cfg.size = sizeof(regs->reg_frm); in hal_h264e_vepu511_start()
2215 wr_cfg.offset = VEPU511_FRAME_OFFSET; in hal_h264e_vepu511_start()
2217 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
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H A Dhal_h264e_vepu510.c2240 MppDevRegWrCfg wr_cfg; in hal_h264e_vepu510_start() local
2243 wr_cfg.reg = &regs->reg_ctl; in hal_h264e_vepu510_start()
2244 wr_cfg.size = sizeof(regs->reg_ctl); in hal_h264e_vepu510_start()
2245 wr_cfg.offset = VEPU510_CTL_OFFSET; in hal_h264e_vepu510_start()
2249 RK_U32 *reg = (RK_U32)wr_cfg.reg; in hal_h264e_vepu510_start()
2256 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
2262 wr_cfg.reg = &regs->reg_frm; in hal_h264e_vepu510_start()
2263 wr_cfg.size = sizeof(regs->reg_frm); in hal_h264e_vepu510_start()
2264 wr_cfg.offset = VEPU510_FRAME_OFFSET; in hal_h264e_vepu510_start()
2266 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
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/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c266 MppDevRegWrCfg wr_cfg; in hal_m2vd_vdpu1_start() local
271 wr_cfg.reg = regs; in hal_m2vd_vdpu1_start()
272 wr_cfg.size = reg_size; in hal_m2vd_vdpu1_start()
273 wr_cfg.offset = 0; in hal_m2vd_vdpu1_start()
275 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_m2vd_vdpu1_start()
H A Dhal_m2vd_vdpu2.c338 MppDevRegWrCfg wr_cfg; in hal_m2vd_vdpu2_start() local
343 wr_cfg.reg = regs; in hal_m2vd_vdpu2_start()
344 wr_cfg.size = reg_size; in hal_m2vd_vdpu2_start()
345 wr_cfg.offset = 0; in hal_m2vd_vdpu2_start()
347 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_m2vd_vdpu2_start()

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