Lines Matching refs:wr_cfg
1189 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu34x_start() local
1192 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu34x_start()
1193 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu34x_start()
1194 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_h265d_vdpu34x_start()
1196 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1202 wr_cfg.reg = &hw_regs->h265d_param; in hal_h265d_vdpu34x_start()
1203 wr_cfg.size = sizeof(hw_regs->h265d_param); in hal_h265d_vdpu34x_start()
1204 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_h265d_vdpu34x_start()
1206 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1212 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu34x_start()
1213 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu34x_start()
1214 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_h265d_vdpu34x_start()
1216 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1222 wr_cfg.reg = &hw_regs->h265d_addr; in hal_h265d_vdpu34x_start()
1223 wr_cfg.size = sizeof(hw_regs->h265d_addr); in hal_h265d_vdpu34x_start()
1224 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu34x_start()
1226 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1232 wr_cfg.reg = &hw_regs->statistic; in hal_h265d_vdpu34x_start()
1233 wr_cfg.size = sizeof(hw_regs->statistic); in hal_h265d_vdpu34x_start()
1234 wr_cfg.offset = OFFSET_STATISTIC_REGS; in hal_h265d_vdpu34x_start()
1236 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()
1243 wr_cfg.reg = &hw_regs->highpoc; in hal_h265d_vdpu34x_start()
1244 wr_cfg.size = sizeof(hw_regs->highpoc); in hal_h265d_vdpu34x_start()
1245 wr_cfg.offset = OFFSET_POC_HIGHBIT_REGS; in hal_h265d_vdpu34x_start()
1247 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu34x_start()