Lines Matching refs:wr_cfg
2191 MppDevRegWrCfg wr_cfg; in hal_h264e_vepu511_start() local
2194 wr_cfg.reg = ®s->reg_ctl; in hal_h264e_vepu511_start()
2195 wr_cfg.size = sizeof(regs->reg_ctl); in hal_h264e_vepu511_start()
2196 wr_cfg.offset = VEPU511_CTL_OFFSET; in hal_h264e_vepu511_start()
2200 RK_U32 *reg = (RK_U32)wr_cfg.reg; in hal_h264e_vepu511_start()
2207 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2213 wr_cfg.reg = ®s->reg_frm; in hal_h264e_vepu511_start()
2214 wr_cfg.size = sizeof(regs->reg_frm); in hal_h264e_vepu511_start()
2215 wr_cfg.offset = VEPU511_FRAME_OFFSET; in hal_h264e_vepu511_start()
2217 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2223 wr_cfg.reg = ®s->reg_rc_roi; in hal_h264e_vepu511_start()
2224 wr_cfg.size = sizeof(regs->reg_rc_roi); in hal_h264e_vepu511_start()
2225 wr_cfg.offset = VEPU511_RC_ROI_OFFSET; in hal_h264e_vepu511_start()
2227 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2233 wr_cfg.reg = ®s->reg_param; in hal_h264e_vepu511_start()
2234 wr_cfg.size = sizeof(regs->reg_param); in hal_h264e_vepu511_start()
2235 wr_cfg.offset = VEPU511_PARAM_OFFSET; in hal_h264e_vepu511_start()
2237 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2243 wr_cfg.reg = ®s->reg_sqi; in hal_h264e_vepu511_start()
2244 wr_cfg.size = sizeof(regs->reg_sqi); in hal_h264e_vepu511_start()
2245 wr_cfg.offset = VEPU511_SQI_OFFSET; in hal_h264e_vepu511_start()
2247 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2253 wr_cfg.reg = ®s->reg_scl; in hal_h264e_vepu511_start()
2254 wr_cfg.size = sizeof(regs->reg_scl); in hal_h264e_vepu511_start()
2255 wr_cfg.offset = VEPU511_SCL_OFFSET ; in hal_h264e_vepu511_start()
2257 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()
2263 wr_cfg.reg = ®s->reg_osd; in hal_h264e_vepu511_start()
2264 wr_cfg.size = sizeof(regs->reg_osd); in hal_h264e_vepu511_start()
2265 wr_cfg.offset = VEPU511_OSD_OFFSET ; in hal_h264e_vepu511_start()
2267 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu511_start()