Lines Matching refs:wr_cfg
1269 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu383_start() local
1272 wr_cfg.reg = &hw_regs->ctrl_regs; in hal_h265d_vdpu383_start()
1273 wr_cfg.size = sizeof(hw_regs->ctrl_regs); in hal_h265d_vdpu383_start()
1274 wr_cfg.offset = OFFSET_CTRL_REGS; in hal_h265d_vdpu383_start()
1275 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1281 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu383_start()
1282 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu383_start()
1283 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_h265d_vdpu383_start()
1284 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1290 wr_cfg.reg = &hw_regs->h265d_paras; in hal_h265d_vdpu383_start()
1291 wr_cfg.size = sizeof(hw_regs->h265d_paras); in hal_h265d_vdpu383_start()
1292 wr_cfg.offset = OFFSET_CODEC_PARAS_REGS; in hal_h265d_vdpu383_start()
1293 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()
1299 wr_cfg.reg = &hw_regs->h265d_addrs; in hal_h265d_vdpu383_start()
1300 wr_cfg.size = sizeof(hw_regs->h265d_addrs); in hal_h265d_vdpu383_start()
1301 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu383_start()
1302 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu383_start()