Lines Matching refs:wr_cfg

2240         MppDevRegWrCfg wr_cfg;  in hal_h264e_vepu510_start()  local
2243 wr_cfg.reg = &regs->reg_ctl; in hal_h264e_vepu510_start()
2244 wr_cfg.size = sizeof(regs->reg_ctl); in hal_h264e_vepu510_start()
2245 wr_cfg.offset = VEPU510_CTL_OFFSET; in hal_h264e_vepu510_start()
2249 RK_U32 *reg = (RK_U32)wr_cfg.reg; in hal_h264e_vepu510_start()
2256 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
2262 wr_cfg.reg = &regs->reg_frm; in hal_h264e_vepu510_start()
2263 wr_cfg.size = sizeof(regs->reg_frm); in hal_h264e_vepu510_start()
2264 wr_cfg.offset = VEPU510_FRAME_OFFSET; in hal_h264e_vepu510_start()
2266 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
2272 wr_cfg.reg = &regs->reg_rc_roi; in hal_h264e_vepu510_start()
2273 wr_cfg.size = sizeof(regs->reg_rc_roi); in hal_h264e_vepu510_start()
2274 wr_cfg.offset = VEPU510_RC_ROI_OFFSET; in hal_h264e_vepu510_start()
2276 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
2282 wr_cfg.reg = &regs->reg_param; in hal_h264e_vepu510_start()
2283 wr_cfg.size = sizeof(regs->reg_param); in hal_h264e_vepu510_start()
2284 wr_cfg.offset = VEPU510_PARAM_OFFSET; in hal_h264e_vepu510_start()
2286 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
2292 wr_cfg.reg = &regs->reg_sqi; in hal_h264e_vepu510_start()
2293 wr_cfg.size = sizeof(regs->reg_sqi); in hal_h264e_vepu510_start()
2294 wr_cfg.offset = VEPU510_SQI_OFFSET; in hal_h264e_vepu510_start()
2296 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()
2302 wr_cfg.reg = &regs->reg_scl; in hal_h264e_vepu510_start()
2303 wr_cfg.size = sizeof(regs->reg_scl); in hal_h264e_vepu510_start()
2304 wr_cfg.offset = VEPU510_SCL_OFFSET ; in hal_h264e_vepu510_start()
2306 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h264e_vepu510_start()