Lines Matching refs:wr_cfg
1207 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu384a_start() local
1210 wr_cfg.reg = &hw_regs->ctrl_regs; in hal_h265d_vdpu384a_start()
1211 wr_cfg.size = sizeof(hw_regs->ctrl_regs); in hal_h265d_vdpu384a_start()
1212 wr_cfg.offset = OFFSET_CTRL_REGS; in hal_h265d_vdpu384a_start()
1213 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1219 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu384a_start()
1220 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu384a_start()
1221 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_h265d_vdpu384a_start()
1222 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1228 wr_cfg.reg = &hw_regs->h265d_paras; in hal_h265d_vdpu384a_start()
1229 wr_cfg.size = sizeof(hw_regs->h265d_paras); in hal_h265d_vdpu384a_start()
1230 wr_cfg.offset = OFFSET_CODEC_PARAS_REGS; in hal_h265d_vdpu384a_start()
1231 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()
1237 wr_cfg.reg = &hw_regs->h265d_addrs; in hal_h265d_vdpu384a_start()
1238 wr_cfg.size = sizeof(hw_regs->h265d_addrs); in hal_h265d_vdpu384a_start()
1239 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu384a_start()
1240 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu384a_start()