1521         MppDevRegWrCfg wr_cfg;  in hal_h264e_vepu540c_start()  local
1524         wr_cfg.reg = &ctx->regs_set->reg_ctl;  in hal_h264e_vepu540c_start()
1525         wr_cfg.size = sizeof(ctx->regs_set->reg_ctl);  in hal_h264e_vepu540c_start()
1526         wr_cfg.offset = VEPU540C_CTL_OFFSET;  in hal_h264e_vepu540c_start()
1530             RK_U32 *reg = (RK_U32)wr_cfg.reg;  in hal_h264e_vepu540c_start()
1538         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_h264e_vepu540c_start()
1543         wr_cfg.reg = &ctx->regs_set->reg_base;  in hal_h264e_vepu540c_start()
1544         wr_cfg.size = sizeof(ctx->regs_set->reg_base);  in hal_h264e_vepu540c_start()
1545         wr_cfg.offset = VEPU540C_BASE_OFFSET;  in hal_h264e_vepu540c_start()
1547         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_h264e_vepu540c_start()
1552         wr_cfg.reg = &ctx->regs_set->reg_rc_roi;  in hal_h264e_vepu540c_start()
1553         wr_cfg.size = sizeof(ctx->regs_set->reg_rc_roi);  in hal_h264e_vepu540c_start()
1554         wr_cfg.offset = VEPU540C_RCROI_OFFSET;  in hal_h264e_vepu540c_start()
1556         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_h264e_vepu540c_start()
1561         wr_cfg.reg = &ctx->regs_set->reg_s3;  in hal_h264e_vepu540c_start()
1562         wr_cfg.size = sizeof(ctx->regs_set->reg_s3);  in hal_h264e_vepu540c_start()
1563         wr_cfg.offset = VEPU540C_WEG_OFFSET;  in hal_h264e_vepu540c_start()
1565         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_h264e_vepu540c_start()
1570         wr_cfg.reg = &ctx->regs_set->reg_rdo;  in hal_h264e_vepu540c_start()
1571         wr_cfg.size = sizeof(ctx->regs_set->reg_rdo);  in hal_h264e_vepu540c_start()
1572         wr_cfg.offset = VEPU540C_RDOCFG_OFFSET;  in hal_h264e_vepu540c_start()
1574         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_h264e_vepu540c_start()
1580         wr_cfg.reg = &ctx->regs_set->reg_scl;  in hal_h264e_vepu540c_start()
1581         wr_cfg.size = sizeof(ctx->regs_set->reg_scl);  in hal_h264e_vepu540c_start()
1582         wr_cfg.offset = VEPU540C_SCLCFG_OFFSET;  in hal_h264e_vepu540c_start()
1584         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_h264e_vepu540c_start()