Lines Matching refs:wr_cfg

936         MppDevRegWrCfg wr_cfg;  in hal_vp9d_vdpu382_start()  local
939 wr_cfg.reg = &hw_regs->common; in hal_vp9d_vdpu382_start()
940 wr_cfg.size = sizeof(hw_regs->common); in hal_vp9d_vdpu382_start()
941 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_vp9d_vdpu382_start()
943 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()
949 wr_cfg.reg = &hw_regs->vp9d_param; in hal_vp9d_vdpu382_start()
950 wr_cfg.size = sizeof(hw_regs->vp9d_param); in hal_vp9d_vdpu382_start()
951 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_vp9d_vdpu382_start()
953 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()
959 wr_cfg.reg = &hw_regs->common_addr; in hal_vp9d_vdpu382_start()
960 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_vp9d_vdpu382_start()
961 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_vp9d_vdpu382_start()
963 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()
969 wr_cfg.reg = &hw_regs->vp9d_addr; in hal_vp9d_vdpu382_start()
970 wr_cfg.size = sizeof(hw_regs->vp9d_addr); in hal_vp9d_vdpu382_start()
971 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_vp9d_vdpu382_start()
973 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()
979 wr_cfg.reg = &hw_regs->statistic; in hal_vp9d_vdpu382_start()
980 wr_cfg.size = sizeof(hw_regs->statistic); in hal_vp9d_vdpu382_start()
981 wr_cfg.offset = OFFSET_STATISTIC_REGS; in hal_vp9d_vdpu382_start()
983 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vp9d_vdpu382_start()