Lines Matching refs:wr_cfg
982 MppDevRegWrCfg wr_cfg; in hal_h265d_vdpu382_start() local
985 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu382_start()
986 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu382_start()
987 wr_cfg.offset = OFFSET_COMMON_REGS; in hal_h265d_vdpu382_start()
989 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
995 wr_cfg.reg = &hw_regs->h265d_param; in hal_h265d_vdpu382_start()
996 wr_cfg.size = sizeof(hw_regs->h265d_param); in hal_h265d_vdpu382_start()
997 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_h265d_vdpu382_start()
999 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1005 wr_cfg.reg = &hw_regs->common_addr; in hal_h265d_vdpu382_start()
1006 wr_cfg.size = sizeof(hw_regs->common_addr); in hal_h265d_vdpu382_start()
1007 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS; in hal_h265d_vdpu382_start()
1009 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1015 wr_cfg.reg = &hw_regs->h265d_addr; in hal_h265d_vdpu382_start()
1016 wr_cfg.size = sizeof(hw_regs->h265d_addr); in hal_h265d_vdpu382_start()
1017 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu382_start()
1019 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1025 wr_cfg.reg = &hw_regs->statistic; in hal_h265d_vdpu382_start()
1026 wr_cfg.size = sizeof(hw_regs->statistic); in hal_h265d_vdpu382_start()
1027 wr_cfg.offset = OFFSET_STATISTIC_REGS; in hal_h265d_vdpu382_start()
1029 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()
1035 wr_cfg.reg = &hw_regs->highpoc; in hal_h265d_vdpu382_start()
1036 wr_cfg.size = sizeof(hw_regs->highpoc); in hal_h265d_vdpu382_start()
1037 wr_cfg.offset = OFFSET_POC_HIGHBIT_REGS; in hal_h265d_vdpu382_start()
1039 ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_h265d_vdpu382_start()