| /rockchip-linux_mpp/mpp/vproc/vdpp/ |
| H A D | vdpp.c | 31 dst_reg->common.reg0.sw_vdpp_frm_en = 1; in vdpp_params_to_reg()
34 dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420; in vdpp_params_to_reg()
35 dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap; in vdpp_params_to_reg()
36 dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt; in vdpp_params_to_reg()
37 dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap; in vdpp_params_to_reg()
38 dst_reg->common.reg1.sw_vdpp_dbmsr_en = src_params->dmsr_params.dmsr_enable; in vdpp_params_to_reg()
41 dst_reg->common.reg2.sw_vdpp_working_mode = VDPP_WORK_MODE_VEP; in vdpp_params_to_reg()
44 dst_reg->common.reg4.sw_vdpp_clk_on = 1; in vdpp_params_to_reg()
45 dst_reg->common.reg4.sw_md_clk_on = 1; in vdpp_params_to_reg()
46 dst_reg->common.reg4.sw_dect_clk_on = 1; in vdpp_params_to_reg()
[all …]
|
| H A D | vdpp_common.c | 831 zme->common.reg0.bypass_en = 0; in set_zme_to_vdpp_reg()
832 zme->common.reg0.align_en = 0; in set_zme_to_vdpp_reg()
833 zme->common.reg0.format_in = FMT_YCbCr420_888; in set_zme_to_vdpp_reg()
835 zme->common.reg0.format_out = FMT_YCbCr444_888; in set_zme_to_vdpp_reg()
837 zme->common.reg0.format_out = FMT_YCbCr420_888; in set_zme_to_vdpp_reg()
838 zme->common.reg0.auto_gating_en = 1; in set_zme_to_vdpp_reg()
843 zme->common.reg3.vir_width = zme_params->src_width; in set_zme_to_vdpp_reg()
844 zme->common.reg3.vir_height = zme_params->src_height; in set_zme_to_vdpp_reg()
847 zme->common.reg4.yrgb_xsd_en = yrgb_scl_info.xsd_en; in set_zme_to_vdpp_reg()
848 zme->common.reg4.yrgb_xsu_en = yrgb_scl_info.xsu_en; in set_zme_to_vdpp_reg()
[all …]
|
| H A D | vdpp2.c | 399 dst_reg->common.reg1.sw_dci_en = src_params->hist_cnt_en; in set_hist_to_vdpp2_reg()
1086 dst_reg->common.reg0.sw_vdpp_frm_en = 1; in vdpp2_params_to_reg()
1089 dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420; in vdpp2_params_to_reg()
1090 dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap; in vdpp2_params_to_reg()
1093 dst_reg->common.reg1.sw_vdpp_src_yuv_swap = 1; in vdpp2_params_to_reg()
1095 dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt; in vdpp2_params_to_reg()
1096 dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap; in vdpp2_params_to_reg()
1097 dst_reg->common.reg1.sw_vdpp_dbmsr_en = (src_params->working_mode == VDPP_WORK_MODE_DCI) in vdpp2_params_to_reg()
1102 dst_reg->common.reg2.sw_vdpp_working_mode = src_params->working_mode; in vdpp2_params_to_reg()
1106 dst_reg->common.reg4.sw_vdpp_clk_on = 1; in vdpp2_params_to_reg()
[all …]
|
| /rockchip-linux_mpp/mpp/hal/rkenc/h264e/ |
| H A D | hal_h264e_vepu510.c | 715 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu510_prep()
716 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu510_prep()
717 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu510_prep()
718 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu510_prep()
722 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu510_prep()
723 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu510_prep()
724 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu510_prep()
725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu510_prep()
789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu510_prep()
790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu510_prep()
[all …]
|
| H A D | hal_h264e_vepu511.c | 714 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu511_prep()
715 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu511_prep()
716 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu511_prep()
717 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu511_prep()
721 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu511_prep()
722 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu511_prep()
723 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu511_prep()
724 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu511_prep()
727 reg_frm->common.src_proc.rkfbcd_en = 1; in setup_vepu511_prep()
766 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu511_prep()
[all …]
|
| H A D | CMakeLists.txt | 3 # hal/common for hal_bufs module
4 include_directories(../common/)
5 include_directories(../../common/h264/)
|
| /rockchip-linux_mpp/mpp/hal/rkenc/h265e/ |
| H A D | hal_h265e_vepu510.c | 1315 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1317 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1318 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1327 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1329 reg_frm->common.rc_cfg.rc_en = 1; in vepu510_h265_set_rc_regs()
1330 reg_frm->common.rc_cfg.aq_en = 1; in vepu510_h265_set_rc_regs()
1331 reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32; in vepu510_h265_set_rc_regs()
1333 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_max; in vepu510_h265_set_rc_regs()
1334 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_min; in vepu510_h265_set_rc_regs()
1335 reg_frm->common.rc_tgt.ctu_ebit = ctu_target_bits_mul_16; in vepu510_h265_set_rc_regs()
[all …]
|
| H A D | hal_h265e_vepu511.c | 677 reg_frm->common.enc_pic.cur_frm_ref = 1; in vepu511_h265e_save_pass1_patch()
678 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu511_h265e_save_pass1_patch()
679 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; in vepu511_h265e_save_pass1_patch()
680 reg_frm->common.enc_pic.rec_fbc_dis = 1; in vepu511_h265e_save_pass1_patch()
688 reg_frm->common.sli_splt.sli_splt = 0; in vepu511_h265e_save_pass1_patch()
689 reg_frm->common.enc_pic.slen_fifo = 0; in vepu511_h265e_save_pass1_patch()
706 reg_frm->common.enc_pic.rfpr_compress_mode = 1; in vepu511_h265e_use_pass1_patch()
708 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu511_h265e_use_pass1_patch()
709 reg_frm->common.src_fmt.alpha_swap = 0; in vepu511_h265e_use_pass1_patch()
710 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu511_h265e_use_pass1_patch()
[all …]
|
| /rockchip-linux_mpp/mpp/hal/rkdec/avs2d/ |
| H A D | hal_avs2d_vdpu382.c | 237 Vdpu382RegCommon *common = ®s->common; in init_common_regs() local
239 common->reg009.dec_mode = 3; // AVS2 in init_common_regs()
240 common->reg015.rlc_mode = 0; in init_common_regs()
242 common->reg011.buf_empty_en = 1; in init_common_regs()
243 common->reg011.err_head_fill_e = 1; in init_common_regs()
244 common->reg011.err_colmv_fill_e = 1; in init_common_regs()
246 common->reg010.dec_e = 1; in init_common_regs()
248 common->reg013.h26x_error_mode = 0; in init_common_regs()
249 common->reg021.inter_error_prc_mode = 0; in init_common_regs()
250 common->reg021.error_deb_en = 0; in init_common_regs()
[all …]
|
| H A D | hal_avs2d_rkv.c | 237 Vdpu34xRegCommon *common = ®s->common; in init_common_regs() local
239 common->reg009.dec_mode = 3; // AVS2 in init_common_regs()
240 common->reg015.rlc_mode = 0; in init_common_regs()
242 common->reg011.buf_empty_en = 1; in init_common_regs()
243 common->reg011.dec_timeout_e = 1; in init_common_regs()
245 common->reg010.dec_e = 1; in init_common_regs()
247 common->reg013.h26x_error_mode = 0; in init_common_regs()
248 common->reg013.colmv_error_mode = 0; in init_common_regs()
249 common->reg013.h26x_streamd_error_mode = 0; in init_common_regs()
250 common->reg021.inter_error_prc_mode = 0; in init_common_regs()
[all …]
|
| /rockchip-linux_mpp/mpp/hal/rkdec/h264d/ |
| H A D | hal_h264d_vdpu34x.c | 535 Vdpu34xRegCommon *common = ®s->common; in set_registers() local
540 common->reg016_str_len = p_hal->strm_len; in set_registers()
541 common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag; in set_registers()
542 common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0; in set_registers()
543 common->reg028.sw_poc_arb_flag = 0; in set_registers()
561 common->reg012.fbc_e = 1; in set_registers()
562 common->reg018.y_hor_virstride = fbc_hdr_stride / 16; in set_registers()
563 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16; in set_registers()
564 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; in set_registers()
566 common->reg012.fbc_e = 0; in set_registers()
[all …]
|
| H A D | hal_h264d_vdpu382.c | 542 Vdpu382RegCommon *common = ®s->common; in set_registers() local
547 common->reg016_str_len = p_hal->strm_len; in set_registers()
548 common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag; in set_registers()
549 common->reg012.colmv_compress_en = in set_registers()
551 common->reg012.info_collect_en = 1; in set_registers()
552 common->reg013.h26x_error_mode = ctx->err_ref_hack ? 0 : 1; in set_registers()
570 common->reg012.fbc_e = 1; in set_registers()
571 common->reg018.y_hor_virstride = fbc_hdr_stride / 16; in set_registers()
572 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16; in set_registers()
573 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; in set_registers()
[all …]
|
| /rockchip-linux_mpp/mpp/hal/rkdec/h265d/ |
| H A D | hal_h265d_vdpu382.c | 420 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v382_output_pps_packet()
514 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
523 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
736 hw_regs->common.reg013.h26x_error_mode = 1; in hal_h265d_vdpu382_gen_regs()
737 hw_regs->common.reg021.error_deb_en = 1; in hal_h265d_vdpu382_gen_regs()
738 hw_regs->common.reg021.inter_error_prc_mode = 0; in hal_h265d_vdpu382_gen_regs()
739 hw_regs->common.reg021.error_intra_mode = 1; in hal_h265d_vdpu382_gen_regs()
741 hw_regs->common.reg017.slice_num = dxva_cxt->slice_count; in hal_h265d_vdpu382_gen_regs()
750 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu382_gen_regs()
751 hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
[all …]
|
| H A D | hal_h265d_vdpu34x.c | 427 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v345_output_pps_packet()
742 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
751 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
945 hw_regs->common.reg013.h26x_error_mode = 1; in hal_h265d_vdpu34x_gen_regs()
946 hw_regs->common.reg013.h26x_streamd_error_mode = 1; in hal_h265d_vdpu34x_gen_regs()
947 hw_regs->common.reg013.colmv_error_mode = 1; in hal_h265d_vdpu34x_gen_regs()
948 hw_regs->common.reg021.error_deb_en = 1; in hal_h265d_vdpu34x_gen_regs()
949 hw_regs->common.reg021.inter_error_prc_mode = 0; in hal_h265d_vdpu34x_gen_regs()
950 hw_regs->common.reg021.error_intra_mode = 1; in hal_h265d_vdpu34x_gen_regs()
952 hw_regs->common.reg017.slice_num = dxva_cxt->slice_count; in hal_h265d_vdpu34x_gen_regs()
[all …]
|
| /rockchip-linux_mpp/mpp/hal/rkdec/vp9d/ |
| H A D | hal_vp9d_vdpu382.c | 326 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()
334 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()
504 vp9_hw_regs->common.reg028.sw_poc_arb_flag = 1; in hal_vp9d_vdpu382_gen_regs()
599 vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = frame_ctx_id + 1; in hal_vp9d_vdpu382_gen_regs()
604 vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = 0; in hal_vp9d_vdpu382_gen_regs()
611 vp9_hw_regs->common.reg028.swreg_vp9_wr_prob_idx = frame_ctx_id + 1; in hal_vp9d_vdpu382_gen_regs()
619 …vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress… in hal_vp9d_vdpu382_gen_regs()
620 vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type; in hal_vp9d_vdpu382_gen_regs()
621 vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec in hal_vp9d_vdpu382_gen_regs()
622 vp9_hw_regs->common.reg016_str_len = ((stream_len + 15) & (~15)) + 0x80; in hal_vp9d_vdpu382_gen_regs()
[all …]
|
| H A D | hal_vp9d_vdpu34x.c | 317 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()
323 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()
585 vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = frame_ctx_id + 1; in hal_vp9d_vdpu34x_gen_regs()
590 vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = 0; in hal_vp9d_vdpu34x_gen_regs()
601 vp9_hw_regs->common.reg028.swreg_vp9_wr_prob_idx = frame_ctx_id + 1; in hal_vp9d_vdpu34x_gen_regs()
609 …vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress… in hal_vp9d_vdpu34x_gen_regs()
610 vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type; in hal_vp9d_vdpu34x_gen_regs()
611 vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec in hal_vp9d_vdpu34x_gen_regs()
612 vp9_hw_regs->common.reg016_str_len = ((stream_len + 15) & (~15)) + 0x80; in hal_vp9d_vdpu34x_gen_regs()
616 aglin_offset = vp9_hw_regs->common.reg016_str_len - stream_len; in hal_vp9d_vdpu34x_gen_regs()
[all …]
|
| /rockchip-linux_mpp/ |
| H A D | Android.bp | 30 "mpp/common",
32 "mpp/codec/dec/common",
37 "mpp/hal/common",
38 "mpp/hal/common/av1",
39 "mpp/hal/common/h265",
40 "mpp/hal/common/h264",
41 "mpp/hal/common/jpeg",
42 "mpp/hal/rkenc/common",
48 "mpp/hal/vpu/common",
90 "mpp/hal/common/**/*.c",
[all …]
|
| /rockchip-linux_mpp/mpp/hal/common/ |
| H A D | CMakeLists.txt | 5 # add hal common file
13 set_target_properties(hal_common PROPERTIES FOLDER "mpp/hal/common")
|
| /rockchip-linux_mpp/mpp/hal/rkdec/av1d/ |
| H A D | CMakeLists.txt | 4 include_directories(../../common/av1)
7 ../../common/av1/hal_av1d_common.h
|
| /rockchip-linux_mpp/mpp/hal/vpu/jpege/ |
| H A D | CMakeLists.txt | 4 include_directories(../common/)
5 include_directories(../../common/jpeg/)
|
| /rockchip-linux_mpp/mpp/hal/vpu/av1d/ |
| H A D | CMakeLists.txt | 4 include_directories(../../common/av1)
8 ../../common/av1/hal_av1d_common.h
|
| /rockchip-linux_mpp/mpp/hal/vpu/h264e/ |
| H A D | CMakeLists.txt | 3 include_directories(../../common/h264/)
5 include_directories(../common/)
|
| /rockchip-linux_mpp/mpp/hal/rkenc/jpege/ |
| H A D | CMakeLists.txt | 3 include_directories(../../common/jpeg/)
4 include_directories(../common/)
|
| /rockchip-linux_mpp/mpp/hal/ |
| H A D | CMakeLists.txt | 3 include_directories(common)
12 add_subdirectory(common)
|
| /rockchip-linux_mpp/mpp/hal/common/h265/ |
| H A D | CMakeLists.txt | 4 include_directories(../../rkenc/common/)
10 # hal h265 encoder common
|