237     Vdpu34xRegCommon *common = &regs->common;  in init_common_regs()  local
239     common->reg009.dec_mode = 3;  // AVS2  in init_common_regs()
240     common->reg015.rlc_mode = 0;  in init_common_regs()
242     common->reg011.buf_empty_en = 1;  in init_common_regs()
243     common->reg011.dec_timeout_e = 1;  in init_common_regs()
245     common->reg010.dec_e = 1;  in init_common_regs()
247     common->reg013.h26x_error_mode = 0;  in init_common_regs()
248     common->reg013.colmv_error_mode = 0;  in init_common_regs()
249     common->reg013.h26x_streamd_error_mode = 0;  in init_common_regs()
250     common->reg021.inter_error_prc_mode = 0;  in init_common_regs()
251     common->reg021.error_deb_en = 0;  in init_common_regs()
252     common->reg021.error_intra_mode = 0;  in init_common_regs()
255         common->reg024.cabac_err_en_lowbits = 0;  in init_common_regs()
256         common->reg025.cabac_err_en_highbits = 0;  in init_common_regs()
257         common->reg026.swreg_block_gating_e = 0xfffef;  in init_common_regs()
259         common->reg024.cabac_err_en_lowbits = 0xffffffdf;  in init_common_regs()
260         common->reg025.cabac_err_en_highbits = 0x3dffffff;  in init_common_regs()
261         common->reg026.swreg_block_gating_e = 0xfffff;  in init_common_regs()
264     common->reg026.reg_cfg_gating_en = 1;  in init_common_regs()
265     common->reg032_timeout_threshold = 0x3fffff;  in init_common_regs()
267     common->reg011.dec_clkgate_e = 1;  in init_common_regs()
268     common->reg011.dec_e_strmd_clkgate_dis = 0;  in init_common_regs()
269     common->reg011.dec_timeout_e = 1;  in init_common_regs()
271     common->reg013.timeout_mode = 1;  in init_common_regs()
272     common->reg013.stmerror_waitdecfifo_empty = 1;  in init_common_regs()
273     common->reg012.colmv_compress_en = COLMV_COMPRESS_EN;  in init_common_regs()
274     common->reg012.wr_ddr_align_en = 1;  in init_common_regs()
275     common->reg012.info_collect_en = 1;  in init_common_regs()
276     common->reg012.error_info_en = 0;  in init_common_regs()
337     Vdpu34xRegCommon *common = &p_regs->common;  in fill_registers()  local
359             common->reg012.fbc_e = 1;  in fill_registers()
360             common->reg018.y_hor_virstride = fbc_hdr_stride / 16;  in fill_registers()
361             common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;  in fill_registers()
362             common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;  in fill_registers()
364             common->reg012.fbc_e = 0;  in fill_registers()
365             common->reg018.y_hor_virstride = hor_virstride / 16;  in fill_registers()
366             common->reg019.uv_hor_virstride = hor_virstride / 16;  in fill_registers()
367             common->reg020_y_virstride.y_virstride = y_virstride / 16;  in fill_registers()
369 …common->reg013.cur_pic_is_idr = (pp->picture_type == 0 || pp->picture_type == 4 || pp->picture_typ…  in fill_registers()
468         common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;  in fill_registers()
659         regs->common.reg012.scanlist_addr_valid_en = 1;  in hal_avs2d_rkv_gen_regs()
710     vdpu34x_setup_statistic(&regs->common, &regs->statistic);  in hal_avs2d_rkv_gen_regs()
738                 ((RK_U32 *)&regs->common)[i]);  in hal_avs2d_rkv_dump_reg_write()
826         wr_cfg.reg = &regs->common;  in hal_avs2d_rkv_start()
827         wr_cfg.size = sizeof(regs->common);  in hal_avs2d_rkv_start()