Lines Matching refs:common
1315 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1317 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1318 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1327 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; in vepu510_h265_set_rc_regs()
1329 reg_frm->common.rc_cfg.rc_en = 1; in vepu510_h265_set_rc_regs()
1330 reg_frm->common.rc_cfg.aq_en = 1; in vepu510_h265_set_rc_regs()
1331 reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32; in vepu510_h265_set_rc_regs()
1333 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_max; in vepu510_h265_set_rc_regs()
1334 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_min; in vepu510_h265_set_rc_regs()
1335 reg_frm->common.rc_tgt.ctu_ebit = ctu_target_bits_mul_16; in vepu510_h265_set_rc_regs()
1338 reg_frm->common.rc_qp.rc_qp_range = 0; in vepu510_h265_set_rc_regs()
1340 reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ? in vepu510_h265_set_rc_regs()
1357 reg_frm->common.enc_pic.pic_qp = fqp_min; in vepu510_h265_set_rc_regs()
1359 reg_frm->common.rc_qp.rc_qp_range = 0; in vepu510_h265_set_rc_regs()
1413 reg_frm->common.src_fmt.src_cfmt = fmt->format; in vepu510_h265_set_pp_regs()
1414 reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap; in vepu510_h265_set_pp_regs()
1415 reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap; in vepu510_h265_set_pp_regs()
1417 …reg_frm->common.src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 … in vepu510_h265_set_pp_regs()
1419 reg_frm->common.src_proc.src_mirr = prep_cfg->mirroring > 0; in vepu510_h265_set_pp_regs()
1420 reg_frm->common.src_proc.src_rot = prep_cfg->rotation; in vepu510_h265_set_pp_regs()
1421 reg_frm->common.src_proc.tile4x4_en = 0; in vepu510_h265_set_pp_regs()
1425 reg_frm->common.src_proc.tile4x4_en = 1; in vepu510_h265_set_pp_regs()
1452 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888) in vepu510_h265_set_pp_regs()
1454 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR888) in vepu510_h265_set_pp_regs()
1456 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 || in vepu510_h265_set_pp_regs()
1457 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 || in vepu510_h265_set_pp_regs()
1458 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422) in vepu510_h265_set_pp_regs()
1462 stridec = (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP || in vepu510_h265_set_pp_regs()
1463 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP || in vepu510_h265_set_pp_regs()
1464 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV444P) ? in vepu510_h265_set_pp_regs()
1467 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV444SP) in vepu510_h265_set_pp_regs()
1470 if (reg_frm->common.src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) { in vepu510_h265_set_pp_regs()
1475 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu510_h265_set_pp_regs()
1476 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu510_h265_set_pp_regs()
1477 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu510_h265_set_pp_regs()
1479 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu510_h265_set_pp_regs()
1480 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu510_h265_set_pp_regs()
1481 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu510_h265_set_pp_regs()
1483 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu510_h265_set_pp_regs()
1484 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu510_h265_set_pp_regs()
1485 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in vepu510_h265_set_pp_regs()
1487 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in vepu510_h265_set_pp_regs()
1488 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu510_h265_set_pp_regs()
1489 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in vepu510_h265_set_pp_regs()
1494 reg_frm->common.src_strd0.src_strd0 = stridey; in vepu510_h265_set_pp_regs()
1495 reg_frm->common.src_strd1.src_strd1 = stridec; in vepu510_h265_set_pp_regs()
1537 regs->common.enc_pic.num_pic_tot_cur_hevc = syn->sp.tot_poc_num; in vepu510_h265_set_slice_regs()
1594 regs->common.me_rnge.cime_srch_dwnh = 15; in vepu510_h265_set_me_regs()
1595 regs->common.me_rnge.cime_srch_uph = 15; in vepu510_h265_set_me_regs()
1596 regs->common.me_rnge.cime_srch_rgtw = 12; in vepu510_h265_set_me_regs()
1597 regs->common.me_rnge.cime_srch_lftw = 12; in vepu510_h265_set_me_regs()
1598 regs->common.me_cfg.rme_srch_h = 3; in vepu510_h265_set_me_regs()
1599 regs->common.me_cfg.rme_srch_v = 3; in vepu510_h265_set_me_regs()
1601 regs->common.me_cfg.srgn_max_num = 54; in vepu510_h265_set_me_regs()
1602 regs->common.me_cfg.cime_dist_thre = 1024; in vepu510_h265_set_me_regs()
1603 regs->common.me_cfg.rme_dis = 0; in vepu510_h265_set_me_regs()
1604 regs->common.me_cfg.fme_dis = 0; in vepu510_h265_set_me_regs()
1605 regs->common.me_rnge.dlt_frm_num = 0x1; in vepu510_h265_set_me_regs()
1610 regs->common.me_cach.colmv_load_hevc = 0; in vepu510_h265_set_me_regs()
1612 regs->common.me_cach.colmv_load_hevc = 1; in vepu510_h265_set_me_regs()
1614 regs->common.me_cach.colmv_stor_hevc = 1; in vepu510_h265_set_me_regs()
1617 regs->common.me_cach.cime_zero_thre = (ctx->cfg->tune.scene_mode == in vepu510_h265_set_me_regs()
1619 regs->common.me_cach.fme_prefsu_en = 0; in vepu510_h265_set_me_regs()
1632 regs->common.adr_src0 = mpp_buffer_get_fd(enc_task->input); in vepu510_h265_set_hw_address()
1633 regs->common.adr_src1 = regs->common.adr_src0; in vepu510_h265_set_hw_address()
1634 regs->common.adr_src2 = regs->common.adr_src0; in vepu510_h265_set_hw_address()
1640 regs->common.rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]); in vepu510_h265_set_hw_address()
1641 regs->common.rfpw_b_addr = regs->common.rfpw_h_addr; in vepu510_h265_set_hw_address()
1644 regs->common.rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]); in vepu510_h265_set_hw_address()
1645 regs->common.rfpr_b_addr = regs->common.rfpr_h_addr; in vepu510_h265_set_hw_address()
1646 regs->common.colmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]); in vepu510_h265_set_hw_address()
1647 regs->common.colmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]); in vepu510_h265_set_hw_address()
1648 regs->common.dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]); in vepu510_h265_set_hw_address()
1649 regs->common.dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]); in vepu510_h265_set_hw_address()
1654 regs->common.enc_pic.mei_stor = 1; in vepu510_h265_set_hw_address()
1655 regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf); in vepu510_h265_set_hw_address()
1657 regs->common.enc_pic.mei_stor = 0; in vepu510_h265_set_hw_address()
1658 regs->common.meiw_addr = 0; in vepu510_h265_set_hw_address()
1661 regs->common.bsbt_addr = mpp_buffer_get_fd(enc_task->output); in vepu510_h265_set_hw_address()
1663 regs->common.bsbb_addr = regs->common.bsbt_addr; in vepu510_h265_set_hw_address()
1664 regs->common.bsbr_addr = regs->common.bsbt_addr; in vepu510_h265_set_hw_address()
1665 regs->common.adr_bsbs = regs->common.bsbt_addr; in vepu510_h265_set_hw_address()
1667 regs->common.rfpt_h_addr = 0xffffffff; in vepu510_h265_set_hw_address()
1668 regs->common.rfpb_h_addr = 0; in vepu510_h265_set_hw_address()
1669 regs->common.rfpt_b_addr = 0xffffffff; in vepu510_h265_set_hw_address()
1670 regs->common.adr_rfpb_b = 0; in vepu510_h265_set_hw_address()
1675 regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in vepu510_h265_set_hw_address()
1676 regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in vepu510_h265_set_hw_address()
1679 regs->common.adr_smear_rd = mpp_buffer_get_fd(ref_buf->buf[3]); in vepu510_h265_set_hw_address()
1680 regs->common.adr_smear_wr = mpp_buffer_get_fd(recon_buf->buf[3]); in vepu510_h265_set_hw_address()
1700 reg_frm->common.enc_pic.cur_frm_ref = 1; in vepu510_h265e_save_pass1_patch()
1701 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu510_h265e_save_pass1_patch()
1702 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; in vepu510_h265e_save_pass1_patch()
1703 reg_frm->common.enc_pic.rec_fbc_dis = 1; in vepu510_h265e_save_pass1_patch()
1711 reg_frm->common.sli_splt.sli_splt = 0; in vepu510_h265e_save_pass1_patch()
1712 reg_frm->common.enc_pic.slen_fifo = 0; in vepu510_h265e_save_pass1_patch()
1728 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu510_h265e_use_pass1_patch()
1729 reg_frm->common.src_fmt.alpha_swap = 0; in vepu510_h265e_use_pass1_patch()
1730 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu510_h265e_use_pass1_patch()
1731 reg_frm->common.src_fmt.out_fmt = 1; in vepu510_h265e_use_pass1_patch()
1732 reg_frm->common.src_fmt.src_rcne = 1; in vepu510_h265e_use_pass1_patch()
1734 reg_frm->common.src_strd0.src_strd0 = hor_stride; in vepu510_h265e_use_pass1_patch()
1735 reg_frm->common.src_strd1.src_strd1 = 3 * hor_stride; in vepu510_h265e_use_pass1_patch()
1737 reg_frm->common.src_proc.src_mirr = 0; in vepu510_h265e_use_pass1_patch()
1738 reg_frm->common.src_proc.src_rot = 0; in vepu510_h265e_use_pass1_patch()
1740 reg_frm->common.adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1); in vepu510_h265e_use_pass1_patch()
1741 reg_frm->common.adr_src1 = reg_frm->common.adr_src0; in vepu510_h265e_use_pass1_patch()
1742 reg_frm->common.adr_src2 = 0; in vepu510_h265e_use_pass1_patch()
1763 reg_frm->common.ebufb_addr = fd; in setup_vepu510_ext_line_buf()
1764 reg_frm->common.ebuft_addr = fd; in setup_vepu510_ext_line_buf()
1767 reg_frm->common.ebufb_addr = 0; in setup_vepu510_ext_line_buf()
1768 reg_frm->common.ebuft_addr = 0; in setup_vepu510_ext_line_buf()
1801 reg_frm->common.dual_core.dchs_txid = ctx->curr_idx; in setup_vepu510_dual_core()
1802 reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx; in setup_vepu510_dual_core()
1803 reg_frm->common.dual_core.dchs_txe = 1; in setup_vepu510_dual_core()
1804 reg_frm->common.dual_core.dchs_rxe = dchs_rxe; in setup_vepu510_dual_core()
1805 reg_frm->common.dual_core.dchs_ofst = dchs_ofst; in setup_vepu510_dual_core()
1806 reg_frm->common.dual_core.dchs_dly = dchs_dly; in setup_vepu510_dual_core()
1823 regs->reg_frm.common.sli_splt.sli_splt = 0; in setup_vepu510_split()
1824 regs->reg_frm.common.sli_splt.sli_splt_mode = 0; in setup_vepu510_split()
1825 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1826 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 0; in setup_vepu510_split()
1827 regs->reg_frm.common.sli_splt.sli_flsh = 0; in setup_vepu510_split()
1828 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu510_split()
1830 regs->reg_frm.common.sli_byte.sli_splt_byte = 0; in setup_vepu510_split()
1831 regs->reg_frm.common.enc_pic.slen_fifo = 0; in setup_vepu510_split()
1834 regs->reg_frm.common.sli_splt.sli_splt = 1; in setup_vepu510_split()
1835 regs->reg_frm.common.sli_splt.sli_splt_mode = 0; in setup_vepu510_split()
1836 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1837 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500; in setup_vepu510_split()
1838 regs->reg_frm.common.sli_splt.sli_flsh = 1; in setup_vepu510_split()
1839 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu510_split()
1841 regs->reg_frm.common.sli_byte.sli_splt_byte = cfg->split_arg; in setup_vepu510_split()
1842 regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu510_split()
1843 regs->reg_ctl.int_en.vslc_done_en = regs->reg_frm.common.enc_pic.slen_fifo ; in setup_vepu510_split()
1855 regs->reg_frm.common.sli_splt.sli_splt = 1; in setup_vepu510_split()
1856 regs->reg_frm.common.sli_splt.sli_splt_mode = 1; in setup_vepu510_split()
1857 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1858 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500; in setup_vepu510_split()
1859 regs->reg_frm.common.sli_splt.sli_flsh = 1; in setup_vepu510_split()
1860 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu510_split()
1862 regs->reg_frm.common.sli_byte.sli_splt_byte = 0; in setup_vepu510_split()
1863 regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu510_split()
1865 (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN))) in setup_vepu510_split()
1996 reg_frm->common.enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v510_gen_regs()
1997 reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v510_gen_regs()
1999 reg_frm->common.enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in hal_h265e_v510_gen_regs()
2000 reg_frm->common.src_fill.pic_hfill = (syn->pp.pic_height & 0x7) in hal_h265e_v510_gen_regs()
2003 reg_frm->common.enc_pic.enc_stnd = 1; //H265 in hal_h265e_v510_gen_regs()
2004 …reg_frm->common.enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be… in hal_h265e_v510_gen_regs()
2005 reg_frm->common.enc_pic.bs_scp = 1; in hal_h265e_v510_gen_regs()
2006 reg_frm->common.enc_pic.log2_ctu_num_hevc = mpp_ceil_log2(pic_wd32 * pic_h32); in hal_h265e_v510_gen_regs()
2008 reg_frm->common.src_proc.src_mirr = 0; in hal_h265e_v510_gen_regs()
2009 reg_frm->common.src_proc.src_rot = 0; in hal_h265e_v510_gen_regs()
2010 reg_frm->common.src_proc.tile4x4_en = 0; in hal_h265e_v510_gen_regs()