Lines Matching refs:common
420 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v382_output_pps_packet()
514 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
523 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()
736 hw_regs->common.reg013.h26x_error_mode = 1; in hal_h265d_vdpu382_gen_regs()
737 hw_regs->common.reg021.error_deb_en = 1; in hal_h265d_vdpu382_gen_regs()
738 hw_regs->common.reg021.inter_error_prc_mode = 0; in hal_h265d_vdpu382_gen_regs()
739 hw_regs->common.reg021.error_intra_mode = 1; in hal_h265d_vdpu382_gen_regs()
741 hw_regs->common.reg017.slice_num = dxva_cxt->slice_count; in hal_h265d_vdpu382_gen_regs()
750 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu382_gen_regs()
751 hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
752 hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4; in hal_h265d_vdpu382_gen_regs()
753 hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; in hal_h265d_vdpu382_gen_regs()
755 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu382_gen_regs()
756 hw_regs->common.reg018.y_hor_virstride = stride_y >> 4; in hal_h265d_vdpu382_gen_regs()
757 hw_regs->common.reg019.uv_hor_virstride = stride_uv >> 4; in hal_h265d_vdpu382_gen_regs()
758 hw_regs->common.reg020_y_virstride.y_virstride = virstrid_y >> 4; in hal_h265d_vdpu382_gen_regs()
799 hw_regs->common.reg016_str_len = ((dxva_cxt->bitstream_size + 15) in hal_h265d_vdpu382_gen_regs()
801 hw_regs->common.reg016_str_len = stream_buf_size > hw_regs->common.reg016_str_len ? in hal_h265d_vdpu382_gen_regs()
802 hw_regs->common.reg016_str_len : stream_buf_size; in hal_h265d_vdpu382_gen_regs()
804 aglin_offset = hw_regs->common.reg016_str_len - dxva_cxt->bitstream_size; in hal_h265d_vdpu382_gen_regs()
809 hw_regs->common.reg010.dec_e = 1; in hal_h265d_vdpu382_gen_regs()
810 hw_regs->common.reg012.colmv_compress_en = reg_ctx->hw_info ? in hal_h265d_vdpu382_gen_regs()
813 hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff; in hal_h265d_vdpu382_gen_regs()
814 hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff; in hal_h265d_vdpu382_gen_regs()
816 hw_regs->common.reg011.dec_clkgate_e = 1; in hal_h265d_vdpu382_gen_regs()
817 hw_regs->common.reg011.err_head_fill_e = 1; in hal_h265d_vdpu382_gen_regs()
818 hw_regs->common.reg011.err_colmv_fill_e = 1; in hal_h265d_vdpu382_gen_regs()
820 hw_regs->common.reg026.inter_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
821 hw_regs->common.reg026.filterd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
822 hw_regs->common.reg026.strmd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
823 hw_regs->common.reg026.mcp_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
824 hw_regs->common.reg026.busifd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
825 hw_regs->common.reg026.dec_ctrl_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
826 hw_regs->common.reg026.intra_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
827 hw_regs->common.reg026.mc_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
828 hw_regs->common.reg026.transd_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
829 hw_regs->common.reg026.sram_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
830 hw_regs->common.reg026.cru_auto_gating_e = 1; in hal_h265d_vdpu382_gen_regs()
831 hw_regs->common.reg026.reg_cfg_gating_en = 1; in hal_h265d_vdpu382_gen_regs()
832 hw_regs->common.reg032_timeout_threshold = 0x3ffff; in hal_h265d_vdpu382_gen_regs()
860 hw_regs->common.reg021.error_intra_mode = 0; in hal_h265d_vdpu382_gen_regs()
914 hw_regs->common.reg013.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag; in hal_h265d_vdpu382_gen_regs()
916 hw_regs->common.reg011.buf_empty_en = 1; in hal_h265d_vdpu382_gen_regs()
933 vdpu382_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->common); in hal_h265d_vdpu382_gen_regs()
937 hw_regs->common.reg012.scale_down_en = 0; in hal_h265d_vdpu382_gen_regs()
940 vdpu382_setup_statistic(&hw_regs->common, &hw_regs->statistic); in hal_h265d_vdpu382_gen_regs()
985 wr_cfg.reg = &hw_regs->common; in hal_h265d_vdpu382_start()
986 wr_cfg.size = sizeof(hw_regs->common); in hal_h265d_vdpu382_start()