1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "vdpp_common"
7
8 #include "vdpp_common.h"
9
10 const char *working_mode_name[] = {
11 NULL,
12 NULL,
13 "VEP MODE",
14 "DCI HIST MODE",
15 };
16
17 #define VDPP_SET_ZME_COEF(index, row, col) \
18 do { \
19 zme->yrgb_hor_coe.reg##index.yrgb_hor_coe##row##_##col = \
20 yrgb_scl_info.xscl_zme_coe[row][col]; \
21 zme->yrgb_ver_coe.reg##index.yrgb_ver_coe##row##_##col = \
22 yrgb_scl_info.yscl_zme_coe[row][col]; \
23 zme->cbcr_hor_coe.reg##index.cbcr_hor_coe##row##_##col = \
24 cbcr_scl_info.xscl_zme_coe[row][col]; \
25 zme->cbcr_ver_coe.reg##index.cbcr_ver_coe##row##_##col = \
26 cbcr_scl_info.yscl_zme_coe[row][col]; \
27 } while (0);
28
29 static RK_U16 vdpp_scale_threshold[] = {
30 2667, 2000, 1500, 1000, 833, 700, 500, 330, 250,
31 };
32
33 static RK_S16 g_zme_tap8_coeff[11][17][8] = {
34 //>=2.667
35 {
36 { 4, -12, 20, 488, 20, -12, 4, 0},
37 { 4, -8, 8, 484, 36, -16, 4, 0},
38 { 4, -4, -4, 476, 52, -20, 8, 0},
39 { 0, 0, -16, 480, 68, -28, 8, 0},
40 { 0, 4, -24, 472, 84, -32, 8, 0},
41 { 0, 4, -36, 468, 100, -36, 12, 0},
42 { 0, 8, -44, 456, 120, -40, 12, 0},
43 { 0, 12, -52, 448, 136, -44, 12, 0},
44 { 0, 12, -56, 436, 156, -48, 16, -4},
45 { -4, 16, -60, 424, 176, -52, 16, -4},
46 { -4, 16, -64, 412, 196, -56, 16, -4},
47 { -4, 16, -68, 400, 216, -60, 16, -4},
48 { -4, 20, -72, 380, 236, -64, 20, -4},
49 { -4, 20, -72, 364, 256, -68, 20, -4},
50 { -4, 20, -72, 348, 272, -68, 20, -4},
51 { -4, 20, -72, 332, 292, -72, 20, -4},
52 { -4, 20, -72, 312, 312, -72, 20, -4},
53 },
54 //>=2
55 {
56 { 8, -24, 44, 456, 44, -24, 8, 0},
57 { 8, -20, 28, 460, 56, -28, 8, 0},
58 { 8, -16, 16, 452, 72, -32, 12, 0},
59 { 4, -12, 8, 448, 88, -36, 12, 0},
60 { 4, -8, -4, 444, 104, -40, 12, 0},
61 { 4, -8, -16, 444, 120, -44, 12, 0},
62 { 4, -4, -24, 432, 136, -48, 16, 0},
63 { 4, 0, -32, 428, 152, -52, 16, -4},
64 { 0, 4, -40, 424, 168, -56, 16, -4},
65 { 0, 4, -44, 412, 188, -60, 16, -4},
66 { 0, 8, -52, 400, 204, -60, 16, -4},
67 { 0, 8, -56, 388, 224, -64, 16, -4},
68 { 0, 12, -60, 372, 240, -64, 16, -4},
69 { 0, 12, -64, 356, 264, -68, 16, -4},
70 { 0, 12, -64, 340, 280, -68, 16, -4},
71 { 0, 16, -68, 324, 296, -68, 16, -4},
72 { 0, 16, -68, 308, 308, -68, 16, 0},
73 },
74 //>=1.5
75 {
76 { 12, -32, 64, 424, 64, -32, 12, 0},
77 { 8, -32, 52, 432, 76, -36, 12, 0},
78 { 8, -28, 40, 432, 88, -40, 12, 0},
79 { 8, -24, 28, 428, 104, -44, 12, 0},
80 { 8, -20, 16, 424, 120, -48, 12, 0},
81 { 8, -16, 8, 416, 132, -48, 12, 0},
82 { 4, -16, -4, 420, 148, -52, 12, 0},
83 { 4, -12, -12, 412, 164, -56, 12, 0},
84 { 4, -8, -20, 400, 180, -56, 12, 0},
85 { 4, -4, -28, 388, 196, -56, 12, 0},
86 { 4, -4, -32, 380, 212, -60, 12, 0},
87 { 4, 0, -40, 368, 228, -60, 12, 0},
88 { 4, 0, -44, 356, 244, -60, 12, 0},
89 { 0, 4, -48, 344, 260, -60, 12, 0},
90 { 0, 4, -52, 332, 276, -60, 12, 0},
91 { 0, 8, -56, 320, 292, -60, 8, 0},
92 { 0, 8, -56, 304, 304, -56, 8, 0},
93 },
94 //>1
95 {
96 { 12, -40, 84, 400, 84, -40, 12, 0},
97 { 12, -40, 72, 404, 96, -44, 12, 0},
98 { 12, -36, 60, 404, 108, -48, 12, 0},
99 { 8, -32, 48, 404, 120, -48, 12, 0},
100 { 8, -32, 36, 404, 136, -52, 12, 0},
101 { 8, -28, 28, 396, 148, -52, 12, 0},
102 { 8, -24, 16, 392, 160, -52, 12, 0},
103 { 8, -20, 8, 384, 176, -56, 12, 0},
104 { 8, -20, 0, 384, 188, -56, 8, 0},
105 { 8, -16, -8, 372, 204, -56, 8, 0},
106 { 8, -12, -16, 364, 216, -56, 8, 0},
107 { 4, -12, -20, 356, 232, -56, 8, 0},
108 { 4, -8, -28, 348, 244, -56, 8, 0},
109 { 4, -8, -32, 332, 264, -52, 4, 0},
110 { 4, -4, -36, 324, 272, -52, 4, 0},
111 { 4, 0, -40, 312, 280, -48, 0, 4},
112 { 4, 0, -44, 296, 296, -44, 0, 4},
113 },
114 //==1
115 {
116 { 0, 0, 0, 511, 0, 0, 0, 0 },
117 { -1, 3, -12, 511, 14, -4, 1, 0 },
118 { -2, 6, -23, 509, 28, -8, 2, 0 },
119 { -2, 9, -33, 503, 44, -12, 3, 0 },
120 { -3, 11, -41, 496, 61, -16, 4, 0 },
121 { -3, 13, -48, 488, 79, -21, 5, -1 },
122 { -3, 14, -54, 477, 98, -25, 7, -2 },
123 { -4, 16, -59, 465, 118, -30, 8, -2 },
124 { -4, 17, -63, 451, 138, -35, 9, -1 },
125 { -4, 18, -66, 437, 158, -39, 10, -2 },
126 { -4, 18, -68, 421, 180, -44, 11, -2 },
127 { -4, 18, -69, 404, 201, -48, 13, -3 },
128 { -4, 18, -70, 386, 222, -52, 14, -2 },
129 { -4, 18, -70, 368, 244, -56, 15, -3 },
130 { -4, 18, -69, 348, 265, -59, 16, -3 },
131 { -4, 18, -67, 329, 286, -63, 16, -3 },
132 { -3, 17, -65, 307, 307, -65, 17, -3 },
133 },
134 //>=0.833
135 {
136 { -16, 0, 145, 254, 145, 0, -16, 0 },
137 { -16, -2, 140, 253, 151, 3, -17, 0 },
138 { -15, -5, 135, 253, 157, 5, -18, 0 },
139 { -14, -7, 129, 252, 162, 8, -18, 0 },
140 { -13, -9, 123, 252, 167, 11, -19, 0 },
141 { -13, -11, 118, 250, 172, 15, -19, 0 },
142 { -12, -12, 112, 250, 177, 18, -20, -1 },
143 { -11, -14, 107, 247, 183, 21, -20, -1 },
144 { -10, -15, 101, 245, 188, 25, -21, -1 },
145 { -9, -16, 96, 243, 192, 29, -21, -2 },
146 { -8, -18, 90, 242, 197, 33, -22, -2 },
147 { -8, -19, 85, 239, 202, 37, -22, -2 },
148 { -7, -19, 80, 236, 206, 41, -22, -3 },
149 { -7, -20, 75, 233, 210, 46, -22, -3 },
150 { -6, -21, 69, 230, 215, 50, -22, -3 },
151 { -5, -21, 65, 226, 219, 55, -22, -5 },
152 { -5, -21, 60, 222, 222, 60, -21, -5 },
153 },
154 //>=0.7
155 {
156 { -16, 0, 145, 254, 145, 0, -16, 0 },
157 { -16, -2, 140, 253, 151, 3, -17, 0 },
158 { -15, -5, 135, 253, 157, 5, -18, 0 },
159 { -14, -7, 129, 252, 162, 8, -18, 0 },
160 { -13, -9, 123, 252, 167, 11, -19, 0 },
161 { -13, -11, 118, 250, 172, 15, -19, 0 },
162 { -12, -12, 112, 250, 177, 18, -20, -1 },
163 { -11, -14, 107, 247, 183, 21, -20, -1 },
164 { -10, -15, 101, 245, 188, 25, -21, -1 },
165 { -9, -16, 96, 243, 192, 29, -21, -2 },
166 { -8, -18, 90, 242, 197, 33, -22, -2 },
167 { -8, -19, 85, 239, 202, 37, -22, -2 },
168 { -7, -19, 80, 236, 206, 41, -22, -3 },
169 { -7, -20, 75, 233, 210, 46, -22, -3 },
170 { -6, -21, 69, 230, 215, 50, -22, -3 },
171 { -5, -21, 65, 226, 219, 55, -22, -5 },
172 { -5, -21, 60, 222, 222, 60, -21, -5 },
173 },
174 //>=0.5
175 {
176 { -16, 0, 145, 254, 145, 0, -16, 0 },
177 { -16, -2, 140, 253, 151, 3, -17, 0 },
178 { -15, -5, 135, 253, 157, 5, -18, 0 },
179 { -14, -7, 129, 252, 162, 8, -18, 0 },
180 { -13, -9, 123, 252, 167, 11, -19, 0 },
181 { -13, -11, 118, 250, 172, 15, -19, 0 },
182 { -12, -12, 112, 250, 177, 18, -20, -1 },
183 { -11, -14, 107, 247, 183, 21, -20, -1 },
184 { -10, -15, 101, 245, 188, 25, -21, -1 },
185 { -9, -16, 96, 243, 192, 29, -21, -2 },
186 { -8, -18, 90, 242, 197, 33, -22, -2 },
187 { -8, -19, 85, 239, 202, 37, -22, -2 },
188 { -7, -19, 80, 236, 206, 41, -22, -3 },
189 { -7, -20, 75, 233, 210, 46, -22, -3 },
190 { -6, -21, 69, 230, 215, 50, -22, -3 },
191 { -5, -21, 65, 226, 219, 55, -22, -5 },
192 { -5, -21, 60, 222, 222, 60, -21, -5 },
193 },
194 //>=0.33
195 {
196 { -18, 18, 144, 226, 144, 19, -17, -4 },
197 { -17, 16, 139, 226, 148, 21, -17, -4 },
198 { -17, 13, 135, 227, 153, 24, -18, -5 },
199 { -17, 11, 131, 226, 157, 27, -18, -5 },
200 { -17, 9, 126, 225, 161, 30, -17, -5 },
201 { -16, 6, 122, 225, 165, 33, -17, -6 },
202 { -16, 4, 118, 224, 169, 37, -17, -7 },
203 { -16, 2, 113, 224, 173, 40, -17, -7 },
204 { -15, 0, 109, 222, 177, 43, -17, -7 },
205 { -15, -1, 104, 220, 181, 47, -16, -8 },
206 { -14, -3, 100, 218, 185, 51, -16, -9 },
207 { -14, -5, 96, 217, 188, 54, -15, -9 },
208 { -14, -6, 91, 214, 192, 58, -14, -9 },
209 { -13, -7, 87, 212, 195, 62, -14, -10 },
210 { -13, -9, 83, 210, 198, 66, -13, -10 },
211 { -12, -10, 79, 207, 201, 70, -12, -11 },
212 { -12, -11, 74, 205, 205, 74, -11, -12 },
213 },
214 //>=0.25
215 {
216 { 14, 66, 113, 133, 113, 66, 14, -7 },
217 { 12, 65, 112, 133, 114, 68, 15, -7 },
218 { 11, 63, 111, 132, 115, 70, 17, -7 },
219 { 10, 62, 110, 132, 116, 71, 18, -7 },
220 { 8, 60, 108, 132, 118, 73, 20, -7 },
221 { 7, 58, 107, 132, 119, 75, 21, -7 },
222 { 6, 56, 106, 132, 120, 76, 23, -7 },
223 { 5, 55, 105, 131, 121, 78, 24, -7 },
224 { 4, 53, 103, 131, 122, 80, 26, -7 },
225 { 3, 51, 102, 131, 122, 81, 28, -6 },
226 { 2, 50, 101, 130, 123, 83, 29, -6 },
227 { 1, 48, 99, 131, 124, 84, 31, -6 },
228 { 0, 46, 98, 129, 125, 86, 33, -5 },
229 { -1, 45, 97, 128, 126, 88, 34, -5 },
230 { -2, 43, 95, 130, 126, 89, 36, -5 },
231 { -3, 41, 94, 128, 127, 91, 38, -4 },
232 { -3, 39, 92, 128, 128, 92, 39, -3 },
233 },
234 //others
235 {
236 { 39, 69, 93, 102, 93, 69, 39, 8 },
237 { 38, 68, 92, 102, 93, 70, 40, 9 },
238 { 37, 67, 91, 102, 93, 71, 41, 10 },
239 { 36, 66, 91, 101, 94, 71, 42, 11 },
240 { 35, 65, 90, 102, 94, 72, 43, 11 },
241 { 34, 64, 89, 102, 94, 73, 44, 12 },
242 { 33, 63, 88, 101, 95, 74, 45, 13 },
243 { 32, 62, 88, 100, 95, 75, 46, 14 },
244 { 31, 62, 87, 100, 95, 75, 47, 15 },
245 { 30, 61, 86, 99, 96, 76, 48, 16 },
246 { 29, 60, 86, 98, 96, 77, 49, 17 },
247 { 28, 59, 85, 98, 96, 78, 50, 18 },
248 { 27, 58, 84, 99, 97, 78, 50, 19 },
249 { 26, 57, 83, 99, 97, 79, 51, 20 },
250 { 25, 56, 83, 98, 97, 80, 52, 21 },
251 { 24, 55, 82, 97, 98, 81, 53, 22 },
252 { 23, 54, 81, 98, 98, 81, 54, 23 },
253 }
254 };
255
256 static RK_S16 g_zme_tap6_coeff[11][17][8] = {
257 //>=2.667
258 {
259 { -12, 20, 492, 20, -12, 4, 0, 0},
260 { -8, 8, 488, 36, -16, 4, 0, 0},
261 { -4, -4, 488, 48, -20, 4, 0, 0},
262 { 0, -16, 484, 64, -24, 4, 0, 0},
263 { 0, -24, 476, 80, -28, 8, 0, 0},
264 { 4, -32, 464, 100, -32, 8, 0, 0},
265 { 8, -40, 456, 116, -36, 8, 0, 0},
266 { 8, -48, 448, 136, -40, 8, 0, 0},
267 { 12, -52, 436, 152, -44, 8, 0, 0},
268 { 12, -60, 424, 172, -48, 12, 0, 0},
269 { 12, -64, 412, 192, -52, 12, 0, 0},
270 { 16, -64, 392, 212, -56, 12, 0, 0},
271 { 16, -68, 380, 232, -60, 12, 0, 0},
272 { 16, -68, 360, 248, -60, 16, 0, 0},
273 { 16, -68, 344, 268, -64, 16, 0, 0},
274 { 16, -68, 328, 288, -68, 16, 0, 0},
275 { 16, -68, 308, 308, -68, 16, 0, 0},
276 },
277 //>=2
278 {
279 { -20, 40, 468, 40, -20, 4, 0, 0},
280 { -16, 28, 464, 56, -24, 4, 0, 0},
281 { -16, 16, 464, 68, -28, 8, 0, 0},
282 { -12, 4, 460, 84, -32, 8, 0, 0},
283 { -8, -4, 452, 100, -36, 8, 0, 0},
284 { -4, -12, 444, 116, -40, 8, 0, 0},
285 { -4, -24, 440, 136, -44, 8, 0, 0},
286 { 0, -32, 432, 152, -48, 8, 0, 0},
287 { 0, -36, 416, 168, -48, 12, 0, 0},
288 { 4, -44, 408, 184, -52, 12, 0, 0},
289 { 4, -48, 400, 200, -56, 12, 0, 0},
290 { 8, -52, 380, 220, -56, 12, 0, 0},
291 { 8, -56, 372, 236, -60, 12, 0, 0},
292 { 8, -60, 356, 256, -60, 12, 0, 0},
293 { 12, -60, 340, 268, -60, 12, 0, 0},
294 { 12, -60, 324, 288, -64, 12, 0, 0},
295 { 12, -64, 308, 308, -64, 12, 0, 0},
296 },
297 //>=1.5
298 {
299 { -28, 60, 440, 60, -28, 8, 0, 0},
300 { -28, 48, 440, 76, -32, 8, 0, 0},
301 { -24, 36, 440, 88, -36, 8, 0, 0},
302 { -20, 28, 432, 104, -40, 8, 0, 0},
303 { -16, 16, 428, 116, -40, 8, 0, 0},
304 { -16, 4, 428, 132, -44, 8, 0, 0},
305 { -12, -4, 420, 148, -48, 8, 0, 0},
306 { -8, -12, 408, 164, -48, 8, 0, 0},
307 { -8, -20, 404, 180, -52, 8, 0, 0},
308 { -4, -24, 388, 196, -52, 8, 0, 0},
309 { -4, -32, 384, 212, -56, 8, 0, 0},
310 { 0, -36, 372, 224, -56, 8, 0, 0},
311 { 0, -40, 360, 240, -56, 8, 0, 0},
312 { 4, -44, 344, 256, -56, 8, 0, 0},
313 { 4, -48, 332, 272, -56, 8, 0, 0},
314 { 4, -52, 316, 292, -56, 8, 0, 0},
315 { 8, -52, 300, 300, -52, 8, 0, 0},
316 },
317 //>1
318 {
319 { -36, 80, 420, 80, -36, 4, 0, 0},
320 { -32, 68, 412, 92, -36, 8, 0, 0},
321 { -28, 56, 412, 104, -40, 8, 0, 0},
322 { -28, 44, 412, 116, -40, 8, 0, 0},
323 { -24, 36, 404, 132, -44, 8, 0, 0},
324 { -24, 24, 404, 144, -44, 8, 0, 0},
325 { -20, 16, 396, 160, -48, 8, 0, 0},
326 { -16, 8, 388, 172, -48, 8, 0, 0},
327 { -16, 0, 380, 188, -48, 8, 0, 0},
328 { -12, -8, 376, 200, -48, 4, 0, 0},
329 { -12, -12, 364, 216, -48, 4, 0, 0},
330 { -8, -20, 356, 228, -48, 4, 0, 0},
331 { -8, -24, 344, 244, -48, 4, 0, 0},
332 { -4, -32, 332, 260, -48, 4, 0, 0},
333 { -4, -36, 320, 272, -44, 4, 0, 0},
334 { 0, -40, 308, 288, -44, 0, 0, 0},
335 { 0, -40, 296, 296, -40, 0, 0, 0},
336 },
337 //==1
338 {
339 { 0, 0, 511, 0, 0, 0, 0, 0 },
340 { 3, -12, 511, 13, -3, 0, 0, 0 },
341 { 6, -22, 507, 28, -7, 0, 0, 0 },
342 { 8, -32, 502, 44, -11, 1, 0, 0 },
343 { 10, -40, 495, 61, -15, 1, 0, 0 },
344 { 11, -47, 486, 79, -19, 2, 0, 0 },
345 { 12, -53, 476, 98, -24, 3, 0, 0 },
346 { 13, -58, 464, 117, -28, 4, 0, 0 },
347 { 14, -62, 451, 137, -33, 5, 0, 0 },
348 { 15, -65, 437, 157, -38, 6, 0, 0 },
349 { 15, -67, 420, 179, -42, 7, 0, 0 },
350 { 15, -68, 404, 200, -46, 7, 0, 0 },
351 { 14, -68, 386, 221, -50, 9, 0, 0 },
352 { 14, -68, 367, 243, -54, 10, 0, 0 },
353 { 14, -67, 348, 264, -58, 11, 0, 0 },
354 { 13, -66, 328, 286, -61, 12, 0, 0 },
355 { 13, -63, 306, 306, -63, 13, 0, 0 },
356 },
357 //>=0.833
358 {
359 { -31, 104, 362, 104, -31, 4, 0, 0 },
360 { -30, 94, 362, 114, -32, 4, 0, 0 },
361 { -29, 84, 361, 125, -32, 3, 0, 0 },
362 { -28, 75, 359, 136, -33, 3, 0, 0 },
363 { -27, 66, 356, 147, -33, 3, 0, 0 },
364 { -25, 57, 353, 158, -33, 2, 0, 0 },
365 { -24, 49, 349, 169, -33, 2, 0, 0 },
366 { -22, 41, 344, 180, -32, 1, 0, 0 },
367 { -20, 33, 339, 191, -31, 0, 0, 0 },
368 { -19, 26, 333, 203, -30, -1, 0, 0 },
369 { -17, 19, 327, 214, -29, -2, 0, 0 },
370 { -16, 13, 320, 225, -27, -3, 0, 0 },
371 { -14, 7, 312, 236, -25, -4, 0, 0 },
372 { -13, 1, 305, 246, -22, -5, 0, 0 },
373 { -11, -4, 295, 257, -19, -6, 0, 0 },
374 { -10, -8, 286, 267, -16, -7, 0, 0 },
375 { -9, -12, 277, 277, -12, -9, 0, 0 },
376 },
377 //>=0.7
378 {
379 { -31, 104, 362, 104, -31, 4, 0, 0 },
380 { -30, 94, 362, 114, -32, 4, 0, 0 },
381 { -29, 84, 361, 125, -32, 3, 0, 0 },
382 { -28, 75, 359, 136, -33, 3, 0, 0 },
383 { -27, 66, 356, 147, -33, 3, 0, 0 },
384 { -25, 57, 353, 158, -33, 2, 0, 0 },
385 { -24, 49, 349, 169, -33, 2, 0, 0 },
386 { -22, 41, 344, 180, -32, 1, 0, 0 },
387 { -20, 33, 339, 191, -31, 0, 0, 0 },
388 { -19, 26, 333, 203, -30, -1, 0, 0 },
389 { -17, 19, 327, 214, -29, -2, 0, 0 },
390 { -16, 13, 320, 225, -27, -3, 0, 0 },
391 { -14, 7, 312, 236, -25, -4, 0, 0 },
392 { -13, 1, 305, 246, -22, -5, 0, 0 },
393 { -11, -4, 295, 257, -19, -6, 0, 0 },
394 { -10, -8, 286, 267, -16, -7, 0, 0 },
395 { -9, -12, 277, 277, -12, -9, 0, 0 },
396 },
397 //>=0.5
398 {
399 { -20, 130, 297, 130, -20, -5, 0, 0 },
400 { -21, 122, 298, 138, -19, -6, 0, 0 },
401 { -22, 115, 297, 146, -17, -7, 0, 0 },
402 { -22, 108, 296, 153, -16, -7, 0, 0 },
403 { -23, 101, 295, 161, -14, -8, 0, 0 },
404 { -23, 93, 294, 169, -12, -9, 0, 0 },
405 { -24, 87, 292, 177, -10, -10, 0, 0 },
406 { -24, 80, 289, 185, -7, -11, 0, 0 },
407 { -24, 73, 286, 193, -4, -12, 0, 0 },
408 { -23, 66, 283, 200, -1, -13, 0, 0 },
409 { -23, 60, 279, 208, 2, -14, 0, 0 },
410 { -23, 54, 276, 215, 5, -15, 0, 0 },
411 { -22, 48, 271, 222, 9, -16, 0, 0 },
412 { -21, 42, 266, 229, 13, -17, 0, 0 },
413 { -21, 37, 261, 236, 17, -18, 0, 0 },
414 { -21, 32, 255, 242, 22, -18, 0, 0 },
415 { -20, 27, 249, 249, 27, -20, 0, 0 },
416 },
417 //>=0.33
418 {
419 { 16, 136, 217, 136, 16, -9, 0, 0 },
420 { 13, 132, 217, 141, 18, -9, 0, 0 },
421 { 11, 128, 217, 145, 21, -10, 0, 0 },
422 { 9, 124, 216, 149, 24, -10, 0, 0 },
423 { 7, 119, 216, 153, 27, -10, 0, 0 },
424 { 5, 115, 216, 157, 30, -11, 0, 0 },
425 { 3, 111, 215, 161, 33, -11, 0, 0 },
426 { 1, 107, 214, 165, 36, -11, 0, 0 },
427 { 0, 102, 213, 169, 39, -11, 0, 0 },
428 { -2, 98, 211, 173, 43, -11, 0, 0 },
429 { -3, 94, 209, 177, 46, -11, 0, 0 },
430 { -4, 90, 207, 180, 50, -11, 0, 0 },
431 { -5, 85, 206, 184, 53, -11, 0, 0 },
432 { -6, 81, 203, 187, 57, -10, 0, 0 },
433 { -7, 77, 201, 190, 61, -10, 0, 0 },
434 { -8, 73, 198, 193, 65, -9, 0, 0 },
435 { -9, 69, 196, 196, 69, -9, 0, 0 },
436 },
437 //>=0.25
438 {
439 { 66, 115, 138, 115, 66, 12, 0, 0 },
440 { 64, 114, 136, 116, 68, 14, 0, 0 },
441 { 63, 113, 134, 117, 70, 15, 0, 0 },
442 { 61, 111, 135, 118, 71, 16, 0, 0 },
443 { 59, 110, 133, 119, 73, 18, 0, 0 },
444 { 57, 108, 134, 120, 74, 19, 0, 0 },
445 { 55, 107, 133, 121, 76, 20, 0, 0 },
446 { 53, 105, 133, 121, 78, 22, 0, 0 },
447 { 51, 104, 133, 122, 79, 23, 0, 0 },
448 { 49, 102, 132, 123, 81, 25, 0, 0 },
449 { 47, 101, 132, 124, 82, 26, 0, 0 },
450 { 45, 99, 131, 125, 84, 28, 0, 0 },
451 { 44, 98, 130, 125, 85, 30, 0, 0 },
452 { 42, 96, 130, 126, 87, 31, 0, 0 },
453 { 40, 95, 128, 127, 89, 33, 0, 0 },
454 { 38, 93, 129, 127, 90, 35, 0, 0 },
455 { 36, 92, 128, 128, 92, 36, 0, 0 },
456 },
457 //others
458 {
459 { 80, 105, 116, 105, 80, 26, 0, 0 },
460 { 79, 104, 115, 105, 81, 28, 0, 0 },
461 { 77, 103, 116, 106, 81, 29, 0, 0 },
462 { 76, 102, 115, 106, 82, 31, 0, 0 },
463 { 74, 101, 115, 106, 83, 33, 0, 0 },
464 { 73, 100, 114, 106, 84, 35, 0, 0 },
465 { 71, 99, 114, 107, 84, 37, 0, 0 },
466 { 70, 98, 113, 107, 85, 39, 0, 0 },
467 { 68, 98, 113, 107, 86, 40, 0, 0 },
468 { 67, 97, 112, 108, 86, 42, 0, 0 },
469 { 65, 96, 112, 108, 87, 44, 0, 0 },
470 { 63, 95, 112, 108, 88, 46, 0, 0 },
471 { 62, 94, 112, 108, 88, 48, 0, 0 },
472 { 60, 93, 111, 109, 89, 50, 0, 0 },
473 { 58, 93, 111, 109, 90, 51, 0, 0 },
474 { 57, 92, 110, 110, 90, 53, 0, 0 },
475 { 55, 91, 110, 110, 91, 55, 0, 0 },
476 }
477 };
478
calc_scl_factor(struct zme_params * src_params,scl_info * p_scl_info,RK_U8 bypass_en)479 static MPP_RET calc_scl_factor(struct zme_params* src_params, scl_info *p_scl_info, RK_U8 bypass_en)
480 {
481 RK_U16 act_width = p_scl_info->act_width;
482 RK_U16 dsp_width = p_scl_info->dsp_width;
483
484 RK_U16 act_height = p_scl_info->act_height;
485 RK_U16 dsp_height = p_scl_info->dsp_height;
486
487 RK_U8 xsd_en = 0;
488 RK_U8 xsu_en = 0;
489 RK_U8 xscl_mode = p_scl_info->xscl_mode;
490 RK_U16 xscl_factor;
491 RK_U8 xscl_offset = 0;
492
493 RK_U8 ysd_en = 0;
494 RK_U8 ysu_en = 0;
495 RK_U8 yscl_mode = p_scl_info->yscl_mode;
496 RK_U16 yscl_factor;
497 RK_U8 yscl_offset = 0;
498
499 RK_U8 xavg_en = 0;
500 RK_U8 xgt_en = 0;
501 RK_U8 xgt_mode = 0;
502
503 RK_U8 yavg_en = 0;
504 RK_U8 ygt_en = 0;
505 RK_U8 ygt_mode = 0;
506
507 RK_U32 f_xscl_factor_t;
508 RK_U32 f_yscl_factor_t;
509 RK_U32 f_xscl_factor_t1;
510 RK_U32 f_yscl_factor_t1;
511
512 if (act_width >= dsp_width * 14) {
513 act_width = act_width / 4;
514 xgt_en = 1;
515 xgt_mode = 3;
516 } else if (act_width >= dsp_width * 7) {
517 act_width = act_width / 2;
518 xgt_en = 1;
519 xgt_mode = 1;
520 }
521
522 if (act_width > dsp_width) {
523 xsd_en = 1;
524 xsu_en = 0;
525 xscl_factor = GET_SCALE_FACTOR_DN(act_width, dsp_width);
526 } else if (act_width < dsp_width) {
527 xsd_en = 0;
528 xsu_en = 1;
529 xscl_factor = GET_SCALE_FACTOR_UP(act_width, dsp_width);
530 } else {
531 xsd_en = 0;
532 xsu_en = 0;
533 xscl_factor = 1 << 12;
534 }
535
536 if (yscl_mode <= SCL_BIL) {
537 if (act_height > dsp_height * 4) {
538 ygt_en = 1;
539 ygt_mode = 1;
540 act_height = act_height / 4;
541 } else if (act_height > dsp_height * 2) {
542 ygt_en = 1;
543 ygt_mode = 0;
544 act_height = act_height / 2;
545 } else {
546 ygt_en = 0;
547 ygt_mode = 0;
548 }
549 }
550
551 if (yscl_mode == SCL_MPH) {
552 if (act_height >= dsp_height * 6) {
553 ygt_en = 1;
554 ygt_mode = 3;
555 }
556 }
557
558 if (act_height > dsp_height) {
559 ysd_en = 1;
560 ysu_en = 0;
561 yscl_factor = GET_SCALE_FACTOR_DN(act_height, dsp_height);
562 } else if (act_height < dsp_height) {
563 ysd_en = 0;
564 ysu_en = 1;
565 yscl_factor = GET_SCALE_FACTOR_UP(act_height, dsp_height);
566 } else {
567 ysd_en = 0;
568 ysu_en = 0;
569 yscl_factor = 1 << 12;
570 }
571
572 if (xsu_en == 1) {
573 f_xscl_factor_t = (1 << 16) * act_width / dsp_width;
574 f_xscl_factor_t1 = 1000 * (1 << 16) / f_xscl_factor_t;
575 } else {
576 f_xscl_factor_t = (1 << 12) * act_width / dsp_width;
577 f_xscl_factor_t1 = 1000 * (1 << 12) / f_xscl_factor_t;
578 }
579
580 if (ysu_en == 1) {
581 f_yscl_factor_t = (1 << 16) * act_height / dsp_height;
582 f_yscl_factor_t1 = 1000 * (1 << 16) / f_yscl_factor_t;
583 } else {
584 f_yscl_factor_t = (1 << 12) * act_height / dsp_height;
585 f_yscl_factor_t1 = 1000 * (1 << 12) / f_yscl_factor_t;
586 }
587
588 if (f_xscl_factor_t1 >= vdpp_scale_threshold[0])
589 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[0];
590 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[1])
591 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[1];
592 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[2])
593 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[2];
594 else if (f_xscl_factor_t1 > vdpp_scale_threshold[3])
595 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[3];
596 else if (f_xscl_factor_t1 == vdpp_scale_threshold[3])
597 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[4];
598 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[4])
599 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[5];
600 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[5])
601 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[6];
602 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[6])
603 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[7];
604 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[7])
605 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[8];
606 else if (f_xscl_factor_t1 >= vdpp_scale_threshold[8])
607 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[9];
608 else
609 p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[10];
610
611 if (f_yscl_factor_t1 >= vdpp_scale_threshold[0])
612 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[0];
613 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[1])
614 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[1];
615 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[2])
616 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[2];
617 else if (f_yscl_factor_t1 > vdpp_scale_threshold[3])
618 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[3];
619 else if (f_yscl_factor_t1 == vdpp_scale_threshold[3])
620 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[4];
621 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[4])
622 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[5];
623 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[5])
624 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[6];
625 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[6])
626 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[7];
627 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[7])
628 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[8];
629 else if (f_yscl_factor_t1 >= vdpp_scale_threshold[8])
630 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[9];
631 else
632 p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[10];
633
634 p_scl_info->xsd_en = xsd_en;
635 p_scl_info->xsu_en = xsu_en;
636 p_scl_info->xscl_mode = xscl_mode;
637 p_scl_info->xscl_factor = xscl_factor;
638 p_scl_info->xscl_offset = xscl_offset;
639
640 p_scl_info->ysd_en = ysd_en;
641 p_scl_info->ysu_en = ysu_en;
642 p_scl_info->yscl_mode = yscl_mode;
643 p_scl_info->yscl_factor = yscl_factor;
644 p_scl_info->yscl_offset = yscl_offset;
645
646 p_scl_info->xavg_en = xavg_en;
647 p_scl_info->xgt_en = xgt_en;
648 p_scl_info->xgt_mode = xgt_mode;
649
650 p_scl_info->yavg_en = yavg_en;
651 p_scl_info->ygt_en = ygt_en;
652 p_scl_info->ygt_mode = ygt_mode;
653
654 if (bypass_en) {
655 p_scl_info->xsd_bypass = !xsd_en;
656 p_scl_info->xsu_bypass = !xsu_en;
657 p_scl_info->ys_bypass = !(ysd_en || ysu_en);
658 } else {
659 p_scl_info->xsd_bypass = 0;
660 p_scl_info->xsu_bypass = 0;
661 p_scl_info->ys_bypass = 0;
662 }
663 return MPP_OK;
664 }
665
set_dmsr_to_vdpp_reg(struct dmsr_params * p_dmsr_param,struct dmsr_reg * dmsr)666 void set_dmsr_to_vdpp_reg(struct dmsr_params* p_dmsr_param, struct dmsr_reg* dmsr)
667 {
668 /* 0x0080(reg0) */
669 dmsr->reg0.sw_dmsr_edge_low_thre_0 = p_dmsr_param->dmsr_edge_th_low_arr[0];
670 dmsr->reg0.sw_dmsr_edge_high_thre_0 = p_dmsr_param->dmsr_edge_th_high_arr[0];
671
672 /* 0x0084(reg1) */
673 dmsr->reg1.sw_dmsr_edge_low_thre_1 = p_dmsr_param->dmsr_edge_th_low_arr[1];
674 dmsr->reg1.sw_dmsr_edge_high_thre_1 = p_dmsr_param->dmsr_edge_th_high_arr[1];
675
676 /* 0x0088(reg2) */
677 dmsr->reg2.sw_dmsr_edge_low_thre_2 = p_dmsr_param->dmsr_edge_th_low_arr[2];
678 dmsr->reg2.sw_dmsr_edge_high_thre_2 = p_dmsr_param->dmsr_edge_th_high_arr[2];
679
680 /* 0x008C(reg3) */
681 dmsr->reg3.sw_dmsr_edge_low_thre_3 = p_dmsr_param->dmsr_edge_th_low_arr[3];
682 dmsr->reg3.sw_dmsr_edge_high_thre_3 = p_dmsr_param->dmsr_edge_th_high_arr[3];
683
684 /* 0x0090(reg4) */
685 dmsr->reg4.sw_dmsr_edge_low_thre_4 = p_dmsr_param->dmsr_edge_th_low_arr[4];
686 dmsr->reg4.sw_dmsr_edge_high_thre_4 = p_dmsr_param->dmsr_edge_th_high_arr[4];
687
688 /* 0x0094(reg5) */
689 dmsr->reg5.sw_dmsr_edge_low_thre_5 = p_dmsr_param->dmsr_edge_th_low_arr[5];
690 dmsr->reg5.sw_dmsr_edge_high_thre_5 = p_dmsr_param->dmsr_edge_th_high_arr[5];
691
692 /* 0x0098(reg6) */
693 dmsr->reg6.sw_dmsr_edge_low_thre_6 = p_dmsr_param->dmsr_edge_th_low_arr[6];
694 dmsr->reg6.sw_dmsr_edge_high_thre_6 = p_dmsr_param->dmsr_edge_th_high_arr[6];
695 {
696 RK_U16 adj_mapping_k[7];
697 RK_U16 tmp_diff;
698 RK_U16 i;
699 RK_U16 contrast2conf_mapping_k;
700 RK_U32 tmp_diff_y, tmp_diff_x;
701
702 for (i = 0; i < 7; i++) {
703 tmp_diff = p_dmsr_param->dmsr_edge_th_high_arr[i] - p_dmsr_param->dmsr_edge_th_low_arr[i];
704 adj_mapping_k[i] = (65535 / MPP_MAX(1, tmp_diff));
705 }
706 tmp_diff_y = p_dmsr_param->dmsr_contrast_to_conf_map_y1 - p_dmsr_param->dmsr_contrast_to_conf_map_y0;
707 tmp_diff_x = MPP_MAX(p_dmsr_param->dmsr_contrast_to_conf_map_x1 - p_dmsr_param->dmsr_contrast_to_conf_map_x0, 1);
708
709 contrast2conf_mapping_k = mpp_clip(256 * tmp_diff_y / tmp_diff_x, 0, 65535);
710 /* 0x009C(reg7) */
711 dmsr->reg7.sw_dmsr_edge_k_0 = adj_mapping_k[0];
712 dmsr->reg7.sw_dmsr_edge_k_1 = adj_mapping_k[1];
713
714 /* 0x00A0(reg8) */
715 dmsr->reg8.sw_dmsr_edge_k_2 = adj_mapping_k[2];
716 dmsr->reg8.sw_dmsr_edge_k_3 = adj_mapping_k[3];
717
718 /* 0x00A4(reg9) */
719 dmsr->reg9.sw_dmsr_edge_k_4 = adj_mapping_k[4];
720 dmsr->reg9.sw_dmsr_edge_k_5 = adj_mapping_k[5];
721
722 /* 0x00A8(reg10) */
723 dmsr->reg10.sw_dmsr_edge_k_6 = adj_mapping_k[6];
724 dmsr->reg10.sw_dmsr_dir_contrast_conf_f = contrast2conf_mapping_k;
725 }
726 /* 0x00AC(reg11) */
727 dmsr->reg11.sw_dmsr_dir_contrast_conf_x0 = p_dmsr_param->dmsr_contrast_to_conf_map_x0;
728 dmsr->reg11.sw_dmsr_dir_contrast_conf_x1 = p_dmsr_param->dmsr_contrast_to_conf_map_x1;
729
730 /* 0x00B0(reg12) */
731 dmsr->reg12.sw_dmsr_dir_contrast_conf_y0 = p_dmsr_param->dmsr_contrast_to_conf_map_y0;
732 dmsr->reg12.sw_dmsr_dir_contrast_conf_y1 = p_dmsr_param->dmsr_contrast_to_conf_map_y1;
733
734 /* 0x00B4(reg13) */
735 dmsr->reg13.sw_dmsr_var_th = p_dmsr_param->dmsr_blk_flat_th;
736
737 /* 0x00B8(reg14) */
738 dmsr->reg14.sw_dmsr_diff_coring_th0 = p_dmsr_param->dmsr_diff_core_th0;
739 dmsr->reg14.sw_dmsr_diff_coring_th1 = p_dmsr_param->dmsr_diff_core_th1;
740
741 /* 0x00BC(reg15) */
742 dmsr->reg15.sw_dmsr_diff_coring_wgt0 = p_dmsr_param->dmsr_diff_core_wgt0;
743 dmsr->reg15.sw_dmsr_diff_coring_wgt1 = p_dmsr_param->dmsr_diff_core_wgt1;
744 dmsr->reg15.sw_dmsr_diff_coring_wgt2 = p_dmsr_param->dmsr_diff_core_wgt2;
745 {
746 RK_U16 diff_coring_y0 = p_dmsr_param->dmsr_diff_core_th0 * p_dmsr_param->dmsr_diff_core_wgt0;
747 RK_U16 diff_coring_y1 = ((p_dmsr_param->dmsr_diff_core_th1 - p_dmsr_param->dmsr_diff_core_th0) * p_dmsr_param->dmsr_diff_core_wgt1) + diff_coring_y0;
748 /* 0x00C0(reg16) */
749 dmsr->reg16.sw_dmsr_diff_coring_y0 = diff_coring_y0;
750 dmsr->reg16.sw_dmsr_diff_coring_y1 = diff_coring_y1;
751 }
752 /* 0x00C4(reg17) */
753 dmsr->reg17.sw_dmsr_wgt_pri_gain_1_odd = p_dmsr_param->dmsr_wgt_pri_gain_odd_1;
754 dmsr->reg17.sw_dmsr_wgt_pri_gain_1_even = p_dmsr_param->dmsr_wgt_pri_gain_even_1;
755 dmsr->reg17.sw_dmsr_wgt_pri_gain_2_odd = p_dmsr_param->dmsr_wgt_pri_gain_odd_2;
756 dmsr->reg17.sw_dmsr_wgt_pri_gain_2_even = p_dmsr_param->dmsr_wgt_pri_gain_even_2;
757
758 /* 0x00C8(reg18) */
759 dmsr->reg18.sw_dmsr_wgt_sec_gain_1 = p_dmsr_param->dmsr_wgt_sec_gain;
760 dmsr->reg18.sw_dmsr_wgt_sec_gain_2 = p_dmsr_param->dmsr_wgt_sec_gain * 2;
761
762 /* 0x00CC(reg19) */
763 dmsr->reg19.sw_dmsr_strength_pri = p_dmsr_param->dmsr_str_pri_y;
764 dmsr->reg19.sw_dmsr_strength_sec = p_dmsr_param->dmsr_str_sec_y;
765 dmsr->reg19.sw_dmsr_dump = p_dmsr_param->dmsr_dumping_y;
766 }
767
vdpp_set_default_zme_param(struct zme_params * param)768 void vdpp_set_default_zme_param(struct zme_params* param)
769 {
770 param->zme_bypass_en = 1;
771 param->zme_dering_enable = 1;
772 param->zme_dering_sen_0 = 16;
773 param->zme_dering_sen_1 = 4;
774 param->zme_dering_blend_alpha = 16;
775 param->zme_dering_blend_beta = 13;
776 param->zme_tap8_coeff = g_zme_tap8_coeff;
777 param->zme_tap6_coeff = g_zme_tap6_coeff;
778 }
779
780
set_zme_to_vdpp_reg(struct zme_params * zme_params,struct zme_reg * zme)781 void set_zme_to_vdpp_reg(struct zme_params *zme_params, struct zme_reg *zme)
782 {
783 /* 0x00D0(reg20), debug settings, skip */
784 /* 3. set reg::zme */
785 /* 3.1 set reg::zme::common */
786 enum ZME_FMT zme_format_in = FMT_YCbCr420_888;
787 scl_info yrgb_scl_info = {0};
788 scl_info cbcr_scl_info = {0};
789
790 yrgb_scl_info.act_width = zme_params->src_width;
791 yrgb_scl_info.act_height = zme_params->src_height;
792 yrgb_scl_info.dsp_width = zme_params->dst_width;
793 yrgb_scl_info.dsp_height = zme_params->dst_height;
794 yrgb_scl_info.xscl_mode = SCL_MPH;
795 yrgb_scl_info.yscl_mode = SCL_MPH;
796 yrgb_scl_info.dering_en = zme_params->zme_dering_enable;
797 calc_scl_factor(zme_params, &yrgb_scl_info, zme_params->zme_bypass_en);
798
799 if (zme_format_in == FMT_YCbCr420_888) {
800 cbcr_scl_info.act_width = zme_params->src_width / 2;
801 cbcr_scl_info.act_height = zme_params->src_height / 2;
802 } else {
803 /* only support yuv420 as input */
804 }
805
806 if (zme_params->dst_fmt == VDPP_FMT_YUV444) {
807 if (!zme_params->yuv_out_diff) {
808 cbcr_scl_info.dsp_width = zme_params->dst_width;
809 cbcr_scl_info.dsp_height = zme_params->dst_height;
810 } else {
811 cbcr_scl_info.dsp_width = zme_params->dst_c_width;
812 cbcr_scl_info.dsp_height = zme_params->dst_c_height;
813 }
814 } else if (zme_params->dst_fmt == VDPP_FMT_YUV420) {
815 if (!zme_params->yuv_out_diff) {
816 cbcr_scl_info.dsp_width = zme_params->dst_width / 2;
817 cbcr_scl_info.dsp_height = zme_params->dst_height / 2;
818 } else {
819 cbcr_scl_info.dsp_width = zme_params->dst_c_width / 2;
820 cbcr_scl_info.dsp_height = zme_params->dst_c_height / 2;
821 }
822 } else {
823 /* not supported */
824 }
825 cbcr_scl_info.xscl_mode = SCL_MPH;
826 cbcr_scl_info.yscl_mode = SCL_MPH;
827 cbcr_scl_info.dering_en = zme_params->zme_dering_enable;
828 calc_scl_factor(zme_params, &cbcr_scl_info, zme_params->zme_bypass_en);
829
830 /* 0x0800(reg0) */
831 zme->common.reg0.bypass_en = 0;
832 zme->common.reg0.align_en = 0;
833 zme->common.reg0.format_in = FMT_YCbCr420_888;
834 if (zme_params->dst_fmt == VDPP_FMT_YUV444)
835 zme->common.reg0.format_out = FMT_YCbCr444_888;
836 else
837 zme->common.reg0.format_out = FMT_YCbCr420_888;
838 zme->common.reg0.auto_gating_en = 1;
839
840 /* 0x0804 ~ 0x0808(reg1 ~ reg2), skip */
841
842 /* 0x080C(reg3), not used */
843 zme->common.reg3.vir_width = zme_params->src_width;
844 zme->common.reg3.vir_height = zme_params->src_height;
845
846 /* 0x0810(reg4) */
847 zme->common.reg4.yrgb_xsd_en = yrgb_scl_info.xsd_en;
848 zme->common.reg4.yrgb_xsu_en = yrgb_scl_info.xsu_en;
849 zme->common.reg4.yrgb_scl_mode = yrgb_scl_info.xscl_mode;
850 zme->common.reg4.yrgb_ysd_en = yrgb_scl_info.ysd_en;
851 zme->common.reg4.yrgb_ysu_en = yrgb_scl_info.ysu_en;
852 zme->common.reg4.yrgb_yscl_mode = yrgb_scl_info.yscl_mode;
853 zme->common.reg4.yrgb_dering_en = yrgb_scl_info.dering_en;
854 zme->common.reg4.yrgb_gt_en = yrgb_scl_info.ygt_en;
855 zme->common.reg4.yrgb_gt_mode = yrgb_scl_info.ygt_mode;
856 zme->common.reg4.yrgb_xgt_en = yrgb_scl_info.xgt_en;
857 zme->common.reg4.yrgb_xgt_mode = yrgb_scl_info.xgt_mode;
858 zme->common.reg4.yrgb_xsd_bypass = yrgb_scl_info.xsd_bypass;
859 zme->common.reg4.yrgb_ys_bypass = yrgb_scl_info.ys_bypass;
860 zme->common.reg4.yrgb_xsu_bypass = yrgb_scl_info.xsu_bypass;
861
862 /* 0x0814(reg5) */
863 zme->common.reg5.yrgb_src_width = yrgb_scl_info.act_width - 1;
864 zme->common.reg5.yrgb_src_height = yrgb_scl_info.act_height - 1;
865
866 /* 0x0818(reg6) */
867 zme->common.reg6.yrgb_dst_width = yrgb_scl_info.dsp_width - 1;
868 zme->common.reg6.yrgb_dst_height = yrgb_scl_info.dsp_height - 1;
869
870 /* 0x081C(reg7) */
871 zme->common.reg7.yrgb_dering_sen0 = zme_params->zme_dering_sen_0;
872 zme->common.reg7.yrgb_dering_sen1 = zme_params->zme_dering_sen_1;
873 zme->common.reg7.yrgb_dering_alpha = zme_params->zme_dering_blend_alpha;
874 zme->common.reg7.yrgb_dering_delta = zme_params->zme_dering_blend_beta;
875
876 /* 0x0820(reg8) */
877 zme->common.reg8.yrgb_xscl_factor = yrgb_scl_info.xscl_factor;
878 zme->common.reg8.yrgb_xscl_offset = yrgb_scl_info.xscl_offset;
879
880 /* 0x0824(reg9) */
881 zme->common.reg9.yrgb_yscl_factor = yrgb_scl_info.yscl_factor;
882 zme->common.reg9.yrgb_yscl_offset = yrgb_scl_info.yscl_offset;
883
884 /* 0x0828 ~ 0x082C(reg10 ~ reg11), skip */
885
886 /* 0x0830(reg12) */
887 zme->common.reg12.cbcr_xsd_en = cbcr_scl_info.xsd_en;
888 zme->common.reg12.cbcr_xsu_en = cbcr_scl_info.xsu_en;
889 zme->common.reg12.cbcr_scl_mode = cbcr_scl_info.xscl_mode;
890 zme->common.reg12.cbcr_ysd_en = cbcr_scl_info.ysd_en;
891 zme->common.reg12.cbcr_ysu_en = cbcr_scl_info.ysu_en;
892 zme->common.reg12.cbcr_yscl_mode = cbcr_scl_info.yscl_mode;
893 zme->common.reg12.cbcr_dering_en = cbcr_scl_info.dering_en;
894 zme->common.reg12.cbcr_gt_en = cbcr_scl_info.ygt_en;
895 zme->common.reg12.cbcr_gt_mode = cbcr_scl_info.ygt_mode;
896 zme->common.reg12.cbcr_xgt_en = cbcr_scl_info.xgt_en;
897 zme->common.reg12.cbcr_xgt_mode = cbcr_scl_info.xgt_mode;
898 zme->common.reg12.cbcr_xsd_bypass = cbcr_scl_info.xsd_bypass;
899 zme->common.reg12.cbcr_ys_bypass = cbcr_scl_info.ys_bypass;
900 zme->common.reg12.cbcr_xsu_bypass = cbcr_scl_info.xsu_bypass;
901
902 /* 0x0834(reg13) */
903 zme->common.reg13.cbcr_src_width = cbcr_scl_info.act_width - 1;
904 zme->common.reg13.cbcr_src_height = cbcr_scl_info.act_height - 1;
905
906 /* 0x0838(reg14) */
907 zme->common.reg14.cbcr_dst_width = cbcr_scl_info.dsp_width - 1;
908 zme->common.reg14.cbcr_dst_height = cbcr_scl_info.dsp_height - 1;
909
910 /* 0x083C(reg15) */
911 zme->common.reg15.cbcr_dering_sen0 = zme_params->zme_dering_sen_0;
912 zme->common.reg15.cbcr_dering_sen1 = zme_params->zme_dering_sen_1;
913 zme->common.reg15.cbcr_dering_alpha = zme_params->zme_dering_blend_alpha;
914 zme->common.reg15.cbcr_dering_delta = zme_params->zme_dering_blend_beta;
915
916 /* 0x0840(reg16) */
917 zme->common.reg16.cbcr_xscl_factor = cbcr_scl_info.xscl_factor;
918 zme->common.reg16.cbcr_xscl_offset = cbcr_scl_info.xscl_offset;
919
920 /* 0x0844(reg17) */
921 zme->common.reg17.cbcr_yscl_factor = cbcr_scl_info.yscl_factor;
922 zme->common.reg17.cbcr_yscl_offset = cbcr_scl_info.yscl_offset;
923
924 /* 3.2 set reg::zme::coef */
925 /* 0x0000(reg0) */
926 VDPP_SET_ZME_COEF(0, 0, 0);
927 VDPP_SET_ZME_COEF(0, 0, 1);
928
929 /* 0x0004(reg1) */
930 VDPP_SET_ZME_COEF(1, 0, 2);
931 VDPP_SET_ZME_COEF(1, 0, 3);
932
933 /* 0x0008(reg2) */
934 VDPP_SET_ZME_COEF(2, 0, 4);
935 VDPP_SET_ZME_COEF(2, 0, 5);
936
937 /* 0x000c(reg3) */
938 VDPP_SET_ZME_COEF(3, 0, 6);
939 VDPP_SET_ZME_COEF(3, 0, 7);
940
941 /* 0x0010(reg4) */
942 VDPP_SET_ZME_COEF(4, 1, 0);
943 VDPP_SET_ZME_COEF(4, 1, 1);
944
945 /* 0x0014(reg5) */
946 VDPP_SET_ZME_COEF(5, 1, 2);
947 VDPP_SET_ZME_COEF(5, 1, 3);
948
949 /* 0x0018(reg6) */
950 VDPP_SET_ZME_COEF(6, 1, 4);
951 VDPP_SET_ZME_COEF(6, 1, 5);
952
953 /* 0x001c(reg7) */
954 VDPP_SET_ZME_COEF(7, 1, 6);
955 VDPP_SET_ZME_COEF(7, 1, 7);
956
957 /* 0x0020(reg8) */
958 VDPP_SET_ZME_COEF(8, 2, 0);
959 VDPP_SET_ZME_COEF(8, 2, 1);
960
961 /* 0x0024(reg9) */
962 VDPP_SET_ZME_COEF(9, 2, 2);
963 VDPP_SET_ZME_COEF(9, 2, 3);
964
965 /* 0x0028(reg10) */
966 VDPP_SET_ZME_COEF(10, 2, 4);
967 VDPP_SET_ZME_COEF(10, 2, 5);
968
969 /* 0x002c(reg11) */
970 VDPP_SET_ZME_COEF(11, 2, 6);
971 VDPP_SET_ZME_COEF(11, 2, 7);
972
973 /* 0x0030(reg12) */
974 VDPP_SET_ZME_COEF(12, 3, 0);
975 VDPP_SET_ZME_COEF(12, 3, 1);
976
977 /* 0x0034(reg13) */
978 VDPP_SET_ZME_COEF(13, 3, 2);
979 VDPP_SET_ZME_COEF(13, 3, 3);
980
981 /* 0x0038(reg14) */
982 VDPP_SET_ZME_COEF(14, 3, 4);
983 VDPP_SET_ZME_COEF(14, 3, 5);
984
985 /* 0x003c(reg15) */
986 VDPP_SET_ZME_COEF(15, 3, 6);
987 VDPP_SET_ZME_COEF(15, 3, 7);
988
989 /* 0x0040(reg16) */
990 VDPP_SET_ZME_COEF(16, 4, 0);
991 VDPP_SET_ZME_COEF(16, 4, 1);
992
993 /* 0x0044(reg17) */
994 VDPP_SET_ZME_COEF(17, 4, 2);
995 VDPP_SET_ZME_COEF(17, 4, 3);
996
997 /* 0x0048(reg18) */
998 VDPP_SET_ZME_COEF(18, 4, 4);
999 VDPP_SET_ZME_COEF(18, 4, 5);
1000
1001 /* 0x004c(reg19) */
1002 VDPP_SET_ZME_COEF(19, 4, 6);
1003 VDPP_SET_ZME_COEF(19, 4, 7);
1004
1005 /* 0x0050(reg20) */
1006 VDPP_SET_ZME_COEF(20, 5, 0);
1007 VDPP_SET_ZME_COEF(20, 5, 1);
1008
1009 /* 0x0054(reg21) */
1010 VDPP_SET_ZME_COEF(21, 5, 2);
1011 VDPP_SET_ZME_COEF(21, 5, 3);
1012
1013 /* 0x0058(reg22) */
1014 VDPP_SET_ZME_COEF(22, 5, 4);
1015 VDPP_SET_ZME_COEF(22, 5, 5);
1016
1017 /* 0x005c(reg23) */
1018 VDPP_SET_ZME_COEF(23, 5, 6);
1019 VDPP_SET_ZME_COEF(23, 5, 7);
1020
1021 /* 0x0060(reg24) */
1022 VDPP_SET_ZME_COEF(24, 6, 0);
1023 VDPP_SET_ZME_COEF(24, 6, 1);
1024
1025 /* 0x0064(reg25) */
1026 VDPP_SET_ZME_COEF(25, 6, 2);
1027 VDPP_SET_ZME_COEF(25, 6, 3);
1028
1029 /* 0x0068(reg26) */
1030 VDPP_SET_ZME_COEF(26, 6, 4);
1031 VDPP_SET_ZME_COEF(26, 6, 5);
1032
1033 /* 0x006c(reg27) */
1034 VDPP_SET_ZME_COEF(27, 6, 6);
1035 VDPP_SET_ZME_COEF(27, 6, 7);
1036
1037 /* 0x0070(reg28) */
1038 VDPP_SET_ZME_COEF(28, 7, 0);
1039 VDPP_SET_ZME_COEF(28, 7, 1);
1040
1041 /* 0x0074(reg29) */
1042 VDPP_SET_ZME_COEF(29, 7, 2);
1043 VDPP_SET_ZME_COEF(29, 7, 3);
1044
1045 /* 0x0078(reg30) */
1046 VDPP_SET_ZME_COEF(30, 7, 4);
1047 VDPP_SET_ZME_COEF(30, 7, 5);
1048
1049 /* 0x007c(reg31) */
1050 VDPP_SET_ZME_COEF(31, 7, 6);
1051 VDPP_SET_ZME_COEF(31, 7, 7);
1052
1053 /* 0x0080(reg32) */
1054 VDPP_SET_ZME_COEF(32, 8, 0);
1055 VDPP_SET_ZME_COEF(32, 8, 1);
1056
1057 /* 0x0084(reg33) */
1058 VDPP_SET_ZME_COEF(33, 8, 2);
1059 VDPP_SET_ZME_COEF(33, 8, 3);
1060
1061 /* 0x0088(reg34) */
1062 VDPP_SET_ZME_COEF(34, 8, 4);
1063 VDPP_SET_ZME_COEF(34, 8, 5);
1064
1065 /* 0x008c(reg35) */
1066 VDPP_SET_ZME_COEF(35, 8, 6);
1067 VDPP_SET_ZME_COEF(35, 8, 7);
1068
1069 /* 0x0090(reg36) */
1070 VDPP_SET_ZME_COEF(36, 9, 0);
1071 VDPP_SET_ZME_COEF(36, 9, 1);
1072
1073 /* 0x0094(reg37) */
1074 VDPP_SET_ZME_COEF(37, 9, 2);
1075 VDPP_SET_ZME_COEF(37, 9, 3);
1076
1077 /* 0x0098(reg38) */
1078 VDPP_SET_ZME_COEF(38, 9, 4);
1079 VDPP_SET_ZME_COEF(38, 9, 5);
1080
1081 /* 0x009c(reg39) */
1082 VDPP_SET_ZME_COEF(39, 9, 6);
1083 VDPP_SET_ZME_COEF(39, 9, 7);
1084
1085 /* 0x00a0(reg40) */
1086 VDPP_SET_ZME_COEF(40, 10, 0);
1087 VDPP_SET_ZME_COEF(40, 10, 1);
1088
1089 /* 0x00a4(reg41) */
1090 VDPP_SET_ZME_COEF(41, 10, 2);
1091 VDPP_SET_ZME_COEF(41, 10, 3);
1092
1093 /* 0x00a8(reg42) */
1094 VDPP_SET_ZME_COEF(42, 10, 4);
1095 VDPP_SET_ZME_COEF(42, 10, 5);
1096
1097 /* 0x00ac(reg43) */
1098 VDPP_SET_ZME_COEF(43, 10, 6);
1099 VDPP_SET_ZME_COEF(43, 10, 7);
1100
1101 /* 0x00b0(reg44) */
1102 VDPP_SET_ZME_COEF(44, 11, 0);
1103 VDPP_SET_ZME_COEF(44, 11, 1);
1104
1105 /* 0x00b4(reg45) */
1106 VDPP_SET_ZME_COEF(45, 11, 2);
1107 VDPP_SET_ZME_COEF(45, 11, 3);
1108
1109 /* 0x00b8(reg46) */
1110 VDPP_SET_ZME_COEF(46, 11, 4);
1111 VDPP_SET_ZME_COEF(46, 11, 5);
1112
1113 /* 0x00bc(reg47) */
1114 VDPP_SET_ZME_COEF(47, 11, 6);
1115 VDPP_SET_ZME_COEF(47, 11, 7);
1116
1117 /* 0x00c0(reg48) */
1118 VDPP_SET_ZME_COEF(48, 12, 0);
1119 VDPP_SET_ZME_COEF(48, 12, 1);
1120
1121 /* 0x00c4(reg49) */
1122 VDPP_SET_ZME_COEF(49, 12, 2);
1123 VDPP_SET_ZME_COEF(49, 12, 3);
1124
1125 /* 0x00c8(reg50) */
1126 VDPP_SET_ZME_COEF(50, 12, 4);
1127 VDPP_SET_ZME_COEF(50, 12, 5);
1128
1129 /* 0x00cc(reg51) */
1130 VDPP_SET_ZME_COEF(51, 12, 6);
1131 VDPP_SET_ZME_COEF(51, 12, 7);
1132
1133 /* 0x00d0(reg52) */
1134 VDPP_SET_ZME_COEF(52, 13, 0);
1135 VDPP_SET_ZME_COEF(52, 13, 1);
1136
1137 /* 0x00d4(reg53) */
1138 VDPP_SET_ZME_COEF(53, 13, 2);
1139 VDPP_SET_ZME_COEF(53, 13, 3);
1140
1141 /* 0x00d8(reg54) */
1142 VDPP_SET_ZME_COEF(54, 13, 4);
1143 VDPP_SET_ZME_COEF(54, 13, 5);
1144
1145 /* 0x00dc(reg55) */
1146 VDPP_SET_ZME_COEF(55, 13, 6);
1147 VDPP_SET_ZME_COEF(55, 13, 7);
1148
1149 /* 0x00e0(reg56) */
1150 VDPP_SET_ZME_COEF(56, 14, 0);
1151 VDPP_SET_ZME_COEF(56, 14, 1);
1152
1153 /* 0x00e4(reg57) */
1154 VDPP_SET_ZME_COEF(57, 14, 2);
1155 VDPP_SET_ZME_COEF(57, 14, 3);
1156
1157 /* 0x00e8(reg58) */
1158 VDPP_SET_ZME_COEF(58, 14, 4);
1159 VDPP_SET_ZME_COEF(58, 14, 5);
1160
1161 /* 0x00ec(reg59) */
1162 VDPP_SET_ZME_COEF(59, 14, 6);
1163 VDPP_SET_ZME_COEF(59, 14, 7);
1164
1165 /* 0x00f0(reg60) */
1166 VDPP_SET_ZME_COEF(60, 15, 0);
1167 VDPP_SET_ZME_COEF(60, 15, 1);
1168
1169 /* 0x00f4(reg61) */
1170 VDPP_SET_ZME_COEF(61, 15, 2);
1171 VDPP_SET_ZME_COEF(61, 15, 3);
1172
1173 /* 0x00f8(reg62) */
1174 VDPP_SET_ZME_COEF(62, 15, 4);
1175 VDPP_SET_ZME_COEF(62, 15, 5);
1176
1177 /* 0x00fc(reg63) */
1178 VDPP_SET_ZME_COEF(63, 15, 6);
1179 VDPP_SET_ZME_COEF(63, 15, 7);
1180
1181 /* 0x0100(reg64) */
1182 VDPP_SET_ZME_COEF(64, 16, 0);
1183 VDPP_SET_ZME_COEF(64, 16, 1);
1184
1185 /* 0x0104(reg65) */
1186 VDPP_SET_ZME_COEF(65, 16, 2);
1187 VDPP_SET_ZME_COEF(65, 16, 3);
1188
1189 /* 0x0108(reg66) */
1190 VDPP_SET_ZME_COEF(66, 16, 4);
1191 VDPP_SET_ZME_COEF(66, 16, 5);
1192
1193 /* 0x010c(reg67) */
1194 VDPP_SET_ZME_COEF(67, 16, 6);
1195 VDPP_SET_ZME_COEF(67, 16, 7);
1196
1197 }
1198