535     Vdpu34xRegCommon *common = &regs->common;  in set_registers()  local
540     common->reg016_str_len = p_hal->strm_len;  in set_registers()
541     common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag;  in set_registers()
542     common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0;  in set_registers()
543     common->reg028.sw_poc_arb_flag = 0;  in set_registers()
561             common->reg012.fbc_e = 1;  in set_registers()
562             common->reg018.y_hor_virstride = fbc_hdr_stride / 16;  in set_registers()
563             common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;  in set_registers()
564             common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;  in set_registers()
566             common->reg012.fbc_e = 0;  in set_registers()
567             common->reg018.y_hor_virstride = hor_virstride / 16;  in set_registers()
568             common->reg019.uv_hor_virstride = hor_virstride / 16;  in set_registers()
569             common->reg020_y_virstride.y_virstride = y_virstride / 16;  in set_registers()
642                     common->reg021.error_intra_mode = 0;  in set_registers()
668     Vdpu34xRegCommon *common = &regs->common;  in init_common_regs()  local
670     common->reg009.dec_mode = 1;  //!< h264  in init_common_regs()
671     common->reg015.rlc_mode = 0;  in init_common_regs()
673     common->reg011.buf_empty_en = 1;  in init_common_regs()
674     common->reg011.dec_timeout_e = 1;  in init_common_regs()
676     common->reg010.dec_e = 1;  in init_common_regs()
677     common->reg017.slice_num = 0x3fff;  in init_common_regs()
679     common->reg012.wait_reset_en = 1;  in init_common_regs()
680     common->reg013.h26x_error_mode = 1;  in init_common_regs()
681     common->reg013.colmv_error_mode = 1;  in init_common_regs()
682     common->reg013.h26x_streamd_error_mode = 1;  in init_common_regs()
683     common->reg021.error_deb_en = 1;  in init_common_regs()
684     common->reg021.inter_error_prc_mode = 0;  in init_common_regs()
685     common->reg021.error_intra_mode = 1;  in init_common_regs()
688         common->reg024.cabac_err_en_lowbits = 0;  in init_common_regs()
689         common->reg025.cabac_err_en_highbits = 0;  in init_common_regs()
690         common->reg026.swreg_block_gating_e = 0xfffef;  in init_common_regs()
692         common->reg024.cabac_err_en_lowbits = 0xffffffff;  in init_common_regs()
693         common->reg025.cabac_err_en_highbits = 0x3ff3ffff;  in init_common_regs()
694         common->reg026.swreg_block_gating_e = 0xfffff;  in init_common_regs()
696     common->reg026.reg_cfg_gating_en = 1;  in init_common_regs()
697     common->reg032_timeout_threshold = 0x3ffff;  in init_common_regs()
699     common->reg011.dec_clkgate_e = 1;  in init_common_regs()
700     common->reg011.dec_e_strmd_clkgate_dis = 0;  in init_common_regs()
701     common->reg011.dec_timeout_e = 1;  in init_common_regs()
703     common->reg013.timeout_mode = 1;  in init_common_regs()
837     if (regs->common.reg012.fbc_e) {  in h264d_refine_rcb_size()
984     regs->common.reg012.scanlist_addr_valid_en = 1;  in vdpu34x_h264d_gen_regs()
997     vdpu34x_setup_statistic(&regs->common, &regs->statistic);  in vdpu34x_h264d_gen_regs()
1025         wr_cfg.reg = &regs->common;  in vdpu34x_h264d_start()
1026         wr_cfg.size = sizeof(regs->common);  in vdpu34x_h264d_start()