427         hw_reg->common.reg012.scanlist_addr_valid_en = 1;  in hal_h265d_v345_output_pps_packet()
742     if (hw_regs->common.reg012.fbc_e) {  in h265d_refine_rcb_size()
751         if (hw_regs->common.reg012.fbc_e) {  in h265d_refine_rcb_size()
945         hw_regs->common.reg013.h26x_error_mode = 1;  in hal_h265d_vdpu34x_gen_regs()
946         hw_regs->common.reg013.h26x_streamd_error_mode = 1;  in hal_h265d_vdpu34x_gen_regs()
947         hw_regs->common.reg013.colmv_error_mode = 1;  in hal_h265d_vdpu34x_gen_regs()
948         hw_regs->common.reg021.error_deb_en = 1;  in hal_h265d_vdpu34x_gen_regs()
949         hw_regs->common.reg021.inter_error_prc_mode = 0;  in hal_h265d_vdpu34x_gen_regs()
950         hw_regs->common.reg021.error_intra_mode = 1;  in hal_h265d_vdpu34x_gen_regs()
952         hw_regs->common.reg017.slice_num = dxva_cxt->slice_count;  in hal_h265d_vdpu34x_gen_regs()
961             hw_regs->common.reg012.fbc_e = 1;  in hal_h265d_vdpu34x_gen_regs()
962             hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;  in hal_h265d_vdpu34x_gen_regs()
963             hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;  in hal_h265d_vdpu34x_gen_regs()
964             hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;  in hal_h265d_vdpu34x_gen_regs()
966             hw_regs->common.reg012.fbc_e = 0;  in hal_h265d_vdpu34x_gen_regs()
967             hw_regs->common.reg018.y_hor_virstride = stride_y >> 4;  in hal_h265d_vdpu34x_gen_regs()
968             hw_regs->common.reg019.uv_hor_virstride = stride_uv >> 4;  in hal_h265d_vdpu34x_gen_regs()
969             hw_regs->common.reg020_y_virstride.y_virstride = virstrid_y >> 4;  in hal_h265d_vdpu34x_gen_regs()
995         hw_regs->common.reg012.wait_reset_en = 1;  in hal_h265d_vdpu34x_gen_regs()
1015     hw_regs->common.reg016_str_len              = ((dxva_cxt->bitstream_size + 15)  in hal_h265d_vdpu34x_gen_regs()
1017     hw_regs->common.reg016_str_len = stream_buf_size > hw_regs->common.reg016_str_len ?  in hal_h265d_vdpu34x_gen_regs()
1018                                      hw_regs->common.reg016_str_len : stream_buf_size;  in hal_h265d_vdpu34x_gen_regs()
1020     aglin_offset =  hw_regs->common.reg016_str_len - dxva_cxt->bitstream_size;  in hal_h265d_vdpu34x_gen_regs()
1025     hw_regs->common.reg010.dec_e                = 1;  in hal_h265d_vdpu34x_gen_regs()
1026     hw_regs->common.reg011.dec_timeout_e        = 1;  in hal_h265d_vdpu34x_gen_regs()
1027     hw_regs->common.reg012.wr_ddr_align_en      = dxva_cxt->pp.tiles_enabled_flag  in hal_h265d_vdpu34x_gen_regs()
1029     hw_regs->common.reg012.colmv_compress_en    = COLMV_COMPRESS_EN;  in hal_h265d_vdpu34x_gen_regs()
1032         hw_regs->common.reg026.swreg_block_gating_e = 0xfffef;  in hal_h265d_vdpu34x_gen_regs()
1033         hw_regs->common.reg024.cabac_err_en_lowbits = 0;  in hal_h265d_vdpu34x_gen_regs()
1034         hw_regs->common.reg025.cabac_err_en_highbits = 0;  in hal_h265d_vdpu34x_gen_regs()
1036         hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff;  in hal_h265d_vdpu34x_gen_regs()
1037         hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff;  in hal_h265d_vdpu34x_gen_regs()
1038         hw_regs->common.reg026.swreg_block_gating_e = 0xfffff;  in hal_h265d_vdpu34x_gen_regs()
1041     hw_regs->common.reg011.dec_clkgate_e    = 1;  in hal_h265d_vdpu34x_gen_regs()
1042     hw_regs->common.reg011.dec_e_strmd_clkgate_dis = 0;  in hal_h265d_vdpu34x_gen_regs()
1043     hw_regs->common.reg026.reg_cfg_gating_en = 1;  in hal_h265d_vdpu34x_gen_regs()
1044     hw_regs->common.reg032_timeout_threshold = 0x3ffff;  in hal_h265d_vdpu34x_gen_regs()
1089                     hw_regs->common.reg021.error_intra_mode = 0;  in hal_h265d_vdpu34x_gen_regs()
1104             if (hw_regs->common.reg013.h26x_error_mode &&  in hal_h265d_vdpu34x_gen_regs()
1105                 !hw_regs->common.reg021.error_intra_mode &&  in hal_h265d_vdpu34x_gen_regs()
1138     hw_regs->common.reg013.timeout_mode = 1;  in hal_h265d_vdpu34x_gen_regs()
1139     hw_regs->common.reg013.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag;  in hal_h265d_vdpu34x_gen_regs()
1141     hw_regs->common.reg011.buf_empty_en = 1;  in hal_h265d_vdpu34x_gen_regs()
1147     vdpu34x_setup_statistic(&hw_regs->common, &hw_regs->statistic);  in hal_h265d_vdpu34x_gen_regs()
1192         wr_cfg.reg = &hw_regs->common;  in hal_h265d_vdpu34x_start()
1193         wr_cfg.size = sizeof(hw_regs->common);  in hal_h265d_vdpu34x_start()