317     if (vp9_hw_regs->common.reg012.fbc_e) {  in vp9d_refine_rcb_size()
323     if (vp9_hw_regs->common.reg012.fbc_e) {  in vp9d_refine_rcb_size()
585             vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = frame_ctx_id + 1;  in hal_vp9d_vdpu34x_gen_regs()
590             vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = 0;  in hal_vp9d_vdpu34x_gen_regs()
601         vp9_hw_regs->common.reg028.swreg_vp9_wr_prob_idx = frame_ctx_id + 1;  in hal_vp9d_vdpu34x_gen_regs()
609 …vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress…  in hal_vp9d_vdpu34x_gen_regs()
610     vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type;  in hal_vp9d_vdpu34x_gen_regs()
611     vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec  in hal_vp9d_vdpu34x_gen_regs()
612     vp9_hw_regs->common.reg016_str_len = ((stream_len + 15) & (~15)) + 0x80;  in hal_vp9d_vdpu34x_gen_regs()
616     aglin_offset = vp9_hw_regs->common.reg016_str_len - stream_len;  in hal_vp9d_vdpu34x_gen_regs()
635             vp9_hw_regs->common.reg012.fbc_e = 1;  in hal_vp9d_vdpu34x_gen_regs()
636             vp9_hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;  in hal_vp9d_vdpu34x_gen_regs()
637             vp9_hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;  in hal_vp9d_vdpu34x_gen_regs()
638             vp9_hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;  in hal_vp9d_vdpu34x_gen_regs()
644             vp9_hw_regs->common.reg012.fbc_e = 0;  in hal_vp9d_vdpu34x_gen_regs()
645             vp9_hw_regs->common.reg018.y_hor_virstride = sw_y_hor_virstride;  in hal_vp9d_vdpu34x_gen_regs()
646             vp9_hw_regs->common.reg019.uv_hor_virstride = sw_uv_hor_virstride;  in hal_vp9d_vdpu34x_gen_regs()
647             vp9_hw_regs->common.reg020_y_virstride.y_virstride = sw_y_virstride;  in hal_vp9d_vdpu34x_gen_regs()
792     vp9_hw_regs->common.reg010.dec_e            = 1;  in hal_vp9d_vdpu34x_gen_regs()
793     vp9_hw_regs->common.reg011.dec_timeout_e    = 1;  in hal_vp9d_vdpu34x_gen_regs()
794     vp9_hw_regs->common.reg011.buf_empty_en     = 1;  in hal_vp9d_vdpu34x_gen_regs()
795     vp9_hw_regs->common.reg011.dec_clkgate_e    = 1;  in hal_vp9d_vdpu34x_gen_regs()
796     vp9_hw_regs->common.reg011.dec_e_strmd_clkgate_dis = 0;  in hal_vp9d_vdpu34x_gen_regs()
798     vp9_hw_regs->common.reg012.wait_reset_en    = 1;  in hal_vp9d_vdpu34x_gen_regs()
799     vp9_hw_regs->common.reg013.timeout_mode     = 1;  in hal_vp9d_vdpu34x_gen_regs()
801     vp9_hw_regs->common.reg026.swreg_block_gating_e =  in hal_vp9d_vdpu34x_gen_regs()
803     vp9_hw_regs->common.reg026.reg_cfg_gating_en = 1;  in hal_vp9d_vdpu34x_gen_regs()
804     vp9_hw_regs->common.reg032_timeout_threshold = 0x3ffff;  in hal_vp9d_vdpu34x_gen_regs()
842     vdpu34x_setup_statistic(&vp9_hw_regs->common, &vp9_hw_regs->statistic);  in hal_vp9d_vdpu34x_gen_regs()
876         tmp = (RK_U32 *)&hw_regs->common;  in hal_vp9d_vdpu34x_start()
877         for (i = 0; i < sizeof(hw_regs->common) / 4; i++) {  in hal_vp9d_vdpu34x_start()
905         wr_cfg.reg = &hw_regs->common;  in hal_vp9d_vdpu34x_start()
906         wr_cfg.size = sizeof(hw_regs->common);  in hal_vp9d_vdpu34x_start()