1 /* SPDX-License-Identifier: Apache-2.0 */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "hal_h265e_v510"
7
8 #include <string.h>
9 #include <math.h>
10 #include <limits.h>
11
12 #include "mpp_env.h"
13 #include "mpp_mem.h"
14 #include "mpp_common.h"
15 #include "mpp_frame_impl.h"
16 #include "mpp_packet_impl.h"
17 #include "mpp_enc_cb_param.h"
18
19 #include "rkv_enc_def.h"
20 #include "h265e_syntax_new.h"
21 #include "h265e_dpb.h"
22 #include "hal_bufs.h"
23 #include "hal_h265e_debug.h"
24 #include "hal_h265e_vepu510.h"
25 #include "hal_h265e_vepu510_reg.h"
26 #include "hal_h265e_stream_amend.h"
27
28 #include "vepu5xx_common.h"
29 #include "vepu510_common.h"
30
31 #define MAX_FRAME_TASK_NUM 2
32 #define H265E_LAMBDA_TAB_SIZE (52 * sizeof(RK_U32))
33
34 #define hal_h265e_err(fmt, ...) \
35 do {\
36 mpp_err_f(fmt, ## __VA_ARGS__);\
37 } while (0)
38
39 typedef struct Vepu510H265Fbk_t {
40 RK_U32 hw_status; /* 0:corret, 1:error */
41 RK_U32 frame_type;
42 RK_U32 qp_sum;
43 RK_U32 out_strm_size;
44 RK_U32 out_hw_strm_size;
45 RK_S64 sse_sum;
46 RK_U32 st_lvl64_inter_num;
47 RK_U32 st_lvl32_inter_num;
48 RK_U32 st_lvl16_inter_num;
49 RK_U32 st_lvl8_inter_num;
50 RK_U32 st_lvl32_intra_num;
51 RK_U32 st_lvl16_intra_num;
52 RK_U32 st_lvl8_intra_num;
53 RK_U32 st_lvl4_intra_num;
54 RK_U32 st_cu_num_qp[52];
55 RK_U32 st_madp;
56 RK_U32 st_madi;
57 RK_U32 st_mb_num;
58 RK_U32 st_ctu_num;
59 RK_U32 st_smear_cnt[5];
60 RK_S32 reg_idx;
61 RK_U32 acc_cover16_num;
62 RK_U32 acc_bndry16_num;
63 RK_U32 acc_zero_mv;
64 RK_S8 tgt_sub_real_lvl[6];
65 } Vepu510H265Fbk;
66
67 typedef struct Vepu510H265eFrmCfg_t {
68 RK_S32 frame_count;
69 RK_S32 frame_type;
70
71 /* dchs cfg on frame parallel */
72 RK_S32 dchs_curr_idx;
73 RK_S32 dchs_prev_idx;
74
75 /* hal dpb management slot idx */
76 RK_S32 hal_curr_idx;
77 RK_S32 hal_refr_idx;
78
79 /* regs cfg */
80 H265eV510RegSet *regs_set;
81 H265eV510StatusElem *regs_ret;
82
83 /* hardware return info collection cfg */
84 Vepu510H265Fbk feedback;
85
86 /* osd cfg */
87 Vepu5xxOsdCfg osd_cfg;
88 void *roi_data;
89
90 /* roi buffer for qpmap or gdr */
91 MppBuffer roir_buf;
92 RK_S32 roir_buf_size;
93 void *roi_base_cfg_sw_buf;
94
95 /* variable length cfg */
96 MppDevRegOffCfgs *reg_cfg;
97 } Vepu510H265eFrmCfg;
98
99 typedef struct H265eV510HalContext_t {
100 MppEncHalApi api;
101 MppDev dev;
102 void *regs;
103 void *reg_out;
104 Vepu510H265eFrmCfg *frms[MAX_FRAME_TASK_NUM];
105
106 /* current used frame config */
107 Vepu510H265eFrmCfg *frm;
108
109 /* slice split poll cfg */
110 RK_S32 poll_slice_max;
111 RK_S32 poll_cfg_size;
112 MppDevPollCfg *poll_cfgs;
113 MppCbCtx *output_cb;
114
115 /* @frame_cnt starts from ZERO */
116 RK_S32 frame_count;
117
118 /* frame parallel info */
119 RK_S32 task_cnt;
120 RK_S32 task_idx;
121
122 /* dchs cfg */
123 RK_S32 curr_idx;
124 RK_S32 prev_idx;
125
126 Vepu510H265Fbk feedback;
127 Vepu510H265Fbk last_frame_fb;
128 void *dump_files;
129 RK_U32 frame_cnt_gen_ready;
130
131 RK_S32 frame_type;
132 RK_S32 last_frame_type;
133
134 MppBufferGroup roi_grp;
135 void *roi_data;
136 MppEncCfgSet *cfg;
137 MppDevRegOffCfgs *reg_cfg;
138 H265eSyntax_new *syn;
139 H265eDpb *dpb;
140
141 RK_U32 enc_mode;
142 RK_U32 frame_size;
143 RK_S32 max_buf_cnt;
144 RK_S32 hdr_status;
145 void *input_fmt;
146 RK_U8 *src_buf;
147 RK_U8 *dst_buf;
148 RK_S32 buf_size;
149 RK_U32 frame_num;
150 HalBufs dpb_bufs;
151 RK_S32 fbc_header_len;
152 RK_U32 title_num;
153
154 RK_S32 qpmap_en;
155 RK_S32 smart_en;
156 RK_S32 sp_enc_en;
157
158 /* external line buffer over 3K */
159 MppBufferGroup ext_line_buf_grp;
160 RK_S32 ext_line_buf_size;
161 MppBuffer ext_line_buf;
162 MppBuffer buf_pass1;
163 MppBuffer ext_line_bufs[MAX_FRAME_TASK_NUM];
164
165 void *tune;
166 } H265eV510HalContext;
167
168 #include "hal_h265e_vepu510_tune.c"
169
170 static RK_S32 atf_b32_skip_thd2[4] = {15, 15, 15, 200};
171 static RK_S32 atf_b32_skip_thd3[4] = {72, 72, 72, 1000};
172 static RK_S32 atf_b32_skip_wgt0[4] = {16, 20, 20, 16};
173 static RK_S32 atf_b32_skip_wgt3[4] = {16, 16, 16, 17};
174 static RK_S32 atf_b16_skip_thd2[4] = {15, 15, 15, 200};
175 static RK_S32 atf_b16_skip_thd3[4] = {25, 25, 25, 1000};
176 static RK_S32 atf_b16_skip_wgt0[4] = {16, 20, 20, 16};
177 static RK_S32 atf_b16_skip_wgt3[4] = {16, 16, 16, 17};
178 static RK_S32 atf_b32_intra_thd0[4] = {20, 20, 20, 24};
179 static RK_S32 atf_b32_intra_thd1[4] = {40, 40, 40, 48};
180 static RK_S32 atf_b32_intra_thd2[4] = {60, 72, 72, 96};
181 static RK_S32 atf_b32_intra_wgt0[4] = {16, 22, 27, 28};
182 static RK_S32 atf_b32_intra_wgt1[4] = {16, 20, 25, 26};
183 static RK_S32 atf_b32_intra_wgt2[4] = {16, 18, 20, 24};
184 static RK_S32 atf_b16_intra_thd0[4] = {20, 20, 20, 24};
185 static RK_S32 atf_b16_intra_thd1[4] = {40, 40, 40, 48};
186 static RK_S32 atf_b16_intra_thd2[4] = {60, 72, 72, 96};
187 static RK_S32 atf_b16_intra_wgt0[4] = {16, 22, 27, 28};
188 static RK_S32 atf_b16_intra_wgt1[4] = {16, 20, 25, 26};
189 static RK_S32 atf_b16_intra_wgt2[4] = {16, 18, 20, 24};
190
191 static RK_S32 smear_qp_strength[8] = {4, 6, 7, 7, 3, 5, 7, 7};
192 static RK_S32 smear_strength[8] = {1, 1, 1, 1, 1, 1, 1, 1};
193 static RK_S32 smear_common_intra_r_dep0[8] = {224, 224, 200, 200, 224, 224, 200, 200};
194 static RK_S32 smear_common_intra_r_dep1[8] = {224, 224, 180, 200, 224, 224, 180, 200};
195 static RK_S32 smear_bndry_intra_r_dep0[8] = {240, 240, 240, 240, 240, 240, 240, 240};
196 static RK_S32 smear_bndry_intra_r_dep1[8] = {240, 240, 240, 240, 240, 240, 240, 240};
197 static RK_S32 smear_thre_madp_stc_cover0[8] = {20, 22, 22, 22, 20, 22, 22, 30};
198 static RK_S32 smear_thre_madp_stc_cover1[8] = {20, 22, 22, 22, 20, 22, 22, 30};
199 static RK_S32 smear_thre_madp_mov_cover0[8] = {10, 9, 9, 9, 10, 9, 9, 6};
200 static RK_S32 smear_thre_madp_mov_cover1[8] = {10, 9, 9, 9, 10, 9, 9, 6};
201
202 static RK_S32 smear_flag_cover_thd0[8] = {12, 13, 13, 13, 12, 13, 13, 17};
203 static RK_S32 smear_flag_cover_thd1[8] = {61, 70, 70, 70, 61, 70, 70, 90};
204 static RK_S32 smear_flag_bndry_thd0[8] = {12, 12, 12, 12, 12, 12, 12, 12};
205 static RK_S32 smear_flag_bndry_thd1[8] = {73, 73, 73, 73, 73, 73, 73, 73};
206
207 static RK_S32 smear_flag_cover_wgt[3] = {1, 0, -3};
208 static RK_S32 smear_flag_cover_intra_wgt0[3] = { -12, 0, 12};
209 static RK_S32 smear_flag_cover_intra_wgt1[3] = { -12, 0, 12};
210 static RK_S32 smear_flag_bndry_wgt[3] = {0, 0, 0};
211 static RK_S32 smear_flag_bndry_intra_wgt0[3] = { -12, 0, 12};
212 static RK_S32 smear_flag_bndry_intra_wgt1[3] = { -12, 0, 12};
213
214 static RK_U32 rdo_lambda_table_I[60] = {
215 0x00000012, 0x00000017,
216 0x0000001d, 0x00000024, 0x0000002e, 0x0000003a,
217 0x00000049, 0x0000005c, 0x00000074, 0x00000092,
218 0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
219 0x000001cf, 0x00000248, 0x000002df, 0x0000039f,
220 0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
221 0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb,
222 0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
223 0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec,
224 0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
225 0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89,
226 0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
227 0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20,
228 0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
229 0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85,
230 0x00b7d902, 0x00e7a232
231 };
232
233 static RK_U32 rdo_lambda_table_P[60] = {
234 0x0000002c, 0x00000038, 0x00000044, 0x00000058,
235 0x00000070, 0x00000089, 0x000000b0, 0x000000e0,
236 0x00000112, 0x00000160, 0x000001c0, 0x00000224,
237 0x000002c0, 0x00000380, 0x00000448, 0x00000580,
238 0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
239 0x00001120, 0x00001600, 0x00001c00, 0x00002240,
240 0x00002c00, 0x00003800, 0x00004480, 0x00005800,
241 0x00007000, 0x00008900, 0x0000b000, 0x0000e000,
242 0x00011200, 0x00016000, 0x0001c000, 0x00022400,
243 0x0002c000, 0x00038000, 0x00044800, 0x00058000,
244 0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
245 0x00112000, 0x00160000, 0x001c0000, 0x00224000,
246 0x002c0000, 0x00380000, 0x00448000, 0x00580000,
247 0x00700000, 0x00890000, 0x00b00000, 0x00e00000,
248 0x01120000, 0x01600000, 0x01c00000, 0x02240000,
249 };
250
251 static RK_U8 vepu510_h265_cqm_intra8[64] = {
252 16, 16, 16, 16, 17, 18, 21, 24,
253 16, 16, 16, 16, 17, 19, 22, 25,
254 16, 16, 17, 18, 20, 22, 25, 29,
255 16, 16, 18, 21, 24, 27, 31, 36,
256 17, 17, 20, 24, 30, 35, 41, 47,
257 18, 19, 22, 27, 35, 44, 54, 65,
258 21, 22, 25, 31, 41, 54, 70, 88,
259 24, 25, 29, 36, 47, 65, 88, 115
260 };
261
262 static RK_U8 vepu510_h265_cqm_inter8[64] = {
263 16, 16, 16, 16, 17, 18, 20, 24,
264 16, 16, 16, 17, 18, 20, 24, 25,
265 16, 16, 17, 18, 20, 24, 25, 28,
266 16, 17, 18, 20, 24, 25, 28, 33,
267 17, 18, 20, 24, 25, 28, 33, 41,
268 18, 20, 24, 25, 28, 33, 41, 54,
269 20, 24, 25, 28, 33, 41, 54, 71,
270 24, 25, 28, 33, 41, 54, 71, 91
271 };
272
setup_ext_line_bufs(H265eV510HalContext * ctx)273 static void setup_ext_line_bufs(H265eV510HalContext *ctx)
274 {
275 RK_S32 i;
276
277 for (i = 0; i < ctx->task_cnt; i++) {
278 if (ctx->ext_line_bufs[i])
279 continue;
280
281 mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
282 ctx->ext_line_buf_size);
283 }
284 }
285
clear_ext_line_bufs(H265eV510HalContext * ctx)286 static void clear_ext_line_bufs(H265eV510HalContext *ctx)
287 {
288 RK_S32 i;
289
290 for (i = 0; i < ctx->task_cnt; i++) {
291 if (ctx->ext_line_bufs[i]) {
292 mpp_buffer_put(ctx->ext_line_bufs[i]);
293 ctx->ext_line_bufs[i] = NULL;
294 }
295 }
296 }
297
vepu510_h265_setup_hal_bufs(H265eV510HalContext * ctx)298 static MPP_RET vepu510_h265_setup_hal_bufs(H265eV510HalContext *ctx)
299 {
300 MPP_RET ret = MPP_OK;
301 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
302 RK_U32 frame_size;
303 VepuFmt input_fmt = VEPU5xx_FMT_YUV420P;
304 RK_S32 mb_wd64, mb_h64;
305 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
306 MppEncPrepCfg *prep = &ctx->cfg->prep;
307 RK_S32 old_max_cnt = ctx->max_buf_cnt;
308 RK_S32 new_max_cnt = 4;
309 RK_S32 alignment = 32;
310 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment);
311
312 hal_h265e_enter();
313
314 mb_wd64 = (prep->width + 63) / 64;
315 mb_h64 = (prep->height + 63) / 64 + 1;
316
317 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
318 vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);
319 input_fmt = (VepuFmt)fmt->format;
320 switch (input_fmt) {
321 case VEPU5xx_FMT_YUV400:
322 break;
323 case VEPU5xx_FMT_YUV420P:
324 case VEPU5xx_FMT_YUV420SP: {
325 frame_size = frame_size * 3 / 2;
326 } break;
327 case VEPU5xx_FMT_YUV422P:
328 case VEPU5xx_FMT_YUV422SP:
329 case VEPU5xx_FMT_YUYV422:
330 case VEPU5xx_FMT_UYVY422:
331 case VEPU5xx_FMT_BGR565: {
332 frame_size *= 2;
333 } break;
334 case VEPU5xx_FMT_BGR888:
335 case VEPU5xx_FMT_YUV444SP:
336 case VEPU5xx_FMT_YUV444P: {
337 frame_size *= 3;
338 } break;
339 case VEPU5xx_FMT_BGRA8888: {
340 frame_size *= 4;
341 } break;
342 default: {
343 hal_h265e_err("invalid src color space: %d\n", input_fmt);
344 return MPP_NOK;
345 }
346 }
347
348 if (ref_cfg) {
349 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
350 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
351 }
352
353 if (aligned_w > SZ_4K) {
354 RK_S32 ctu_w = (aligned_w + 31) / 32;
355 RK_S32 ext_line_buf_size = ((ctu_w - 113) * 27 + 15) / 16 * 16 * 16;
356
357 if (NULL == ctx->ext_line_buf_grp)
358 mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
359 else if (ext_line_buf_size != ctx->ext_line_buf_size) {
360 clear_ext_line_bufs(ctx);
361 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
362 }
363
364 mpp_assert(ctx->ext_line_buf_grp);
365 setup_ext_line_bufs(ctx);
366 ctx->ext_line_buf_size = ext_line_buf_size;
367 } else {
368 clear_ext_line_bufs(ctx);
369
370 if (ctx->ext_line_buf_grp) {
371 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
372 mpp_buffer_group_put(ctx->ext_line_buf_grp);
373 ctx->ext_line_buf_grp = NULL;
374 }
375 ctx->ext_line_buf_size = 0;
376 }
377
378 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
379 size_t size[4] = {0};
380 RK_S32 ctu_w = (prep->width + 31) / 32;
381 RK_S32 ctu_h = (prep->height + 31) / 32;
382
383 hal_bufs_deinit(ctx->dpb_bufs);
384 hal_bufs_init(&ctx->dpb_bufs);
385
386 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
387 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
388 size[1] = (mb_wd64 * mb_h64 << 8);
389 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
390 /* smear bufs */
391 size[3] = MPP_ALIGN(ctu_w, 16) * MPP_ALIGN(ctu_h, 16);
392 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
393
394 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
395 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
396
397 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, MPP_ARRAY_ELEMS(size), size);
398
399 ctx->frame_size = frame_size;
400 ctx->max_buf_cnt = new_max_cnt;
401 }
402 hal_h265e_leave();
403 return ret;
404 }
405
vepu510_h265_set_atr_regs(H265eVepu510Sqi * reg_sqi,MppEncSceneMode sm,int atr_level)406 static void vepu510_h265_set_atr_regs(H265eVepu510Sqi *reg_sqi, MppEncSceneMode sm, int atr_level)
407 {
408 // atr_level 0~3
409 // 0 close
410 // 1 weak
411 // 2 medium
412 // 3 strong
413 H265eVepu510Sqi *reg = reg_sqi;
414 (void)sm;
415 if (atr_level == 0) {
416 reg->block_opt_cfg.block_en = 0;
417 reg->cmplx_opt_cfg.cmplx_en = 0;
418 reg->line_opt_cfg.line_en = 0;
419 } else {
420 reg->block_opt_cfg.block_en = 0;
421 reg->cmplx_opt_cfg.cmplx_en = 0;
422 reg->line_opt_cfg.line_en = 1;
423 }
424
425 if (atr_level == 3) {
426 reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
427 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
428 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
429 reg->block_opt_cfg.block_delta_qp_flag = 3;
430
431 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
432 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
433
434 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
435 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
436
437 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
438 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
439
440 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 4;
441 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 30;//20
442 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 30;//20
443 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;//7
444 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 6;//8
445
446 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
447 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 50;
448 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 50;
449
450 reg->subj_opt_dqp0.line_thre_qp = 20;
451 reg->subj_opt_dqp0.block_strength = 4;
452 reg->subj_opt_dqp0.block_thre_qp = 30;
453 reg->subj_opt_dqp0.cmplx_strength = 4;
454 reg->subj_opt_dqp0.cmplx_thre_qp = 34;
455 reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
456 } else if (atr_level == 2) {
457 reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
458 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
459 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
460 reg->block_opt_cfg.block_delta_qp_flag = 3;
461
462 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
463 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
464
465 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
466 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
467
468 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
469 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
470
471 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
472 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
473 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
474 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
475 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
476
477 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
478 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 60;
479 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 60;
480
481 reg->subj_opt_dqp0.line_thre_qp = 25;
482 reg->subj_opt_dqp0.block_strength = 4;
483 reg->subj_opt_dqp0.block_thre_qp = 30;
484 reg->subj_opt_dqp0.cmplx_strength = 4;
485 reg->subj_opt_dqp0.cmplx_thre_qp = 34;
486 reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
487 } else {
488 reg->block_opt_cfg.block_thre_cst_best_mad = 1000;
489 reg->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
490 reg->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
491 reg->block_opt_cfg.block_delta_qp_flag = 3;
492
493 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 6000;
494 reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
495
496 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 300;
497 reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 1280;
498
499 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
500 reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 512;
501
502 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
503 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
504 reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
505 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
506 reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
507
508 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
509 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 70;
510 reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 70;
511
512 reg->subj_opt_dqp0.line_thre_qp = 30;
513 reg->subj_opt_dqp0.block_strength = 4;
514 reg->subj_opt_dqp0.block_thre_qp = 30;
515 reg->subj_opt_dqp0.cmplx_strength = 4;
516 reg->subj_opt_dqp0.cmplx_thre_qp = 34;
517 reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
518 }
519 }
520
vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi * reg_sqi,int anti_blur_level)521 static void vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi *reg_sqi, int anti_blur_level)
522 {
523 H265eVepu510Sqi *reg = reg_sqi;
524 if (anti_blur_level >= 1)
525 reg->subj_anti_blur_thd.anti_blur_en = 1;
526 else
527 reg->subj_anti_blur_thd.anti_blur_en = 0;
528 reg->subj_anti_blur_thd.blur_low_madi_thd = 5;
529 reg->subj_anti_blur_thd.blur_high_madi_thd = 27;
530 reg->subj_anti_blur_thd.blur_low_cnt_thd = 0;
531 reg->subj_anti_blur_thd.blur_hight_cnt_thd = 0;
532 reg->subj_anti_blur_thd.blur_sum_cnt_thd = 5;
533
534 reg->subj_anti_blur_sao.blur_motion_thd = 32;
535 reg->subj_anti_blur_sao.sao_ofst_thd_eo_luma = 2;
536 reg->subj_anti_blur_sao.sao_ofst_thd_bo_luma = 4;
537 reg->subj_anti_blur_sao.sao_ofst_thd_eo_chroma = 2;
538 reg->subj_anti_blur_sao.sao_ofst_thd_bo_chroma = 4;
539 }
540
vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi * reg_sqi,int atl_level)541 static void vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi *reg_sqi, int atl_level)
542 {
543 pre_cst_par* pre_i32 = (pre_cst_par*)®_sqi->preintra32_cst;
544 pre_cst_par* pre_i16 = (pre_cst_par*)®_sqi->preintra16_cst;
545
546 pre_i32->cst_madi_thd0.madi_thd0 = 5;
547 pre_i32->cst_madi_thd0.madi_thd1 = 15;
548 pre_i32->cst_madi_thd0.madi_thd2 = 5;
549 pre_i32->cst_madi_thd0.madi_thd3 = 3;
550 pre_i32->cst_madi_thd1.madi_thd4 = 3;
551 pre_i32->cst_madi_thd1.madi_thd5 = 6;
552 pre_i32->cst_madi_thd1.madi_thd6 = 7;
553 pre_i32->cst_madi_thd1.madi_thd7 = 5;
554 pre_i32->cst_madi_thd2.madi_thd8 = 10;
555 pre_i32->cst_madi_thd2.madi_thd9 = 5;
556 pre_i32->cst_madi_thd2.madi_thd10 = 7;
557 pre_i32->cst_madi_thd2.madi_thd11 = 5;
558 pre_i32->cst_madi_thd3.madi_thd12 = 7;
559 pre_i32->cst_madi_thd3.madi_thd13 = 5;
560 pre_i32->cst_madi_thd3.mode_th = 5;
561
562 pre_i32->cst_wgt0.wgt0 = 20;
563 pre_i32->cst_wgt0.wgt1 = 18;
564 pre_i32->cst_wgt0.wgt2 = 19;
565 pre_i32->cst_wgt0.wgt3 = 18;
566 pre_i32->cst_wgt1.wgt4 = 12;
567 pre_i32->cst_wgt1.wgt5 = 6;
568 pre_i32->cst_wgt1.wgt6 = 13;
569 pre_i32->cst_wgt1.wgt7 = 9;
570 pre_i32->cst_wgt2.wgt8 = 12;
571 pre_i32->cst_wgt2.wgt9 = 6;
572 pre_i32->cst_wgt2.wgt10 = 13;
573 pre_i32->cst_wgt2.wgt11 = 9;
574 pre_i32->cst_wgt3.wgt12 = 18;
575 pre_i32->cst_wgt3.wgt13 = 17;
576 pre_i32->cst_wgt3.wgt14 = 17;
577
578 pre_i16->cst_madi_thd0.madi_thd0 = 5;
579 pre_i16->cst_madi_thd0.madi_thd1 = 15;
580 pre_i16->cst_madi_thd0.madi_thd2 = 5;
581 pre_i16->cst_madi_thd0.madi_thd3 = 3;
582 pre_i16->cst_madi_thd1.madi_thd4 = 3;
583 pre_i16->cst_madi_thd1.madi_thd5 = 6;
584 pre_i16->cst_madi_thd1.madi_thd6 = 7;
585 pre_i16->cst_madi_thd1.madi_thd7 = 5;
586 pre_i16->cst_madi_thd2.madi_thd8 = 10;
587 pre_i16->cst_madi_thd2.madi_thd9 = 5;
588 pre_i16->cst_madi_thd2.madi_thd10 = 7;
589 pre_i16->cst_madi_thd2.madi_thd11 = 5;
590 pre_i16->cst_madi_thd3.madi_thd12 = 7;
591 pre_i16->cst_madi_thd3.madi_thd13 = 5;
592 pre_i16->cst_madi_thd3.mode_th = 5;
593
594 pre_i16->cst_wgt0.wgt0 = 20;
595 pre_i16->cst_wgt0.wgt1 = 18;
596 pre_i16->cst_wgt0.wgt2 = 19;
597 pre_i16->cst_wgt0.wgt3 = 18;
598 pre_i16->cst_wgt1.wgt4 = 12;
599 pre_i16->cst_wgt1.wgt5 = 6;
600 pre_i16->cst_wgt1.wgt6 = 13;
601 pre_i16->cst_wgt1.wgt7 = 9;
602 pre_i16->cst_wgt2.wgt8 = 12;
603 pre_i16->cst_wgt2.wgt9 = 6;
604 pre_i16->cst_wgt2.wgt10 = 13;
605 pre_i16->cst_wgt2.wgt11 = 9;
606 pre_i16->cst_wgt3.wgt12 = 18;
607 pre_i16->cst_wgt3.wgt13 = 17;
608 pre_i16->cst_wgt3.wgt14 = 17;
609
610 pre_i32->cst_madi_thd3.qp_thd = 28;
611 pre_i32->cst_wgt3.lambda_mv_bit_0 = 5; // lv32
612 pre_i32->cst_wgt3.lambda_mv_bit_1 = 4; // lv16
613 pre_i16->cst_wgt3.lambda_mv_bit_0 = 4; // lv8
614 pre_i16->cst_wgt3.lambda_mv_bit_1 = 3; // lv4
615 if (atl_level >= 1)
616 pre_i32->cst_wgt3.anti_strp_e = 1;
617 else
618 pre_i32->cst_wgt3.anti_strp_e = 0;
619 }
620
vepu510_h265_rdo_cfg(H265eV510HalContext * ctx,H265eVepu510Sqi * reg,MppEncSceneMode sm)621 static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, MppEncSceneMode sm)
622 {
623 reg->subj_opt_cfg.subj_opt_en = 1;
624 reg->subj_opt_cfg.subj_opt_strength = 3;
625 reg->subj_opt_cfg.aq_subj_en = (sm == MPP_ENC_SCENE_MODE_IPC);
626 reg->subj_opt_cfg.aq_subj_strength = 4;
627
628 /* skin_opt */
629 reg->skin_opt_cfg.skin_en = 0;
630 reg->skin_opt_cfg.skin_strength = 3;
631 reg->skin_opt_cfg.thre_uvsqr16_skin = 128;
632 reg->skin_opt_cfg.skin_thre_cst_best_mad = 1000;
633 reg->skin_opt_cfg.skin_thre_cst_best_grdn_blk = 98;
634 reg->skin_opt_cfg.frame_skin_ratio = 3;
635 reg->skin_chrm_thd.thre_sum_mad_intra = 3;
636 reg->skin_chrm_thd.thre_sum_grdn_blk_intra = 3;
637 reg->skin_chrm_thd.vld_thre_skin_v = 7;
638 reg->skin_chrm_thd.thre_min_skin_u = 107;
639 reg->skin_chrm_thd.thre_max_skin_u = 129;
640 reg->skin_chrm_thd.thre_min_skin_v = 135;
641 reg->subj_opt_dqp1.skin_thre_qp = 31;
642
643 /* 0x00002100 reg2112 */
644 reg->cudecis_thd0.base_thre_rough_mad32_intra = 9;
645 reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10;
646 reg->cudecis_thd0.delta1_thre_rough_mad32_intra = 55;
647 reg->cudecis_thd0.delta2_thre_rough_mad32_intra = 55;
648 reg->cudecis_thd0.delta3_thre_rough_mad32_intra = 66;
649 reg->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2;
650
651 /* 0x00002104 reg2113 */
652 reg->cudecis_thd1.delta4_thre_rough_mad32_intra_high2 = 2;
653 reg->cudecis_thd1.delta5_thre_rough_mad32_intra = 74;
654 reg->cudecis_thd1.delta6_thre_rough_mad32_intra = 106;
655 reg->cudecis_thd1.base_thre_fine_mad32_intra = 8;
656 reg->cudecis_thd1.delta0_thre_fine_mad32_intra = 0;
657 reg->cudecis_thd1.delta1_thre_fine_mad32_intra = 13;
658 reg->cudecis_thd1.delta2_thre_fine_mad32_intra_low3 = 6;
659
660 /* 0x00002108 reg2114 */
661 reg->cudecis_thd2.delta2_thre_fine_mad32_intra_high2 = 1;
662 reg->cudecis_thd2.delta3_thre_fine_mad32_intra = 17;
663 reg->cudecis_thd2.delta4_thre_fine_mad32_intra = 23;
664 reg->cudecis_thd2.delta5_thre_fine_mad32_intra = 50;
665 reg->cudecis_thd2.delta6_thre_fine_mad32_intra = 54;
666 reg->cudecis_thd2.base_thre_str_edge_mad32_intra = 6;
667 reg->cudecis_thd2.delta0_thre_str_edge_mad32_intra = 0;
668 reg->cudecis_thd2.delta1_thre_str_edge_mad32_intra = 0;
669
670 /* 0x0000210c reg2115 */
671 reg->cudecis_thd3.delta2_thre_str_edge_mad32_intra = 3;
672 reg->cudecis_thd3.delta3_thre_str_edge_mad32_intra = 8;
673 reg->cudecis_thd3.base_thre_str_edge_bgrad32_intra = 25;
674 reg->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra = 0;
675 reg->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra = 0;
676 reg->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra = 7;
677 reg->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra = 19;
678 reg->cudecis_thd3.base_thre_mad16_intra = 6;
679 reg->cudecis_thd3.delta0_thre_mad16_intra = 0;
680
681 /* 0x00002110 reg2116 */
682 reg->cudecis_thd4.delta1_thre_mad16_intra = 3;
683 reg->cudecis_thd4.delta2_thre_mad16_intra = 3;
684 reg->cudecis_thd4.delta3_thre_mad16_intra = 24;
685 reg->cudecis_thd4.delta4_thre_mad16_intra = 28;
686 reg->cudecis_thd4.delta5_thre_mad16_intra = 40;
687 reg->cudecis_thd4.delta6_thre_mad16_intra = 52;
688 reg->cudecis_thd4.delta0_thre_mad16_ratio_intra = 7;
689
690 /* 0x00002114 reg2117 */
691 reg->cudecis_thd5.delta1_thre_mad16_ratio_intra = 7;
692 reg->cudecis_thd5.delta2_thre_mad16_ratio_intra = 2;
693 reg->cudecis_thd5.delta3_thre_mad16_ratio_intra = 2;
694 reg->cudecis_thd5.delta4_thre_mad16_ratio_intra = 0;
695 reg->cudecis_thd5.delta5_thre_mad16_ratio_intra = 0;
696 reg->cudecis_thd5.delta6_thre_mad16_ratio_intra = 0;
697 reg->cudecis_thd5.delta7_thre_mad16_ratio_intra = 4;
698 reg->cudecis_thd5.delta0_thre_rough_bgrad32_intra = 1;
699 reg->cudecis_thd5.delta1_thre_rough_bgrad32_intra = 5;
700 reg->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4 = 8;
701
702 /* 0x00002118 reg2118 */
703 reg->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2 = 2;
704 reg->cudecis_thd6.delta3_thre_rough_bgrad32_intra = 540;
705 reg->cudecis_thd6.delta4_thre_rough_bgrad32_intra = 692;
706 reg->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10 = 866;
707
708 /* 0x0000211c reg2119 */
709 reg->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1 = 1;
710 reg->cudecis_thd7.delta6_thre_rough_bgrad32_intra = 3286;
711 reg->cudecis_thd7.delta7_thre_rough_bgrad32_intra = 6620;
712 reg->cudecis_thd7.delta0_thre_bgrad16_ratio_intra = 8;
713 reg->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2 = 3;
714
715 /* 0x00002120 reg2120 */
716 reg->cudecis_thdt8.delta1_thre_bgrad16_ratio_intra_high2 = 2;
717 reg->cudecis_thdt8.delta2_thre_bgrad16_ratio_intra = 15;
718 reg->cudecis_thdt8.delta3_thre_bgrad16_ratio_intra = 15;
719 reg->cudecis_thdt8.delta4_thre_bgrad16_ratio_intra = 13;
720 reg->cudecis_thdt8.delta5_thre_bgrad16_ratio_intra = 13;
721 reg->cudecis_thdt8.delta6_thre_bgrad16_ratio_intra = 7;
722 reg->cudecis_thdt8.delta7_thre_bgrad16_ratio_intra = 15;
723 reg->cudecis_thdt8.delta0_thre_fme_ratio_inter = 4;
724 reg->cudecis_thdt8.delta1_thre_fme_ratio_inter = 4;
725
726 /* 0x00002124 reg2121 */
727 reg->cudecis_thd9.delta2_thre_fme_ratio_inter = 3;
728 reg->cudecis_thd9.delta3_thre_fme_ratio_inter = 2;
729 reg->cudecis_thd9.delta4_thre_fme_ratio_inter = 0;
730 reg->cudecis_thd9.delta5_thre_fme_ratio_inter = 0;
731 reg->cudecis_thd9.delta6_thre_fme_ratio_inter = 0;
732 reg->cudecis_thd9.delta7_thre_fme_ratio_inter = 0;
733 reg->cudecis_thd9.base_thre_fme32_inter = 4;
734 reg->cudecis_thd9.delta0_thre_fme32_inter = 2;
735 reg->cudecis_thd9.delta1_thre_fme32_inter = 7;
736 reg->cudecis_thd9.delta2_thre_fme32_inter = 12;
737
738 /* 0x00002128 reg2122 */
739 reg->cudecis_thd10.delta3_thre_fme32_inter = 23;
740 reg->cudecis_thd10.delta4_thre_fme32_inter = 41;
741 reg->cudecis_thd10.delta5_thre_fme32_inter = 71;
742 reg->cudecis_thd10.delta6_thre_fme32_inter = 123;
743 reg->cudecis_thd10.thre_cme32_inter = 48;
744
745 /* 0x0000212c reg2123 */
746 reg->cudecis_thd11.delta0_thre_mad_fme_ratio_inter = 0;
747 reg->cudecis_thd11.delta1_thre_mad_fme_ratio_inter = 7;
748 reg->cudecis_thd11.delta2_thre_mad_fme_ratio_inter = 7;
749 reg->cudecis_thd11.delta3_thre_mad_fme_ratio_inter = 6;
750 reg->cudecis_thd11.delta4_thre_mad_fme_ratio_inter = 5;
751 reg->cudecis_thd11.delta5_thre_mad_fme_ratio_inter = 4;
752 reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4;
753 reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4;
754
755 vepu510_h265_set_anti_stripe_regs(reg, ctx->cfg->tune.atl_str);
756 if (ctx->frame_type == INTRA_FRAME)
757 vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_i);
758 else
759 vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_p);
760
761 if (ctx->frame_type == INTRA_FRAME)
762 vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_i);
763 else
764 vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_p);
765 }
766
vepu510_h265_atf_cfg(H265eVepu510Sqi * reg,RK_S32 atf_str)767 static void vepu510_h265_atf_cfg(H265eVepu510Sqi *reg, RK_S32 atf_str)
768 {
769 rdo_skip_par *p_rdo_skip = NULL;
770 rdo_noskip_par *p_rdo_noskip = NULL;
771
772 p_rdo_skip = ®->rdo_b32_skip;
773 p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
774 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
775 p_rdo_skip->atf_thd1.madp_thd2 = atf_b32_skip_thd2[atf_str];
776 p_rdo_skip->atf_thd1.madp_thd3 = atf_b32_skip_thd3[atf_str];
777 p_rdo_skip->atf_wgt0.wgt0 = atf_b32_skip_wgt0[atf_str];
778 p_rdo_skip->atf_wgt0.wgt1 = 16 ;
779 p_rdo_skip->atf_wgt0.wgt2 = 16 ;
780 p_rdo_skip->atf_wgt0.wgt3 = atf_b32_skip_wgt3[atf_str];
781
782 p_rdo_noskip = ®->rdo_b32_inter;
783 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
784 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
785 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
786 p_rdo_noskip->atf_wgt.wgt0 = 16;
787 p_rdo_noskip->atf_wgt.wgt1 = 16;
788 p_rdo_noskip->atf_wgt.wgt2 = 16;
789
790 p_rdo_noskip = ®->rdo_b32_intra;
791 p_rdo_noskip->ratf_thd0.madp_thd0 = atf_b32_intra_thd0[atf_str];
792 p_rdo_noskip->ratf_thd0.madp_thd1 = atf_b32_intra_thd1[atf_str];
793 p_rdo_noskip->ratf_thd1.madp_thd2 = atf_b32_intra_thd2[atf_str];
794 p_rdo_noskip->atf_wgt.wgt0 = atf_b32_intra_wgt0[atf_str];
795 p_rdo_noskip->atf_wgt.wgt1 = atf_b32_intra_wgt1[atf_str];
796 p_rdo_noskip->atf_wgt.wgt2 = atf_b32_intra_wgt2[atf_str];
797
798 p_rdo_skip = ®->rdo_b16_skip;
799 p_rdo_skip->atf_thd0.madp_thd0 = 1 ;
800 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
801 p_rdo_skip->atf_thd1.madp_thd2 = atf_b16_skip_thd2[atf_str];
802 p_rdo_skip->atf_thd1.madp_thd3 = atf_b16_skip_thd3[atf_str];
803 p_rdo_skip->atf_wgt0.wgt0 = atf_b16_skip_wgt0[atf_str];
804 p_rdo_skip->atf_wgt0.wgt1 = 16 ;
805 p_rdo_skip->atf_wgt0.wgt2 = 16 ;
806 p_rdo_skip->atf_wgt0.wgt3 = atf_b16_skip_wgt3[atf_str];
807 p_rdo_skip->atf_wgt1.wgt4 = 16 ;
808
809 p_rdo_noskip = ®->rdo_b16_inter;
810 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
811 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
812 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
813 p_rdo_noskip->atf_wgt.wgt0 = 16;
814 p_rdo_noskip->atf_wgt.wgt1 = 16;
815 p_rdo_noskip->atf_wgt.wgt2 = 16;
816 p_rdo_noskip->atf_wgt.wgt3 = 16;
817
818 p_rdo_noskip = ®->rdo_b16_intra;
819 p_rdo_noskip->ratf_thd0.madp_thd0 = atf_b16_intra_thd0[atf_str];
820 p_rdo_noskip->ratf_thd0.madp_thd1 = atf_b16_intra_thd1[atf_str];
821 p_rdo_noskip->ratf_thd1.madp_thd2 = atf_b16_intra_thd2[atf_str];
822 p_rdo_noskip->atf_wgt.wgt0 = atf_b16_intra_wgt0[atf_str];
823 p_rdo_noskip->atf_wgt.wgt1 = atf_b16_intra_wgt1[atf_str];
824 p_rdo_noskip->atf_wgt.wgt2 = atf_b16_intra_wgt2[atf_str];
825 p_rdo_noskip->atf_wgt.wgt3 = 16;
826 }
827
vepu510_h265_smear_cfg(H265eVepu510Sqi * reg,H265eV510HalContext * ctx)828 static void vepu510_h265_smear_cfg(H265eVepu510Sqi *reg, H265eV510HalContext *ctx)
829 {
830 RK_S32 frame_num = ctx->frame_num;
831 RK_S32 frame_keyint = (ctx->cfg->rc.gop > 0) ? ctx->cfg->rc.gop : 0x7FFFFFFF;
832 RK_U32 cover_num = ctx->feedback.acc_cover16_num;
833 RK_U32 bndry_num = ctx->feedback.acc_bndry16_num;
834 RK_U32 st_ctu_num = ctx->feedback.st_ctu_num;
835 RK_S32 deblur_en = ctx->cfg->tune.deblur_en;
836 RK_S32 deblur_str = ctx->cfg->tune.deblur_str;
837 RK_S16 flag_cover = 0;
838 RK_S16 flag_bndry = 0;
839
840 if (cover_num * 1000 < smear_flag_cover_thd0[deblur_str] * st_ctu_num)
841 flag_cover = 0;
842 else if (cover_num * 1000 < smear_flag_cover_thd1[deblur_str] * st_ctu_num)
843 flag_cover = 1;
844 else
845 flag_cover = 2;
846
847 if (bndry_num * 1000 < smear_flag_bndry_thd0[deblur_str] * st_ctu_num)
848 flag_bndry = 0;
849 else if (bndry_num * 1000 < smear_flag_bndry_thd1[deblur_str] * st_ctu_num)
850 flag_bndry = 1;
851 else
852 flag_bndry = 2;
853
854 reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0 = 64;
855 reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1 = 32;
856 reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2 = 16;
857 reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep0 = smear_common_intra_r_dep0[deblur_str] + smear_flag_cover_intra_wgt0[flag_bndry];
858 reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep1 = smear_common_intra_r_dep1[deblur_str] + smear_flag_cover_intra_wgt1[flag_bndry];
859
860 /* anti smear */
861 reg->smear_opt_cfg0.anti_smear_en = 1;
862 if (deblur_en == 0)
863 reg->smear_opt_cfg0.anti_smear_en = 0;
864 reg->smear_opt_cfg0.smear_strength = smear_strength[deblur_str] + smear_flag_bndry_wgt[flag_cover];
865 reg->smear_opt_cfg0.thre_mv_inconfor_cime = 8;
866 reg->smear_opt_cfg0.thre_mv_confor_cime = 2;
867 reg->smear_opt_cfg0.thre_mv_inconfor_cime_gmv = 8;
868 reg->smear_opt_cfg0.thre_mv_confor_cime_gmv = 2;
869 reg->smear_opt_cfg0.thre_num_mv_confor_cime = 3;
870 reg->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2;
871 reg->smear_opt_cfg0.frm_static = 1;
872
873 if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % frame_keyint == 1) {
874 reg->smear_opt_cfg0.smear_load_en = 0;
875 } else {
876 reg->smear_opt_cfg0.smear_load_en = 1;
877 }
878
879 if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % frame_keyint == frame_keyint - 1) {
880 reg->smear_opt_cfg0.smear_stor_en = 0;
881 } else {
882 reg->smear_opt_cfg0.smear_stor_en = 1;
883 }
884
885 reg->smear_opt_cfg1.dist0_frm_avg = 0;
886 reg->smear_opt_cfg1.thre_dsp_static = 10;
887 reg->smear_opt_cfg1.thre_dsp_mov = 15;
888 reg->smear_opt_cfg1.thre_dist_mv_confor_cime = 32;
889
890 reg->smear_madp_thd.thre_madp_stc_dep0 = 10;
891 reg->smear_madp_thd.thre_madp_stc_dep1 = 8;
892 reg->smear_madp_thd.thre_madp_stc_dep2 = 8;
893 reg->smear_madp_thd.thre_madp_mov_dep0 = 16;
894 reg->smear_madp_thd.thre_madp_mov_dep1 = 18;
895 reg->smear_madp_thd.thre_madp_mov_dep2 = 20;
896
897 reg->smear_stat_thd.thre_num_pt_stc_dep0 = 47;
898 reg->smear_stat_thd.thre_num_pt_stc_dep1 = 11;
899 reg->smear_stat_thd.thre_num_pt_stc_dep2 = 3;
900 reg->smear_stat_thd.thre_num_pt_mov_dep0 = 47;
901 reg->smear_stat_thd.thre_num_pt_mov_dep1 = 11;
902 reg->smear_stat_thd.thre_num_pt_mov_dep2 = 3;
903
904 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv0 = 21;
905 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv1 = 16;
906 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv0 = 48;
907 reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv1 = 34;
908
909 reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv2 = 32;
910 reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv3 = 29;
911 reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv4 = 27;
912
913 reg->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv = 0;
914 reg->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv = 3;
915 reg->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv = 0;
916 reg->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv = 3;
917 reg->smear_min_bndry_gmv.thre_split_dep0 = 2;
918 reg->smear_min_bndry_gmv.thre_zero_srgn = 8;
919 reg->smear_min_bndry_gmv.madi_thre_dep0 = 22;
920 reg->smear_min_bndry_gmv.madi_thre_dep1 = 18;
921
922 reg->smear_madp_cov_thd.thre_madp_stc_cover0 = smear_thre_madp_stc_cover0[deblur_str];
923 reg->smear_madp_cov_thd.thre_madp_stc_cover1 = smear_thre_madp_stc_cover1[deblur_str];
924 reg->smear_madp_cov_thd.thre_madp_mov_cover0 = smear_thre_madp_mov_cover0[deblur_str];
925 reg->smear_madp_cov_thd.thre_madp_mov_cover1 = smear_thre_madp_mov_cover1[deblur_str];
926 reg->smear_madp_cov_thd.smear_qp_strength = smear_qp_strength[deblur_str] + smear_flag_cover_wgt[flag_cover];
927 reg->smear_madp_cov_thd.smear_thre_qp = 30;
928
929 reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep0 = smear_bndry_intra_r_dep0[deblur_str] + smear_flag_bndry_intra_wgt0[flag_bndry];
930 reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep1 = smear_bndry_intra_r_dep1[deblur_str] + smear_flag_bndry_intra_wgt1[flag_bndry];
931 }
932
vepu510_h265_global_cfg_set(H265eV510HalContext * ctx,H265eV510RegSet * regs)933 static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSet *regs)
934 {
935 MppEncHwCfg *hw = &ctx->cfg->hw;
936 H265eVepu510Param *reg_param = ®s->reg_param;
937 H265eVepu510Sqi *reg_sqi = ®s->reg_sqi;
938 MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
939 RK_S32 atf_str = ctx->cfg->tune.anti_flicker_str;
940 RK_S32 lambda_idx = 0;
941
942 vepu510_h265_rdo_cfg(ctx, reg_sqi, sm);
943 vepu510_h265_atf_cfg(reg_sqi, atf_str);
944 vepu510_h265_smear_cfg(reg_sqi, ctx);
945 memcpy(®_param->pprd_lamb_satd_0_51[0], lamd_satd_qp_510, sizeof(lamd_satd_qp));
946
947 if (ctx->frame_type == INTRA_FRAME) {
948 reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
949 lambda_idx = ctx->cfg->tune.lambda_idx_i;
950 memcpy(®_param->rdo_wgta_qp_grpa_0_51[0],
951 &rdo_lambda_table_I[lambda_idx], H265E_LAMBDA_TAB_SIZE);
952 } else {
953 reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
954 lambda_idx = ctx->cfg->tune.lambda_idx_p;
955 memcpy(®_param->rdo_wgta_qp_grpa_0_51[0],
956 &rdo_lambda_table_P[lambda_idx], H265E_LAMBDA_TAB_SIZE);
957 }
958
959 reg_param->qnt_bias_comb.qnt_f_bias_i = 171;
960 reg_param->qnt_bias_comb.qnt_f_bias_p = 85;
961 if (hw->qbias_en) {
962 reg_param->qnt_bias_comb.qnt_f_bias_i = hw->qbias_i;
963 reg_param->qnt_bias_comb.qnt_f_bias_p = hw->qbias_p;
964 } else if (ctx->smart_en || ctx->sp_enc_en) {
965 reg_param->qnt_bias_comb.qnt_f_bias_i = 144;
966 }
967
968 /* CIME */
969 {
970 reg_param->me_sqi_comb.cime_pmv_num = 1;
971 reg_param->me_sqi_comb.cime_fuse = 1;
972 reg_param->me_sqi_comb.itp_mode = 1;
973 reg_param->me_sqi_comb.move_lambda = (sm == MPP_ENC_SCENE_MODE_IPC) ? 2 : 8;
974 reg_param->me_sqi_comb.rime_lvl_mrg = 1;
975 reg_param->me_sqi_comb.rime_prelvl_en = 3;
976 reg_param->me_sqi_comb.rime_prersu_en = 0;
977 reg_param->cime_mvd_th_comb.cime_mvd_th0 = 8;
978 reg_param->cime_mvd_th_comb.cime_mvd_th1 = 20;
979 reg_param->cime_mvd_th_comb.cime_mvd_th2 = 32;
980 reg_param->cime_madp_th_comb.cime_madp_th = (sm == MPP_ENC_SCENE_MODE_IPC) ? 16 : 0;
981
982 if (sm == MPP_ENC_SCENE_MODE_IPC) {
983 reg_param->cime_multi_comb.cime_multi0 = 8;
984 reg_param->cime_multi_comb.cime_multi1 = 12;
985 reg_param->cime_multi_comb.cime_multi2 = 16;
986 reg_param->cime_multi_comb.cime_multi3 = 20;
987 } else {
988 reg_param->cime_multi_comb.cime_multi0 = 4;
989 reg_param->cime_multi_comb.cime_multi1 = 4;
990 reg_param->cime_multi_comb.cime_multi2 = 4;
991 reg_param->cime_multi_comb.cime_multi3 = 4;
992 }
993 }
994
995 /* RIME && FME */
996 if (sm == MPP_ENC_SCENE_MODE_IPC) {
997 reg_param->rime_mvd_th_comb.rime_mvd_th0 = 1;
998 reg_param->rime_mvd_th_comb.rime_mvd_th1 = 2;
999 reg_param->rime_mvd_th_comb.fme_madp_th = 0;
1000 reg_param->rime_madp_th_comb.rime_madp_th0 = 8;
1001 reg_param->rime_madp_th_comb.rime_madp_th1 = 16;
1002 reg_param->rime_multi_comb.rime_multi0 = 4;
1003 reg_param->rime_multi_comb.rime_multi1 = 8;
1004 reg_param->rime_multi_comb.rime_multi2 = 12;
1005 } else {
1006 reg_param->rime_mvd_th_comb.rime_mvd_th0 = 0;
1007 reg_param->rime_mvd_th_comb.rime_mvd_th1 = 0;
1008 reg_param->rime_mvd_th_comb.fme_madp_th = 30;
1009 reg_param->rime_madp_th_comb.rime_madp_th0 = 0;
1010 reg_param->rime_madp_th_comb.rime_madp_th1 = 0;
1011 reg_param->rime_multi_comb.rime_multi0 = 4;
1012 reg_param->rime_multi_comb.rime_multi1 = 4;
1013 reg_param->rime_multi_comb.rime_multi2 = 4;
1014 }
1015
1016 {
1017 /* 0x1064 */
1018 regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
1019 regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
1020 regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
1021 /* 0x1068 */
1022 regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
1023 regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
1024 /* 0x106C */
1025 regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
1026
1027 /* 0x177C */
1028 reg_param->cmv_st_th_comb.cmv_th0 = 64;
1029 reg_param->cmv_st_th_comb.cmv_th1 = 96;
1030 reg_param->cmv_st_th_comb.cmv_th2 = 128;
1031 }
1032 }
1033
hal_h265e_v510_deinit(void * hal)1034 MPP_RET hal_h265e_v510_deinit(void *hal)
1035 {
1036 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
1037 RK_S32 i = 0;
1038
1039 hal_h265e_enter();
1040 MPP_FREE(ctx->poll_cfgs);
1041 MPP_FREE(ctx->input_fmt);
1042 hal_bufs_deinit(ctx->dpb_bufs);
1043
1044 for (i = 0; i < ctx->task_cnt; i++) {
1045 Vepu510H265eFrmCfg *frm = ctx->frms[i];
1046
1047 if (!frm)
1048 continue;
1049
1050 if (frm->roir_buf) {
1051 mpp_buffer_put(frm->roir_buf);
1052 frm->roir_buf = NULL;
1053 frm->roir_buf_size = 0;
1054 }
1055
1056 MPP_FREE(frm->roi_base_cfg_sw_buf);
1057
1058 if (frm->reg_cfg) {
1059 mpp_dev_multi_offset_deinit(frm->reg_cfg);
1060 frm->reg_cfg = NULL;
1061 }
1062
1063 MPP_FREE(frm->regs_set);
1064 MPP_FREE(frm->regs_ret);
1065 MPP_FREE(ctx->frms[i]);
1066 }
1067
1068 clear_ext_line_bufs(ctx);
1069
1070 if (ctx->ext_line_buf_grp) {
1071 mpp_buffer_group_put(ctx->ext_line_buf_grp);
1072 ctx->ext_line_buf_grp = NULL;
1073 }
1074
1075 if (ctx->buf_pass1) {
1076 mpp_buffer_put(ctx->buf_pass1);
1077 ctx->buf_pass1 = NULL;
1078 }
1079
1080 if (ctx->dev) {
1081 mpp_dev_deinit(ctx->dev);
1082 ctx->dev = NULL;
1083 }
1084
1085 if (ctx->reg_cfg) {
1086 mpp_dev_multi_offset_deinit(ctx->reg_cfg);
1087 ctx->reg_cfg = NULL;
1088 }
1089
1090 if (ctx->roi_grp) {
1091 mpp_buffer_group_put(ctx->roi_grp);
1092 ctx->roi_grp = NULL;
1093 }
1094
1095 if (ctx->tune) {
1096 vepu510_h265e_tune_deinit(ctx->tune);
1097 ctx->tune = NULL;
1098 }
1099
1100 hal_h265e_leave();
1101 return MPP_OK;
1102 }
1103
hal_h265e_v510_init(void * hal,MppEncHalCfg * cfg)1104 MPP_RET hal_h265e_v510_init(void *hal, MppEncHalCfg *cfg)
1105 {
1106 MPP_RET ret = MPP_OK;
1107 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
1108 RK_S32 i = 0;
1109
1110 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
1111 hal_h265e_enter();
1112
1113 ctx->task_cnt = cfg->task_cnt;
1114 mpp_assert(ctx->task_cnt && ctx->task_cnt <= MAX_FRAME_TASK_NUM);
1115 if (ctx->task_cnt > MAX_FRAME_TASK_NUM)
1116 ctx->task_cnt = MAX_FRAME_TASK_NUM;
1117
1118 for (i = 0; i < ctx->task_cnt; i++) {
1119 Vepu510H265eFrmCfg *frm_cfg = mpp_calloc(Vepu510H265eFrmCfg, 1);
1120
1121 frm_cfg->regs_set = mpp_calloc(H265eV510RegSet, 1);
1122 frm_cfg->regs_ret = mpp_calloc(H265eV510StatusElem, 1);
1123 frm_cfg->frame_type = INTRA_FRAME;
1124 ctx->frms[i] = frm_cfg;
1125 }
1126
1127 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
1128 ctx->cfg = cfg->cfg;
1129 hal_bufs_init(&ctx->dpb_bufs);
1130
1131 ctx->frame_count = -1;
1132 ctx->frame_cnt_gen_ready = 0;
1133 ctx->enc_mode = 1;
1134 cfg->cap_recn_out = 1;
1135 cfg->type = VPU_CLIENT_RKVENC;
1136 ret = mpp_dev_init(&cfg->dev, cfg->type);
1137 if (ret) {
1138 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
1139 return ret;
1140 }
1141 mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);
1142 ctx->dev = cfg->dev;
1143 ctx->frame_type = INTRA_FRAME;
1144
1145 { /* setup default hardware config */
1146 MppEncHwCfg *hw = &cfg->cfg->hw;
1147 RK_U32 j;
1148
1149 hw->qp_delta_row_i = 2;
1150 hw->qp_delta_row = 2;
1151 hw->qbias_i = 171;
1152 hw->qbias_p = 85;
1153 hw->qbias_en = 0;
1154
1155 for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++)
1156 hw->mode_bias[j] = 8;
1157 }
1158
1159 ctx->poll_slice_max = 8;
1160 ctx->poll_cfg_size = (sizeof(ctx->poll_cfgs) + sizeof(RK_S32) * ctx->poll_slice_max) * 2;
1161 ctx->poll_cfgs = mpp_malloc_size(MppDevPollCfg, ctx->poll_cfg_size);
1162
1163 if (NULL == ctx->poll_cfgs) {
1164 ret = MPP_ERR_MALLOC;
1165 mpp_err_f("init poll cfg buffer failed\n");
1166 goto DONE;
1167 }
1168
1169 ctx->output_cb = cfg->output_cb;
1170 cfg->cap_recn_out = 1;
1171
1172 ctx->tune = vepu510_h265e_tune_init(ctx);
1173
1174 DONE:
1175 if (ret)
1176 hal_h265e_v510_deinit(hal);
1177
1178 hal_h265e_leave();
1179 return ret;
1180 }
1181
hal_h265e_vepu510_prepare(void * hal)1182 static MPP_RET hal_h265e_vepu510_prepare(void *hal)
1183 {
1184 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
1185 MppEncPrepCfg *prep = &ctx->cfg->prep;
1186
1187 hal_h265e_dbg_func("enter %p\n", hal);
1188
1189 if (prep->change_res) {
1190 RK_S32 i;
1191
1192 // pre-alloc required buffers to reduce first frame delay
1193 vepu510_h265_setup_hal_bufs(ctx);
1194 for (i = 0; i < ctx->max_buf_cnt; i++)
1195 hal_bufs_get_buf(ctx->dpb_bufs, i);
1196
1197 prep->change_res = 0;
1198 }
1199
1200 hal_h265e_dbg_func("leave %p\n", hal);
1201
1202 return MPP_OK;
1203 }
1204
1205 static MPP_RET
vepu510_h265_set_patch_info(H265eSyntax_new * syn,VepuFmt input_fmt,MppDevRegOffCfgs * offsets,HalEncTask * task)1206 vepu510_h265_set_patch_info(H265eSyntax_new *syn, VepuFmt input_fmt, MppDevRegOffCfgs *offsets, HalEncTask *task)
1207 {
1208 RK_U32 hor_stride = syn->pp.hor_stride;
1209 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
1210 RK_U32 frame_size = hor_stride * ver_stride;
1211 RK_U32 u_offset = 0, v_offset = 0;
1212 MPP_RET ret = MPP_OK;
1213
1214 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
1215 mpp_err("VEPU_510 unsupports FBC format input.\n");
1216
1217 ret = MPP_NOK;
1218 } else {
1219 switch (input_fmt) {
1220 case VEPU5xx_FMT_YUV420P: {
1221 u_offset = frame_size;
1222 v_offset = frame_size * 5 / 4;
1223 } break;
1224 case VEPU5xx_FMT_YUV420SP:
1225 case VEPU5xx_FMT_YUV422SP: {
1226 u_offset = frame_size;
1227 v_offset = frame_size;
1228 } break;
1229 case VEPU5xx_FMT_YUV422P: {
1230 u_offset = frame_size;
1231 v_offset = frame_size * 3 / 2;
1232 } break;
1233 case VEPU5xx_FMT_YUV400:
1234 case VEPU5xx_FMT_YUYV422:
1235 case VEPU5xx_FMT_UYVY422: {
1236 u_offset = 0;
1237 v_offset = 0;
1238 } break;
1239 case VEPU5xx_FMT_BGR565:
1240 case VEPU5xx_FMT_BGR888:
1241 case VEPU5xx_FMT_BGRA8888: {
1242 u_offset = 0;
1243 v_offset = 0;
1244 } break;
1245 case VEPU5xx_FMT_YUV444SP : {
1246 u_offset = hor_stride * ver_stride;
1247 v_offset = hor_stride * ver_stride;
1248 } break;
1249 case VEPU5xx_FMT_YUV444P : {
1250 u_offset = hor_stride * ver_stride;
1251 v_offset = hor_stride * ver_stride * 2;
1252 } break;
1253 default: {
1254 hal_h265e_err("unknown color space: %d\n", input_fmt);
1255 u_offset = frame_size;
1256 v_offset = frame_size * 5 / 4;
1257 }
1258 }
1259 }
1260 mpp_dev_multi_offset_update(offsets, 161, u_offset);
1261 mpp_dev_multi_offset_update(offsets, 162, v_offset);
1262
1263 return ret;
1264 }
1265
1266
1267 #if 0
1268 static MPP_RET vepu510_h265_set_roi_regs(H265eV510HalContext *ctx, H265eVepu510Frame *regs)
1269 {
1270 /* memset register on start so do not clear registers again here */
1271 if (ctx->roi_data) {
1272 /* roi setup */
1273 MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data;
1274
1275 regs->reg0192_enc_pic.roi_en = 1;
1276 regs->reg0178_roi_addr = mpp_dev_get_iova_address(ctx->dev, cfg->base_cfg_buf, 0);
1277 if (cfg->roi_qp_en) {
1278 regs->reg0179_roi_qp_addr = mpp_dev_get_iova_address(ctx->dev, cfg->qp_cfg_buf, 0);
1279 regs->reg0228_roi_en.roi_qp_en = 1;
1280 }
1281
1282 if (cfg->roi_amv_en) {
1283 regs->reg0180_roi_amv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->amv_cfg_buf, 0);
1284 regs->reg0228_roi_en.roi_amv_en = 1;
1285 }
1286
1287 if (cfg->roi_mv_en) {
1288 regs->reg0181_roi_mv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->mv_cfg_buf, 0);
1289 regs->reg0228_roi_en.roi_mv_en = 1;
1290 }
1291 }
1292
1293 return MPP_OK;
1294 }
1295 #endif
1296
vepu510_h265_set_rc_regs(H265eV510HalContext * ctx,H265eV510RegSet * regs,HalEncTask * task)1297 static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSet *regs, HalEncTask *task)
1298 {
1299 H265eSyntax_new *syn = ctx->syn;
1300 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
1301 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1302 Vepu510RcRoi *reg_rc = ®s->reg_rc_roi;
1303 MppEncCfgSet *cfg = ctx->cfg;
1304 MppEncRcCfg *rc = &cfg->rc;
1305 MppEncHwCfg *hw = &cfg->hw;
1306 MppEncH265Cfg *h265 = &cfg->h265;
1307 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32;
1308 RK_S32 mb_h32 = (syn->pp.pic_height + 31) / 32;
1309
1310 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd32 * mb_h32);
1311 RK_U32 ctu_target_bits;
1312 RK_S32 negative_bits_thd, positive_bits_thd;
1313
1314 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
1315 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target;
1316 reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target;
1317 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_target;
1318 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_target;
1319 } else {
1320 if (ctu_target_bits_mul_16 >= 0x100000) {
1321 ctu_target_bits_mul_16 = 0x50000;
1322 }
1323 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd32) >> 4;
1324 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
1325 positive_bits_thd = 5 * ctu_target_bits / 16;
1326
1327 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target;
1328 reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target;
1329 reg_frm->common.rc_cfg.rc_en = 1;
1330 reg_frm->common.rc_cfg.aq_en = 1;
1331 reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32;
1332
1333 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_max;
1334 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_min;
1335 reg_frm->common.rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
1336
1337 if (ctx->smart_en || ctx->sp_enc_en) {
1338 reg_frm->common.rc_qp.rc_qp_range = 0;
1339 } else {
1340 reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
1341 hw->qp_delta_row_i : hw->qp_delta_row;
1342 }
1343
1344 {
1345 /* fixed frame qp */
1346 RK_S32 fqp_min, fqp_max;
1347
1348 if (ctx->frame_type == INTRA_FRAME) {
1349 fqp_min = rc->fqp_min_i;
1350 fqp_max = rc->fqp_max_i;
1351 } else {
1352 fqp_min = rc->fqp_min_p;
1353 fqp_max = rc->fqp_max_p;
1354 }
1355
1356 if ((fqp_min == fqp_max) && (fqp_min >= 0) && (fqp_max <= 51)) {
1357 reg_frm->common.enc_pic.pic_qp = fqp_min;
1358 reg_frm->synt_sli1.sli_qp = fqp_min;
1359 reg_frm->common.rc_qp.rc_qp_range = 0;
1360 }
1361 }
1362
1363 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
1364 reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
1365 reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
1366 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
1367 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
1368 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
1369 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
1370 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
1371 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
1372
1373 reg_rc->rc_adj0.qp_adj0 = -2;
1374 reg_rc->rc_adj0.qp_adj1 = -1;
1375 reg_rc->rc_adj0.qp_adj2 = 0;
1376 reg_rc->rc_adj0.qp_adj3 = 1;
1377 reg_rc->rc_adj0.qp_adj4 = 2;
1378 reg_rc->rc_adj1.qp_adj5 = 0;
1379 reg_rc->rc_adj1.qp_adj6 = 0;
1380 reg_rc->rc_adj1.qp_adj7 = 0;
1381 reg_rc->rc_adj1.qp_adj8 = 0;
1382 }
1383
1384 reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
1385 reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
1386 reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
1387 reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
1388 reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
1389 reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
1390 reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
1391 reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
1392 reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
1393 reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
1394 reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
1395 reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
1396 reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
1397 reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
1398 reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
1399 reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
1400 reg_rc->roi_qthd3.qpmap_mode = h265->qpmap_mode;
1401
1402 return MPP_OK;
1403 }
1404
vepu510_h265_set_pp_regs(H265eV510RegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg)1405 static MPP_RET vepu510_h265_set_pp_regs(H265eV510RegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *prep_cfg)
1406 {
1407 Vepu510ControlCfg *reg_ctl = ®s->reg_ctl;
1408 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1409 RK_S32 stridey = 0;
1410 RK_S32 stridec = 0;
1411
1412 reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
1413 reg_frm->common.src_fmt.src_cfmt = fmt->format;
1414 reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap;
1415 reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap;
1416
1417 reg_frm->common.src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 : 1;
1418
1419 reg_frm->common.src_proc.src_mirr = prep_cfg->mirroring > 0;
1420 reg_frm->common.src_proc.src_rot = prep_cfg->rotation;
1421 reg_frm->common.src_proc.tile4x4_en = 0;
1422
1423 if (prep_cfg->hor_stride) {
1424 if (MPP_FRAME_FMT_IS_TILE(prep_cfg->format)) {
1425 reg_frm->common.src_proc.tile4x4_en = 1;
1426
1427 switch (prep_cfg->format & MPP_FRAME_FMT_MASK) {
1428 case MPP_FMT_YUV400:
1429 stridey = prep_cfg->hor_stride * 4;
1430 break;
1431 case MPP_FMT_YUV420P:
1432 case MPP_FMT_YUV420SP:
1433 stridey = prep_cfg->hor_stride * 4 * 3 / 2;
1434 break;
1435 case MPP_FMT_YUV422P:
1436 case MPP_FMT_YUV422SP:
1437 stridey = prep_cfg->hor_stride * 4 * 2;
1438 break;
1439 case MPP_FMT_YUV444P:
1440 case MPP_FMT_YUV444SP:
1441 stridey = prep_cfg->hor_stride * 4 * 3;
1442 break;
1443 default:
1444 mpp_err("Unsupported input format 0x%08x, with TILE mask.\n", fmt);
1445 return MPP_ERR_VALUE;
1446 break;
1447 }
1448 } else {
1449 stridey = prep_cfg->hor_stride;
1450 }
1451 } else {
1452 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888)
1453 stridey = prep_cfg->width * 4;
1454 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR888)
1455 stridey = prep_cfg->width * 3;
1456 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 ||
1457 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 ||
1458 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422)
1459 stridey = prep_cfg->width * 2;
1460 }
1461
1462 stridec = (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP ||
1463 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP ||
1464 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV444P) ?
1465 stridey : stridey / 2;
1466
1467 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUV444SP)
1468 stridec = stridey * 2;
1469
1470 if (reg_frm->common.src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {
1471 const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
1472
1473 hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
1474
1475 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
1476 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
1477 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
1478
1479 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
1480 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
1481 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
1482
1483 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
1484 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
1485 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
1486
1487 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;
1488 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;
1489 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;
1490
1491 hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
1492 }
1493
1494 reg_frm->common.src_strd0.src_strd0 = stridey;
1495 reg_frm->common.src_strd1.src_strd1 = stridec;
1496
1497 return MPP_OK;
1498 }
1499
vepu510_h265_set_slice_regs(H265eSyntax_new * syn,H265eVepu510Frame * regs)1500 static void vepu510_h265_set_slice_regs(H265eSyntax_new *syn, H265eVepu510Frame *regs)
1501 {
1502 regs->synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag;
1503 regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
1504 regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
1505 regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
1506 regs->synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag;
1507 regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
1508 regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
1509
1510 regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
1511 regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
1512 regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
1513 regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
1514 regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
1515 regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
1516 regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
1517 regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
1518 regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
1519 regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
1520 regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
1521 regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
1522 regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
1523 regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
1524 regs->synt_pps.csip_flag = syn->pp.constrained_intra_pred_flag;
1525
1526 regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
1527 regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
1528 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1529 regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
1530 regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
1531
1532 regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
1533
1534 regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
1535 regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
1536 regs->synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en;
1537 regs->common.enc_pic.num_pic_tot_cur_hevc = syn->sp.tot_poc_num;
1538
1539 regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
1540 regs->synt_sli0.sli_type = syn->sp.slice_type;
1541 regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
1542 regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
1543 regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
1544 regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
1545
1546 regs->synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
1547 regs->synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
1548 regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
1549 regs->synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
1550 regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
1551 regs->synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst;
1552 regs->synt_sli1.max_mrg_cnd = 3;//syn->sp.max_mrg_cnd;
1553
1554 regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
1555 regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
1556 regs->synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb;
1557 regs->synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
1558 }
1559
vepu510_h265_set_ref_regs(H265eSyntax_new * syn,H265eVepu510Frame * regs)1560 static void vepu510_h265_set_ref_regs(H265eSyntax_new *syn, H265eVepu510Frame *regs)
1561 {
1562 regs->synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
1563 regs->synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
1564 regs->synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
1565
1566 regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1567 regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1568 regs->synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
1569 regs->synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
1570 regs->synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
1571 regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1572 regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1573 regs->synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
1574 regs->synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
1575 regs->synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
1576
1577 regs->synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
1578 regs->synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
1579 regs->synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
1580 regs->synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
1581 regs->synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
1582
1583 regs->synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
1584 regs->synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
1585 regs->synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
1586 regs->synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
1587 regs->synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
1588 regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
1589 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1590 }
1591
vepu510_h265_set_me_regs(H265eV510HalContext * ctx,H265eSyntax_new * syn,H265eVepu510Frame * regs)1592 static void vepu510_h265_set_me_regs(H265eV510HalContext *ctx, H265eSyntax_new *syn, H265eVepu510Frame *regs)
1593 {
1594 regs->common.me_rnge.cime_srch_dwnh = 15;
1595 regs->common.me_rnge.cime_srch_uph = 15;
1596 regs->common.me_rnge.cime_srch_rgtw = 12;
1597 regs->common.me_rnge.cime_srch_lftw = 12;
1598 regs->common.me_cfg.rme_srch_h = 3;
1599 regs->common.me_cfg.rme_srch_v = 3;
1600
1601 regs->common.me_cfg.srgn_max_num = 54;
1602 regs->common.me_cfg.cime_dist_thre = 1024;
1603 regs->common.me_cfg.rme_dis = 0;
1604 regs->common.me_cfg.fme_dis = 0;
1605 regs->common.me_rnge.dlt_frm_num = 0x1;
1606
1607 if (syn->pp.sps_temporal_mvp_enabled_flag &&
1608 (ctx->frame_type != INTRA_FRAME)) {
1609 if (ctx->last_frame_type == INTRA_FRAME) {
1610 regs->common.me_cach.colmv_load_hevc = 0;
1611 } else {
1612 regs->common.me_cach.colmv_load_hevc = 1;
1613 }
1614 regs->common.me_cach.colmv_stor_hevc = 1;
1615 }
1616
1617 regs->common.me_cach.cime_zero_thre = (ctx->cfg->tune.scene_mode ==
1618 MPP_ENC_SCENE_MODE_IPC) ? 1024 : 64;
1619 regs->common.me_cach.fme_prefsu_en = 0;
1620 }
1621
vepu510_h265_set_hw_address(H265eV510HalContext * ctx,H265eVepu510Frame * regs,HalEncTask * task)1622 void vepu510_h265_set_hw_address(H265eV510HalContext *ctx, H265eVepu510Frame *regs, HalEncTask *task)
1623 {
1624 HalEncTask *enc_task = task;
1625 HalBuf *recon_buf, *ref_buf;
1626 MppBuffer md_info_buf = enc_task->md_info;
1627 Vepu510H265eFrmCfg *frm = ctx->frm;
1628 H265eSyntax_new *syn = ctx->syn;
1629
1630 hal_h265e_enter();
1631
1632 regs->common.adr_src0 = mpp_buffer_get_fd(enc_task->input);
1633 regs->common.adr_src1 = regs->common.adr_src0;
1634 regs->common.adr_src2 = regs->common.adr_src0;
1635
1636 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_curr_idx);
1637 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_refr_idx);
1638
1639 if (!syn->sp.non_reference_flag) {
1640 regs->common.rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
1641 regs->common.rfpw_b_addr = regs->common.rfpw_h_addr;
1642 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
1643 }
1644 regs->common.rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
1645 regs->common.rfpr_b_addr = regs->common.rfpr_h_addr;
1646 regs->common.colmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
1647 regs->common.colmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
1648 regs->common.dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
1649 regs->common.dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
1650
1651 mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
1652
1653 if (md_info_buf) {
1654 regs->common.enc_pic.mei_stor = 1;
1655 regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf);
1656 } else {
1657 regs->common.enc_pic.mei_stor = 0;
1658 regs->common.meiw_addr = 0;
1659 }
1660
1661 regs->common.bsbt_addr = mpp_buffer_get_fd(enc_task->output);
1662 /* TODO: stream size relative with syntax */
1663 regs->common.bsbb_addr = regs->common.bsbt_addr;
1664 regs->common.bsbr_addr = regs->common.bsbt_addr;
1665 regs->common.adr_bsbs = regs->common.bsbt_addr;
1666
1667 regs->common.rfpt_h_addr = 0xffffffff;
1668 regs->common.rfpb_h_addr = 0;
1669 regs->common.rfpt_b_addr = 0xffffffff;
1670 regs->common.adr_rfpb_b = 0;
1671
1672 mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet));
1673 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
1674
1675 regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1676 regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1677
1678 /* smear bufs */
1679 regs->common.adr_smear_rd = mpp_buffer_get_fd(ref_buf->buf[3]);
1680 regs->common.adr_smear_wr = mpp_buffer_get_fd(recon_buf->buf[3]);
1681 }
1682
vepu510_h265e_save_pass1_patch(H265eV510RegSet * regs,H265eV510HalContext * ctx,RK_S32 tiles_enabled_flag)1683 static MPP_RET vepu510_h265e_save_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx,
1684 RK_S32 tiles_enabled_flag)
1685 {
1686 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1687 RK_S32 width = ctx->cfg->prep.width;
1688 RK_S32 height = ctx->cfg->prep.height;
1689 RK_S32 width_align = MPP_ALIGN(width, 16);
1690 RK_S32 height_align = MPP_ALIGN(height, 16);
1691
1692 if (NULL == ctx->buf_pass1) {
1693 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
1694 if (!ctx->buf_pass1) {
1695 mpp_err("buf_pass1 malloc fail, debreath invaild");
1696 return MPP_NOK;
1697 }
1698 }
1699
1700 reg_frm->common.enc_pic.cur_frm_ref = 1;
1701 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
1702 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
1703 reg_frm->common.enc_pic.rec_fbc_dis = 1;
1704
1705 if (tiles_enabled_flag)
1706 reg_frm->synt_pps.lpf_fltr_acrs_til = 0;
1707
1708 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, 0);
1709
1710 /* NOTE: disable split to avoid lowdelay slice output */
1711 reg_frm->common.sli_splt.sli_splt = 0;
1712 reg_frm->common.enc_pic.slen_fifo = 0;
1713
1714 return MPP_OK;
1715 }
1716
vepu510_h265e_use_pass1_patch(H265eV510RegSet * regs,H265eV510HalContext * ctx)1717 static MPP_RET vepu510_h265e_use_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx)
1718 {
1719 Vepu510ControlCfg *reg_ctl = ®s->reg_ctl;
1720 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1721 RK_U32 hor_stride = MPP_ALIGN(ctx->cfg->prep.width, 16);
1722 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1723 MPP_RET ret = MPP_OK;
1724
1725 hal_h265e_dbg_func("enter\n");
1726
1727 reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
1728 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP;
1729 reg_frm->common.src_fmt.alpha_swap = 0;
1730 reg_frm->common.src_fmt.rbuv_swap = 0;
1731 reg_frm->common.src_fmt.out_fmt = 1;
1732 reg_frm->common.src_fmt.src_rcne = 1;
1733
1734 reg_frm->common.src_strd0.src_strd0 = hor_stride;
1735 reg_frm->common.src_strd1.src_strd1 = 3 * hor_stride;
1736
1737 reg_frm->common.src_proc.src_mirr = 0;
1738 reg_frm->common.src_proc.src_rot = 0;
1739
1740 reg_frm->common.adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
1741 reg_frm->common.adr_src1 = reg_frm->common.adr_src0;
1742 reg_frm->common.adr_src2 = 0;
1743
1744 /* input cb addr */
1745 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, 2 * hor_stride);
1746 if (ret)
1747 mpp_err_f("set input cb addr offset failed %d\n", ret);
1748
1749 return MPP_OK;
1750 }
1751
setup_vepu510_ext_line_buf(H265eV510HalContext * ctx,H265eV510RegSet * regs)1752 static void setup_vepu510_ext_line_buf(H265eV510HalContext *ctx, H265eV510RegSet *regs)
1753 {
1754 MppDevRcbInfoCfg rcb_cfg;
1755 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1756 RK_S32 offset = 0;
1757 RK_S32 fd;
1758
1759 if (ctx->ext_line_buf) {
1760 fd = mpp_buffer_get_fd(ctx->ext_line_buf);
1761 offset = ctx->ext_line_buf_size;
1762
1763 reg_frm->common.ebufb_addr = fd;
1764 reg_frm->common.ebuft_addr = fd;
1765 mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size);
1766 } else {
1767 reg_frm->common.ebufb_addr = 0;
1768 reg_frm->common.ebuft_addr = 0;
1769 }
1770
1771 /* rcb info for sram */
1772 rcb_cfg.reg_idx = 179;
1773 rcb_cfg.size = offset;
1774
1775 mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
1776
1777 rcb_cfg.reg_idx = 178;
1778 rcb_cfg.size = 0;
1779
1780 mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
1781 }
1782
setup_vepu510_dual_core(H265eV510HalContext * ctx)1783 static MPP_RET setup_vepu510_dual_core(H265eV510HalContext *ctx)
1784 {
1785 Vepu510H265eFrmCfg *frm = ctx->frm;
1786 H265eV510RegSet *regs = frm->regs_set;
1787 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1788 RK_U32 dchs_ofst = 9;
1789 RK_U32 dchs_dly = 0;
1790 RK_U32 dchs_rxe = 1;
1791
1792 if (ctx->task_cnt == 1)
1793 return MPP_OK;
1794
1795 if (ctx->frame_type == INTRA_FRAME) {
1796 ctx->curr_idx = 0;
1797 ctx->prev_idx = 0;
1798 dchs_rxe = 0;
1799 }
1800
1801 reg_frm->common.dual_core.dchs_txid = ctx->curr_idx;
1802 reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx;
1803 reg_frm->common.dual_core.dchs_txe = 1;
1804 reg_frm->common.dual_core.dchs_rxe = dchs_rxe;
1805 reg_frm->common.dual_core.dchs_ofst = dchs_ofst;
1806 reg_frm->common.dual_core.dchs_dly = dchs_dly;
1807
1808 ctx->prev_idx = ctx->curr_idx++;
1809 if (ctx->curr_idx > 3)
1810 ctx->curr_idx = 0;
1811
1812 return MPP_OK;
1813 }
1814
setup_vepu510_split(H265eV510RegSet * regs,MppEncCfgSet * enc_cfg,RK_U32 title_en)1815 static void setup_vepu510_split(H265eV510RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
1816 {
1817 MppEncSliceSplit *cfg = &enc_cfg->split;
1818
1819 hal_h265e_dbg_func("enter\n");
1820
1821 switch (cfg->split_mode) {
1822 case MPP_ENC_SPLIT_NONE : {
1823 regs->reg_frm.common.sli_splt.sli_splt = 0;
1824 regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
1825 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
1826 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 0;
1827 regs->reg_frm.common.sli_splt.sli_flsh = 0;
1828 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
1829
1830 regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
1831 regs->reg_frm.common.enc_pic.slen_fifo = 0;
1832 } break;
1833 case MPP_ENC_SPLIT_BY_BYTE : {
1834 regs->reg_frm.common.sli_splt.sli_splt = 1;
1835 regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
1836 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
1837 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
1838 regs->reg_frm.common.sli_splt.sli_flsh = 1;
1839 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
1840
1841 regs->reg_frm.common.sli_byte.sli_splt_byte = cfg->split_arg;
1842 regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
1843 regs->reg_ctl.int_en.vslc_done_en = regs->reg_frm.common.enc_pic.slen_fifo ;
1844 } break;
1845 case MPP_ENC_SPLIT_BY_CTU : {
1846 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 32) / 32;
1847 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 32) / 32;
1848 RK_U32 slice_num = 0;
1849
1850 if (title_en)
1851 mb_w = mb_w / 2;
1852
1853 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
1854
1855 regs->reg_frm.common.sli_splt.sli_splt = 1;
1856 regs->reg_frm.common.sli_splt.sli_splt_mode = 1;
1857 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
1858 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
1859 regs->reg_frm.common.sli_splt.sli_flsh = 1;
1860 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
1861
1862 regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
1863 regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
1864 if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
1865 (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN)))
1866 regs->reg_ctl.int_en.vslc_done_en = 1;
1867
1868 } break;
1869 default : {
1870 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
1871 } break;
1872 }
1873
1874 hal_h265e_dbg_func("leave\n");
1875 }
1876
vepu510_h265_set_scaling_list(H265eV510HalContext * ctx)1877 static void vepu510_h265_set_scaling_list(H265eV510HalContext *ctx)
1878 {
1879 Vepu510H265eFrmCfg *frm_cfg = ctx->frm;
1880 H265eV510RegSet *regs = frm_cfg->regs_set;
1881 Vepu510SclCfg *s = ®s->reg_scl;
1882 RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
1883 RK_U32 scl_lst_sel = regs->reg_frm.rdo_cfg.scl_lst_sel;
1884 RK_U8 idx;
1885
1886 hal_h265e_dbg_func("enter\n");
1887
1888 if (scl_lst_sel == 1) {
1889 for (idx = 0; idx < 64; idx++) {
1890 /* TU8 intra Y/U/V */
1891 p[idx + 64 * 0] = vepu510_h265_cqm_intra8[63 - idx];
1892 p[idx + 64 * 1] = vepu510_h265_cqm_intra8[63 - idx];
1893 p[idx + 64 * 2] = vepu510_h265_cqm_intra8[63 - idx];
1894
1895 /* TU8 inter Y/U/V */
1896 p[idx + 64 * 3] = vepu510_h265_cqm_inter8[63 - idx];
1897 p[idx + 64 * 4] = vepu510_h265_cqm_inter8[63 - idx];
1898 p[idx + 64 * 5] = vepu510_h265_cqm_inter8[63 - idx];
1899
1900 /* TU16 intra Y/U/V AC */
1901 p[idx + 64 * 6] = vepu510_h265_cqm_intra8[63 - idx];
1902 p[idx + 64 * 7] = vepu510_h265_cqm_intra8[63 - idx];
1903 p[idx + 64 * 8] = vepu510_h265_cqm_intra8[63 - idx];
1904
1905 /* TU16 inter Y/U/V AC */
1906 p[idx + 64 * 9] = vepu510_h265_cqm_inter8[63 - idx];
1907 p[idx + 64 * 10] = vepu510_h265_cqm_inter8[63 - idx];
1908 p[idx + 64 * 11] = vepu510_h265_cqm_inter8[63 - idx];
1909
1910 /* TU32 intra/inter Y AC */
1911 p[idx + 64 * 12] = vepu510_h265_cqm_intra8[63 - idx];
1912 p[idx + 64 * 13] = vepu510_h265_cqm_inter8[63 - idx];
1913 }
1914
1915 s->tu_dc0.tu16_intra_y_dc = 16;
1916 s->tu_dc0.tu16_intra_u_dc = 16;
1917 s->tu_dc0.tu16_intra_v_dc = 16;
1918 s->tu_dc0.tu16_inter_y_dc = 16;
1919 s->tu_dc1.tu16_inter_u_dc = 16;
1920 s->tu_dc1.tu16_inter_v_dc = 16;
1921 s->tu_dc1.tu32_intra_y_dc = 16;
1922 s->tu_dc1.tu32_inter_y_dc = 16;
1923 } else if (scl_lst_sel == 2) {
1924 //TODO: Update scaling list for (scaling_list_mode == 2)
1925 mpp_log_f("scaling_list_mode 2 is not supported yet\n");
1926 }
1927
1928 hal_h265e_dbg_func("leave\n");
1929 }
1930
hal_h265e_v510_gen_regs(void * hal,HalEncTask * task)1931 MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task)
1932 {
1933 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
1934 HalEncTask *enc_task = task;
1935 EncRcTask *rc_task = enc_task->rc_task;
1936 EncFrmStatus *frm = &rc_task->frm;
1937 H265eSyntax_new *syn = ctx->syn;
1938 Vepu510H265eFrmCfg *frm_cfg = ctx->frm;
1939 H265eV510RegSet *regs = frm_cfg->regs_set;
1940 RK_U32 pic_width_align8, pic_height_align8;
1941 RK_S32 pic_wd32, pic_h32;
1942 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1943 Vepu510ControlCfg *reg_ctl = ®s->reg_ctl;
1944 H265eVepu510Frame *reg_frm = ®s->reg_frm;
1945 Vepu510RcRoi *reg_klut = ®s->reg_rc_roi;
1946 MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
1947 MPP_RET ret = MPP_OK;
1948
1949 hal_h265e_enter();
1950 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
1951 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
1952 pic_wd32 = (syn->pp.pic_width + 31) / 32;
1953 pic_h32 = (syn->pp.pic_height + 31) / 32;
1954
1955 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
1956 ctx->frame_count, ctx->frame_type);
1957 vepu510_h265e_tune_aq_prepare(ctx->tune);
1958 memset(regs, 0, sizeof(H265eV510RegSet));
1959
1960 reg_ctl->enc_strt.lkt_num = 0;
1961 reg_ctl->enc_strt.vepu_cmd = ctx->enc_mode;
1962 reg_ctl->enc_clr.safe_clr = 0x0;
1963 reg_ctl->enc_clr.force_clr = 0x0;
1964
1965 reg_ctl->int_en.enc_done_en = 1;
1966 reg_ctl->int_en.lkt_node_done_en = 1;
1967 reg_ctl->int_en.sclr_done_en = 1;
1968 reg_ctl->int_en.vslc_done_en = 0;
1969 reg_ctl->int_en.vbsf_oflw_en = 1;
1970 reg_ctl->int_en.vbuf_lens_en = 1;
1971 reg_ctl->int_en.enc_err_en = 1;
1972 reg_ctl->int_en.vsrc_err_en = 1;
1973 reg_ctl->int_en.wdg_en = 1;
1974 reg_ctl->int_en.lkt_err_int_en = 0;
1975 reg_ctl->int_en.lkt_err_stop_en = 1;
1976 reg_ctl->int_en.lkt_force_stop_en = 1;
1977 reg_ctl->int_en.jslc_done_en = 1;
1978 reg_ctl->int_en.jbsf_oflw_en = 1;
1979 reg_ctl->int_en.jbuf_lens_en = 1;
1980 reg_ctl->int_en.dvbm_err_en = 0;
1981
1982 reg_ctl->dtrns_map.jpeg_bus_edin = 0x0;
1983 reg_ctl->dtrns_map.src_bus_edin = 0x0;
1984 reg_ctl->dtrns_map.meiw_bus_edin = 0x0;
1985 reg_ctl->dtrns_map.bsw_bus_edin = 0x7;
1986 reg_ctl->dtrns_map.lktw_bus_edin = 0x0;
1987 reg_ctl->dtrns_map.rec_nfbc_bus_edin = 0x0;
1988
1989 reg_ctl->dtrns_cfg.axi_brsp_cke = 0x0;
1990 reg_ctl->enc_wdg.vs_load_thd = 0;
1991
1992 reg_ctl->opt_strg.cke = 1;
1993 reg_ctl->opt_strg.resetn_hw_en = 1;
1994 reg_ctl->opt_strg.rfpr_err_e = 1;
1995
1996 reg_frm->common.enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
1997 reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
1998 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
1999 reg_frm->common.enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
2000 reg_frm->common.src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
2001 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
2002
2003 reg_frm->common.enc_pic.enc_stnd = 1; //H265
2004 reg_frm->common.enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
2005 reg_frm->common.enc_pic.bs_scp = 1;
2006 reg_frm->common.enc_pic.log2_ctu_num_hevc = mpp_ceil_log2(pic_wd32 * pic_h32);
2007
2008 reg_frm->common.src_proc.src_mirr = 0;
2009 reg_frm->common.src_proc.src_rot = 0;
2010 reg_frm->common.src_proc.tile4x4_en = 0;
2011
2012 reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 :
2013 (sm == MPP_ENC_SCENE_MODE_IPC ? 9 : 6);
2014
2015 reg_frm->sao_cfg.sao_lambda_multi = 5;
2016
2017 setup_vepu510_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag);
2018
2019 if (ctx->task_cnt > 1)
2020 setup_vepu510_dual_core(ctx);
2021
2022 vepu510_h265_set_me_regs(ctx, syn, reg_frm);
2023
2024 reg_frm->rdo_cfg.chrm_spcl = 0;
2025 reg_frm->rdo_cfg.cu_inter_e = 0xdb;
2026 reg_frm->rdo_cfg.lambda_qp_use_avg_cu16_flag = (sm == MPP_ENC_SCENE_MODE_IPC);
2027 reg_frm->rdo_cfg.yuvskip_calc_en = 1;
2028 reg_frm->rdo_cfg.atf_e = (sm == MPP_ENC_SCENE_MODE_IPC);
2029 reg_frm->rdo_cfg.atr_e = 1;
2030
2031 if (syn->pp.num_long_term_ref_pics_sps) {
2032 reg_frm->rdo_cfg.ltm_col = 0;
2033 reg_frm->rdo_cfg.ltm_idx0l0 = 1;
2034 } else {
2035 reg_frm->rdo_cfg.ltm_col = 0;
2036 reg_frm->rdo_cfg.ltm_idx0l0 = 0;
2037 }
2038
2039 reg_frm->rdo_cfg.ccwa_e = 1;
2040 reg_frm->rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
2041 reg_frm->synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type);
2042
2043 vepu510_h265_set_scaling_list(ctx);
2044 vepu510_h265_set_hw_address(ctx, reg_frm, task);
2045 vepu510_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep);
2046 vepu510_h265_set_rc_regs(ctx, regs, task);
2047 vepu510_h265_set_slice_regs(syn, reg_frm);
2048 vepu510_h265_set_ref_regs(syn, reg_frm);
2049 ret = vepu510_h265_set_patch_info(syn, (VepuFmt)fmt->format, ctx->reg_cfg, enc_task);
2050 if (ret)
2051 return ret;
2052
2053 setup_vepu510_ext_line_buf(ctx, regs);
2054
2055 /* ROI configure */
2056 if (ctx->roi_data)
2057 vepu510_set_roi(®s->reg_rc_roi.roi_cfg, ctx->roi_data,
2058 ctx->cfg->prep.width, ctx->cfg->prep.height);
2059 /*paramet cfg*/
2060 vepu510_h265_global_cfg_set(ctx, regs);
2061 vepu510_h265e_tune_reg_patch(ctx->tune, task);
2062
2063 /* two pass register patch */
2064 if (frm->save_pass1)
2065 vepu510_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag);
2066
2067 if (frm->use_pass1)
2068 vepu510_h265e_use_pass1_patch(regs, ctx);
2069
2070
2071 ctx->frame_num++;
2072
2073 hal_h265e_leave();
2074 return MPP_OK;
2075 }
2076
hal_h265e_v510_start(void * hal,HalEncTask * enc_task)2077 MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task)
2078 {
2079 MPP_RET ret = MPP_OK;
2080 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
2081 Vepu510H265eFrmCfg *frm = ctx->frm;
2082 RK_U32 *regs = (RK_U32*)frm->regs_set;
2083 H265eV510RegSet *hw_regs = frm->regs_set;
2084 H265eV510StatusElem *reg_out = (H265eV510StatusElem *)frm->regs_ret;
2085 MppDevRegWrCfg cfg;
2086 MppDevRegRdCfg cfg1;
2087 RK_U32 i = 0;
2088
2089 hal_h265e_enter();
2090 if (enc_task->flags.err) {
2091 hal_h265e_err("enc_task->flags.err %08x, return e arly",
2092 enc_task->flags.err);
2093 return MPP_NOK;
2094 }
2095
2096 cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
2097 cfg.size = sizeof(Vepu510ControlCfg);
2098 cfg.offset = VEPU510_CTL_OFFSET;
2099
2100 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2101 if (ret) {
2102 mpp_err_f("set register write failed %d\n", ret);
2103 return ret;
2104 }
2105
2106 if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
2107 regs = (RK_U32*)&hw_regs->reg_ctl;
2108 for (i = 0; i < sizeof(Vepu510ControlCfg) / 4; i++) {
2109 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
2110 }
2111 }
2112
2113 cfg.reg = &hw_regs->reg_frm;
2114 cfg.size = sizeof(H265eVepu510Frame);
2115 cfg.offset = VEPU510_FRAME_OFFSET;
2116
2117 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2118 if (ret) {
2119 mpp_err_f("set register write failed %d\n", ret);
2120 return ret;
2121 }
2122
2123 if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
2124 regs = (RK_U32*)(&hw_regs->reg_frm);
2125 for (i = 0; i < 32; i++) {
2126 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]);
2127 }
2128 regs += 32;
2129 for (i = 0; i < (sizeof(H265eVepu510Frame) - 128) / 4; i++) {
2130 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2131 }
2132 }
2133 cfg.reg = &hw_regs->reg_rc_roi;
2134 cfg.size = sizeof(Vepu510RcRoi);
2135 cfg.offset = VEPU510_RC_ROI_OFFSET;
2136
2137 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2138 if (ret) {
2139 mpp_err_f("set register write failed %d\n", ret);
2140 return ret;
2141 }
2142
2143 if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
2144 regs = (RK_U32*)&hw_regs->reg_rc_roi;
2145 for (i = 0; i < sizeof(Vepu510RcRoi) / 4; i++) {
2146 hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2147 }
2148 }
2149
2150 cfg.reg = &hw_regs->reg_param;
2151 cfg.size = sizeof(H265eVepu510Param);
2152 cfg.offset = VEPU510_PARAM_OFFSET;
2153
2154 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2155 if (ret) {
2156 mpp_err_f("set register write failed %d\n", ret);
2157 return ret;
2158 }
2159
2160 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2161 regs = (RK_U32*)&hw_regs->reg_param;
2162 for (i = 0; i < sizeof(H265eVepu510Param) / 4; i++) {
2163 hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2164 }
2165 }
2166
2167 cfg.reg = &hw_regs->reg_sqi;
2168 cfg.size = sizeof(H265eVepu510Sqi);
2169 cfg.offset = VEPU510_SQI_OFFSET;
2170
2171 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2172 if (ret) {
2173 mpp_err_f("set register write failed %d\n", ret);
2174 return ret;
2175 }
2176
2177 cfg.reg = &hw_regs->reg_scl;
2178 cfg.size = sizeof(hw_regs->reg_scl);
2179 cfg.offset = VEPU510_SCL_OFFSET ;
2180
2181 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2182 if (ret) {
2183 mpp_err_f("set register write failed %d\n", ret);
2184 return ret;
2185 }
2186
2187 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);
2188 if (ret) {
2189 mpp_err_f("set register offsets failed %d\n", ret);
2190 return ret;
2191 }
2192
2193 cfg1.reg = ®_out->hw_status;
2194 cfg1.size = sizeof(RK_U32);
2195 cfg1.offset = VEPU510_REG_BASE_HW_STATUS;
2196
2197 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
2198 if (ret) {
2199 mpp_err_f("set register read failed %d\n", ret);
2200 return ret;
2201 }
2202
2203 cfg1.reg = ®_out->st;
2204 cfg1.size = sizeof(H265eV510StatusElem) - 4;
2205 cfg1.offset = VEPU510_STATUS_OFFSET;
2206
2207 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
2208 if (ret) {
2209 mpp_err_f("set register read failed %d\n", ret);
2210 return ret;
2211 }
2212
2213 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2214 if (ret) {
2215 mpp_err_f("send cmd failed %d\n", ret);
2216 }
2217 hal_h265e_leave();
2218 return ret;
2219 }
2220
vepu510_h265_set_feedback(H265eV510HalContext * ctx,HalEncTask * enc_task)2221 static MPP_RET vepu510_h265_set_feedback(H265eV510HalContext *ctx, HalEncTask *enc_task)
2222 {
2223 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
2224 Vepu510H265eFrmCfg *frm = ctx->frms[enc_task->flags.reg_idx];
2225 Vepu510H265Fbk *fb = &frm->feedback;
2226 MppEncCfgSet *cfg = ctx->cfg;
2227 RK_S32 mb8_num = MPP_ALIGN(cfg->prep.width, 8) * MPP_ALIGN(cfg->prep.height, 8) / 64;
2228 RK_S32 mb4_num = (mb8_num << 2);
2229 H265eV510StatusElem *elem = (H265eV510StatusElem *)frm->regs_ret;
2230 RK_U32 hw_status = elem->hw_status;
2231
2232 hal_h265e_enter();
2233
2234 fb->qp_sum += elem->st.qp_sum;
2235 fb->out_strm_size += elem->st.bs_lgth_l32;
2236 fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
2237 (elem->st.st_sse_bsl.sse_l16 & 0xffff);
2238
2239 fb->hw_status = hw_status;
2240 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
2241 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
2242 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
2243
2244 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
2245 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
2246
2247 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
2248 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
2249
2250 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
2251 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
2252
2253 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
2254 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
2255
2256 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
2257 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
2258
2259 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
2260 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
2261
2262 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
2263 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
2264
2265 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
2266 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
2267
2268 fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
2269
2270 fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
2271 fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
2272 fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
2273 fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
2274 fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
2275 fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8;
2276 fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8;
2277 fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4;
2278 ctx->feedback.acc_cover16_num = elem->st.st_skin_sum1.acc_cover16_num;
2279 ctx->feedback.acc_bndry16_num = elem->st.st_skin_sum2.acc_bndry16_num;
2280 ctx->feedback.acc_zero_mv = elem->st.acc_zero_mv;
2281 ctx->feedback.st_ctu_num = elem->st.st_bnum_b16.num_b16;
2282 memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32));
2283
2284 if (mb4_num > 0)
2285 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
2286 (fb->st_lvl16_intra_num << 4) +
2287 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
2288
2289 if (mb8_num > 0) {
2290 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
2291 }
2292
2293 hal_h265e_leave();
2294 return MPP_OK;
2295 }
2296
hal_h265e_vepu510_status_check(H265eV510RegSet * regs)2297 static MPP_RET hal_h265e_vepu510_status_check(H265eV510RegSet *regs)
2298 {
2299 MPP_RET ret = MPP_OK;
2300
2301 if (regs->reg_ctl.int_sta.lkt_node_done_sta)
2302 hal_h265e_dbg_detail("lkt_done finish");
2303
2304 if (regs->reg_ctl.int_sta.enc_done_sta)
2305 hal_h265e_dbg_detail("enc_done finish");
2306
2307 if (regs->reg_ctl.int_sta.vslc_done_sta)
2308 hal_h265e_dbg_detail("enc_slice finsh");
2309
2310 if (regs->reg_ctl.int_sta.sclr_done_sta)
2311 hal_h265e_dbg_detail("safe clear finsh");
2312
2313 if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
2314 mpp_err_f("bit stream overflow");
2315 ret = MPP_NOK;
2316 }
2317
2318 if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
2319 mpp_err_f("bus write full");
2320 ret = MPP_NOK;
2321 }
2322
2323 if (regs->reg_ctl.int_sta.enc_err_sta) {
2324 mpp_err_f("bus error");
2325 ret = MPP_NOK;
2326 }
2327
2328 if (regs->reg_ctl.int_sta.wdg_sta) {
2329 mpp_err_f("wdg timeout");
2330 ret = MPP_NOK;
2331 }
2332
2333 return ret;
2334 }
2335
2336 //#define DUMP_DATA
hal_h265e_v510_wait(void * hal,HalEncTask * task)2337 MPP_RET hal_h265e_v510_wait(void *hal, HalEncTask *task)
2338 {
2339 MPP_RET ret = MPP_OK;
2340 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
2341 HalEncTask *enc_task = task;
2342 MppPacket pkt = enc_task->packet;
2343 RK_U32 split_out = ctx->cfg->split.split_out;
2344 RK_S32 task_idx = task->flags.reg_idx;
2345 Vepu510H265eFrmCfg *frm = ctx->frms[task_idx];
2346 H265eV510RegSet *regs = frm->regs_set;
2347 RK_U32 offset = mpp_packet_get_length(pkt);
2348 RK_U32 seg_offset = offset;
2349 H265eVepu510Frame *reg_frm = ®s->reg_frm;
2350 RK_U32 type = reg_frm->synt_nal.nal_unit_type;
2351 H265eV510StatusElem *elem = (H265eV510StatusElem *)frm->regs_ret;
2352
2353 hal_h265e_enter();
2354
2355 if (enc_task->flags.err) {
2356 hal_h265e_err("enc_task->flags.err %08x, return early",
2357 enc_task->flags.err);
2358 return MPP_NOK;
2359 }
2360
2361 /* if pass1 mode, it will disable split mode and the split out need to be disable */
2362 if (enc_task->rc_task->frm.save_pass1)
2363 split_out = 0;
2364
2365 if (split_out) {
2366 EncOutParam param;
2367 RK_U32 slice_len = 0;
2368 RK_U32 slice_last = 0;
2369 MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs);
2370 param.task = task;
2371 param.base = mpp_packet_get_data(task->packet);
2372
2373 do {
2374 RK_S32 i = 0;
2375 poll_cfg->poll_type = 0;
2376 poll_cfg->poll_ret = 0;
2377 poll_cfg->count_max = ctx->poll_slice_max;
2378 poll_cfg->count_ret = 0;
2379
2380 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
2381 for (i = 0; i < poll_cfg->count_ret; i++) {
2382 slice_last = poll_cfg->slice_info[i].last;
2383 slice_len = poll_cfg->slice_info[i].length;
2384 param.length = slice_len;
2385
2386 mpp_packet_add_segment_info(pkt, type, seg_offset, slice_len);
2387 seg_offset += slice_len;
2388
2389 if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
2390 param.length = slice_len;
2391 if (slice_last)
2392 ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
2393 else
2394 ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
2395
2396 mpp_callback(ctx->output_cb, ¶m);
2397 }
2398 }
2399 } while (!slice_last);
2400
2401 ret = hal_h265e_vepu510_status_check(regs);
2402 if (!ret)
2403 task->hw_length += elem->st.bs_lgth_l32;
2404
2405 } else {
2406 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
2407 if (ret) {
2408 mpp_err_f("poll cmd failed %d\n", ret);
2409 ret = MPP_ERR_VPUHW;
2410 } else {
2411 ret = hal_h265e_vepu510_status_check(regs);
2412 if (!ret)
2413 task->hw_length += elem->st.bs_lgth_l32;
2414 }
2415 mpp_packet_add_segment_info(pkt, type, offset, elem->st.bs_lgth_l32);
2416 }
2417
2418 #ifdef DUMP_DATA
2419 static FILE *fp_fbd = NULL;
2420 static FILE *fp_fbh = NULL;
2421 static FILE *fp_dws = NULL;
2422 HalBuf *recon_buf;
2423 static RK_U32 frm_num = 0;
2424 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
2425 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
2426 char file_name[20] = "";
2427 size_t rec_size = mpp_buffer_get_size(recon_buf->buf[0]);
2428 size_t dws_size = mpp_buffer_get_size(recon_buf->buf[1]);
2429
2430 void *ptr = mpp_buffer_get_ptr(recon_buf->buf[0]);
2431 void *dws_ptr = mpp_buffer_get_ptr(recon_buf->buf[1]);
2432
2433 sprintf(&file_name[0], "fbd%d.bin", frm_num);
2434 if (fp_fbd != NULL) {
2435 fclose(fp_fbd);
2436 fp_fbd = NULL;
2437 } else {
2438 fp_fbd = fopen(file_name, "wb+");
2439 }
2440 if (fp_fbd) {
2441 fwrite(ptr + ctx->fbc_header_len, 1, rec_size - ctx->fbc_header_len, fp_fbd);
2442 fflush(fp_fbd);
2443 }
2444
2445 sprintf(&file_name[0], "fbh%d.bin", frm_num);
2446
2447 if (fp_fbh != NULL) {
2448 fclose(fp_fbh);
2449 fp_fbh = NULL;
2450 } else {
2451 fp_fbh = fopen(file_name, "wb+");
2452 }
2453
2454 if (fp_fbh) {
2455 fwrite(ptr , 1, ctx->fbc_header_len, fp_fbh);
2456 fflush(fp_fbh);
2457 }
2458
2459 sprintf(&file_name[0], "dws%d.bin", frm_num);
2460
2461 if (fp_dws != NULL) {
2462 fclose(fp_dws);
2463 fp_dws = NULL;
2464 } else {
2465 fp_dws = fopen(file_name, "wb+");
2466 }
2467
2468 if (fp_dws) {
2469 fwrite(dws_ptr , 1, dws_size, fp_dws);
2470 fflush(fp_dws);
2471 }
2472 frm_num++;
2473 #endif
2474 if (ret)
2475 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
2476
2477 hal_h265e_leave();
2478 return ret;
2479 }
2480
hal_h265e_v510_get_task(void * hal,HalEncTask * task)2481 MPP_RET hal_h265e_v510_get_task(void *hal, HalEncTask *task)
2482 {
2483 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
2484 Vepu510H265eFrmCfg *frm_cfg = NULL;
2485 MppFrame frame = task->frame;
2486 EncFrmStatus *frm_status = &task->rc_task->frm;
2487 RK_S32 task_idx = ctx->task_idx;
2488
2489 hal_h265e_enter();
2490
2491 ctx->syn = (H265eSyntax_new *)task->syntax.data;
2492 ctx->dpb = (H265eDpb*)ctx->syn->dpb;
2493 ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
2494 ctx->qpmap_en = ctx->cfg->tune.deblur_en;
2495 ctx->sp_enc_en = ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SE;
2496
2497 if (vepu510_h265_setup_hal_bufs(ctx)) {
2498 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
2499 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
2500 return MPP_ERR_MALLOC;
2501 }
2502
2503 ctx->last_frame_type = ctx->frame_type;
2504 frm_cfg = ctx->frms[task_idx];
2505 ctx->frm = frm_cfg;
2506
2507 if (frm_status->is_intra) {
2508 ctx->frame_type = INTRA_FRAME;
2509 } else {
2510 ctx->frame_type = INTER_P_FRAME;
2511 }
2512
2513 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
2514 MppMeta meta = mpp_frame_get_meta(frame);
2515
2516 mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
2517 }
2518
2519 task->part_first = 1;
2520 task->part_last = 0;
2521 task->flags.reg_idx = ctx->task_idx;
2522 ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
2523 frm_cfg->frame_count = ctx->frame_count++;
2524
2525 ctx->task_idx++;
2526 if (ctx->task_idx >= ctx->task_cnt)
2527 ctx->task_idx = 0;
2528
2529 frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;
2530 frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;
2531
2532 h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
2533 h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
2534
2535 memset(&frm_cfg->feedback, 0, sizeof(Vepu510H265Fbk));
2536
2537 hal_h265e_leave();
2538 return MPP_OK;
2539 }
2540
hal_h265e_v510_ret_task(void * hal,HalEncTask * task)2541 MPP_RET hal_h265e_v510_ret_task(void *hal, HalEncTask *task)
2542 {
2543 H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
2544 HalEncTask *enc_task = task;
2545 RK_S32 task_idx = task->flags.reg_idx;
2546 Vepu510H265eFrmCfg *frm = ctx->frms[task_idx];
2547 Vepu510H265Fbk *fb = &frm->feedback;
2548 EncRcTaskInfo *rc_info = &task->rc_task->info;
2549 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
2550
2551 hal_h265e_enter();
2552
2553 vepu510_h265_set_feedback(ctx, enc_task);
2554 mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
2555 hal_h265e_amend_temporal_id(task, fb->out_strm_size);
2556
2557 rc_info->sse = fb->sse_sum;
2558 rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
2559 rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
2560 rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
2561 rc_info->lvl8_inter_num = fb->st_lvl8_inter_num;
2562 rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
2563 rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
2564 rc_info->lvl8_intra_num = fb->st_lvl8_intra_num;
2565 rc_info->lvl4_intra_num = fb->st_lvl4_intra_num;
2566
2567 enc_task->hw_length = fb->out_strm_size;
2568 enc_task->length += fb->out_strm_size;
2569
2570 h265e_dpb_hal_end(ctx->dpb, frm->hal_curr_idx);
2571 h265e_dpb_hal_end(ctx->dpb, frm->hal_refr_idx);
2572
2573 vepu510_h265e_tune_stat_update(ctx->tune, enc_task);
2574
2575 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
2576 hal_h265e_leave();
2577 return MPP_OK;
2578 }
2579
2580 const MppEncHalApi hal_h265e_vepu510 = {
2581 "hal_h265e_v510",
2582 MPP_VIDEO_CodingHEVC,
2583 sizeof(H265eV510HalContext),
2584 0,
2585 hal_h265e_v510_init,
2586 hal_h265e_v510_deinit,
2587 hal_h265e_vepu510_prepare,
2588 hal_h265e_v510_get_task,
2589 hal_h265e_v510_gen_regs,
2590 hal_h265e_v510_start,
2591 hal_h265e_v510_wait,
2592 NULL,
2593 NULL,
2594 hal_h265e_v510_ret_task,
2595 };
2596