Lines Matching refs:common
715 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu510_prep()
716 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu510_prep()
717 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu510_prep()
718 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu510_prep()
722 reg_frm->common.src_fmt.src_cfmt = hw_fmt; in setup_vepu510_prep()
723 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu510_prep()
724 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu510_prep()
725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu510_prep()
789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu510_prep()
790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu510_prep()
791 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu510_prep()
793 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu510_prep()
794 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu510_prep()
795 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu510_prep()
797 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu510_prep()
798 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu510_prep()
799 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu510_prep()
801 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu510_prep()
802 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu510_prep()
803 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; in setup_vepu510_prep()
807 reg_frm->common.src_udfy.csc_wgt_b2y = cfg.weight[0]; in setup_vepu510_prep()
808 reg_frm->common.src_udfy.csc_wgt_g2y = cfg.weight[1]; in setup_vepu510_prep()
809 reg_frm->common.src_udfy.csc_wgt_r2y = cfg.weight[2]; in setup_vepu510_prep()
811 reg_frm->common.src_udfu.csc_wgt_b2u = cfg.weight[3]; in setup_vepu510_prep()
812 reg_frm->common.src_udfu.csc_wgt_g2u = cfg.weight[4]; in setup_vepu510_prep()
813 reg_frm->common.src_udfu.csc_wgt_r2u = cfg.weight[5]; in setup_vepu510_prep()
815 reg_frm->common.src_udfv.csc_wgt_b2v = cfg.weight[6]; in setup_vepu510_prep()
816 reg_frm->common.src_udfv.csc_wgt_g2v = cfg.weight[7]; in setup_vepu510_prep()
817 reg_frm->common.src_udfv.csc_wgt_r2v = cfg.weight[8]; in setup_vepu510_prep()
819 reg_frm->common.src_udfo.csc_ofst_y = cfg.offset[0]; in setup_vepu510_prep()
820 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu510_prep()
821 reg_frm->common.src_udfo.csc_ofst_v = cfg.offset[2]; in setup_vepu510_prep()
824 reg_frm->common.src_strd0.src_strd0 = y_stride; in setup_vepu510_prep()
825 reg_frm->common.src_strd1.src_strd1 = c_stride; in setup_vepu510_prep()
827 reg_frm->common.src_proc.src_mirr = prep->mirroring > 0; in setup_vepu510_prep()
828 reg_frm->common.src_proc.src_rot = prep->rotation; in setup_vepu510_prep()
831 reg_frm->common.src_proc.tile4x4_en = 1; in setup_vepu510_prep()
833 reg_frm->common.src_proc.tile4x4_en = 0; in setup_vepu510_prep()
838 reg_frm->common.pic_ofst.pic_ofst_y = 0; in setup_vepu510_prep()
839 reg_frm->common.pic_ofst.pic_ofst_x = 0; in setup_vepu510_prep()
860 reg_frm->common.enc_pic.cur_frm_ref = 1; in vepu510_h264e_save_pass1_patch()
861 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); in vepu510_h264e_save_pass1_patch()
862 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; in vepu510_h264e_save_pass1_patch()
863 reg_frm->common.enc_pic.rec_fbc_dis = 1; in vepu510_h264e_save_pass1_patch()
868 reg_frm->common.sli_splt.sli_splt = 0; in vepu510_h264e_save_pass1_patch()
869 reg_frm->common.enc_pic.slen_fifo = 0; in vepu510_h264e_save_pass1_patch()
884 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP; in vepu510_h264e_use_pass1_patch()
885 reg_frm->common.src_fmt.alpha_swap = 0; in vepu510_h264e_use_pass1_patch()
886 reg_frm->common.src_fmt.rbuv_swap = 0; in vepu510_h264e_use_pass1_patch()
887 reg_frm->common.src_fmt.out_fmt = 1; in vepu510_h264e_use_pass1_patch()
888 reg_frm->common.src_fmt.src_rcne = 1; in vepu510_h264e_use_pass1_patch()
892 reg_frm->common.src_strd0.src_strd0 = y_stride; in vepu510_h264e_use_pass1_patch()
893 reg_frm->common.src_strd1.src_strd1 = 3 * c_stride; in vepu510_h264e_use_pass1_patch()
895 reg_frm->common.src_proc.src_mirr = 0; in vepu510_h264e_use_pass1_patch()
896 reg_frm->common.src_proc.src_rot = 0; in vepu510_h264e_use_pass1_patch()
898 reg_frm->common.pic_ofst.pic_ofst_y = 0; in vepu510_h264e_use_pass1_patch()
899 reg_frm->common.pic_ofst.pic_ofst_x = 0; in vepu510_h264e_use_pass1_patch()
902 reg_frm->common.adr_src0 = fd_in; in vepu510_h264e_use_pass1_patch()
903 reg_frm->common.adr_src1 = fd_in; in vepu510_h264e_use_pass1_patch()
904 reg_frm->common.adr_src2 = fd_in; in vepu510_h264e_use_pass1_patch()
919 reg_frm->common.enc_pic.enc_stnd = 0; in setup_vepu510_codec()
920 reg_frm->common.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; in setup_vepu510_codec()
921 reg_frm->common.enc_pic.bs_scp = 1; in setup_vepu510_codec()
1204 reg_frm->common.enc_pic.pic_qp = rc_info->quality_target; in setup_vepu510_rc_base()
1205 reg_frm->common.rc_qp.rc_max_qp = rc_info->quality_target; in setup_vepu510_rc_base()
1206 reg_frm->common.rc_qp.rc_min_qp = rc_info->quality_target; in setup_vepu510_rc_base()
1218 reg_frm->common.enc_pic.pic_qp = qp_target; in setup_vepu510_rc_base()
1220 reg_frm->common.rc_cfg.rc_en = 1; in setup_vepu510_rc_base()
1221 reg_frm->common.rc_cfg.aq_en = 1; in setup_vepu510_rc_base()
1222 reg_frm->common.rc_cfg.rc_ctu_num = mb_w; in setup_vepu510_rc_base()
1224 reg_frm->common.rc_qp.rc_max_qp = qp_max; in setup_vepu510_rc_base()
1225 reg_frm->common.rc_qp.rc_min_qp = qp_min; in setup_vepu510_rc_base()
1226 reg_frm->common.rc_tgt.ctu_ebit = mb_target_bits_mul_16; in setup_vepu510_rc_base()
1229 reg_frm->common.rc_qp.rc_qp_range = 0; in setup_vepu510_rc_base()
1231 reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? in setup_vepu510_rc_base()
1248 reg_frm->common.enc_pic.pic_qp = fqp_min; in setup_vepu510_rc_base()
1249 reg_frm->common.rc_qp.rc_qp_range = 0; in setup_vepu510_rc_base()
1295 reg_frm->common.adr_src0 = fd_in; in setup_vepu510_io_buf()
1296 reg_frm->common.adr_src1 = fd_in; in setup_vepu510_io_buf()
1297 reg_frm->common.adr_src2 = fd_in; in setup_vepu510_io_buf()
1299 reg_frm->common.bsbt_addr = fd_out; in setup_vepu510_io_buf()
1300 reg_frm->common.bsbb_addr = fd_out; in setup_vepu510_io_buf()
1301 reg_frm->common.adr_bsbs = fd_out; in setup_vepu510_io_buf()
1302 reg_frm->common.bsbr_addr = fd_out; in setup_vepu510_io_buf()
1304 reg_frm->common.rfpt_h_addr = 0xffffffff; in setup_vepu510_io_buf()
1305 reg_frm->common.rfpb_h_addr = 0; in setup_vepu510_io_buf()
1306 reg_frm->common.rfpt_b_addr = 0xffffffff; in setup_vepu510_io_buf()
1307 reg_frm->common.adr_rfpb_b = 0; in setup_vepu510_io_buf()
1467 reg_frm->common.me_rnge.cime_srch_uph = 1; in setup_vepu510_intra_refresh()
1478 reg_frm->common.me_rnge.cime_srch_dwnh = 1; in setup_vepu510_intra_refresh()
1517 reg_frm->common.rfpw_h_addr = fd; in setup_vepu510_recn_refr()
1518 reg_frm->common.rfpw_b_addr = fd; in setup_vepu510_recn_refr()
1519 reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu510_recn_refr()
1520 reg_frm->common.adr_smear_wr = mpp_buffer_get_fd(buf_smear); in setup_vepu510_recn_refr()
1532 reg_frm->common.rfpr_h_addr = fd; in setup_vepu510_recn_refr()
1533 reg_frm->common.rfpr_b_addr = fd; in setup_vepu510_recn_refr()
1534 reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb); in setup_vepu510_recn_refr()
1535 reg_frm->common.adr_smear_rd = mpp_buffer_get_fd(buf_smear); in setup_vepu510_recn_refr()
1552 reg_frm->common.sli_splt.sli_splt = 0; in setup_vepu510_split()
1553 reg_frm->common.sli_splt.sli_splt_mode = 0; in setup_vepu510_split()
1554 reg_frm->common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1555 reg_frm->common.sli_splt.sli_max_num_m1 = 0; in setup_vepu510_split()
1556 reg_frm->common.sli_splt.sli_flsh = 0; in setup_vepu510_split()
1557 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu510_split()
1559 reg_frm->common.sli_byte.sli_splt_byte = 0; in setup_vepu510_split()
1560 reg_frm->common.enc_pic.slen_fifo = 0; in setup_vepu510_split()
1563 reg_frm->common.sli_splt.sli_splt = 1; in setup_vepu510_split()
1564 reg_frm->common.sli_splt.sli_splt_mode = 0; in setup_vepu510_split()
1565 reg_frm->common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1566 reg_frm->common.sli_splt.sli_max_num_m1 = 500; in setup_vepu510_split()
1567 reg_frm->common.sli_splt.sli_flsh = 1; in setup_vepu510_split()
1568 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0; in setup_vepu510_split()
1570 reg_frm->common.sli_byte.sli_splt_byte = cfg->split_arg; in setup_vepu510_split()
1571 reg_frm->common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu510_split()
1572 regs->reg_ctl.int_en.vslc_done_en = reg_frm->common.enc_pic.slen_fifo; in setup_vepu510_split()
1579 reg_frm->common.sli_splt.sli_splt = 1; in setup_vepu510_split()
1580 reg_frm->common.sli_splt.sli_splt_mode = 1; in setup_vepu510_split()
1581 reg_frm->common.sli_splt.sli_splt_cpst = 0; in setup_vepu510_split()
1582 reg_frm->common.sli_splt.sli_max_num_m1 = 500; in setup_vepu510_split()
1583 reg_frm->common.sli_splt.sli_flsh = 1; in setup_vepu510_split()
1584 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; in setup_vepu510_split()
1586 reg_frm->common.sli_byte.sli_splt_byte = 0; in setup_vepu510_split()
1587 reg_frm->common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0; in setup_vepu510_split()
1589 (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN))) in setup_vepu510_split()
1609 reg_frm->common.me_rnge.cime_srch_dwnh = 15; in setup_vepu510_me()
1610 reg_frm->common.me_rnge.cime_srch_uph = 15; in setup_vepu510_me()
1611 reg_frm->common.me_rnge.cime_srch_rgtw = 12; in setup_vepu510_me()
1612 reg_frm->common.me_rnge.cime_srch_lftw = 12; in setup_vepu510_me()
1613 reg_frm->common.me_cfg.rme_srch_h = 3; in setup_vepu510_me()
1614 reg_frm->common.me_cfg.rme_srch_v = 3; in setup_vepu510_me()
1616 reg_frm->common.me_cfg.srgn_max_num = 54; in setup_vepu510_me()
1617 reg_frm->common.me_cfg.cime_dist_thre = 1024; in setup_vepu510_me()
1618 reg_frm->common.me_cfg.rme_dis = 0; in setup_vepu510_me()
1619 reg_frm->common.me_cfg.fme_dis = 0; in setup_vepu510_me()
1620 reg_frm->common.me_rnge.dlt_frm_num = 0x0; in setup_vepu510_me()
1621 reg_frm->common.me_cach.cime_zero_thre = 64; in setup_vepu510_me()
1754 reg_frm->common.ebufb_addr = 0; in setup_vepu510_ext_line_buf()
1755 reg_frm->common.ebufb_addr = 0; in setup_vepu510_ext_line_buf()
1762 reg_frm->common.ebuft_addr = fd; in setup_vepu510_ext_line_buf()
1763 reg_frm->common.ebufb_addr = fd; in setup_vepu510_ext_line_buf()
1795 reg_frm->common.dual_core.dchs_txid = ctx->curr_idx; in setup_vepu510_dual_core()
1796 reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx; in setup_vepu510_dual_core()
1797 reg_frm->common.dual_core.dchs_txe = 1; in setup_vepu510_dual_core()
1798 reg_frm->common.dual_core.dchs_rxe = dchs_rxe; in setup_vepu510_dual_core()
1799 reg_frm->common.dual_core.dchs_ofst = dchs_ofst; in setup_vepu510_dual_core()
1800 reg_frm->common.dual_core.dchs_dly = dchs_dly; in setup_vepu510_dual_core()
2196 reg_frm->common.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; in hal_h264e_vepu510_gen_regs()
2197 reg_frm->common.enc_pic.mei_stor = task->md_info ? 1 : 0; in hal_h264e_vepu510_gen_regs()
2199 reg_frm->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); in hal_h264e_vepu510_gen_regs()
2200 reg_frm->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); in hal_h264e_vepu510_gen_regs()