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Searched refs:rk_clrsetreg (Results 1 – 25 of 59) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3308.c70 rk_clrsetreg(&priv->pmu->sft_con_lo, DDR_IO_RET_CFG_MASK, in enable_ddr_io_ret()
73 rk_clrsetreg(&priv->grf->upctl_con0, GRF_DDR_16BIT_EN_MASK, in enable_ddr_io_ret()
81 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, in pll_set()
83 rk_clrsetreg(&priv->cru->pll[pll_type].con1, in pll_set()
87 rk_clrsetreg(&priv->cru->pll[pll_type].con0, in pll_set()
91 rk_clrsetreg(&priv->cru->pll[pll_type].con1, in pll_set()
98 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, in pll_set()
116 rk_clrsetreg(&priv->cru->mode, VPLL1_WORK_MODE_MASK, in rkdclk_init()
118 rk_clrsetreg(&priv->cru->mode, VPLL0_WORK_MODE_MASK, in rkdclk_init()
120 rk_clrsetreg(&priv->cru->mode, DPLL_WORK_MODE_MASK, in rkdclk_init()
[all …]
H A Dsdram_rv1108.c33 rk_clrsetreg(&priv->pmu_grf->soc_con[0], in enable_ddr_io_ret()
41 rk_clrsetreg(&priv->cru->pll[1].con3, WORK_MODE_MASK, in rkdclk_init()
43 rk_clrsetreg(&priv->cru->pll[1].con3, GLOBAL_POWER_DOWN_MASK, in rkdclk_init()
45 rk_clrsetreg(&priv->cru->pll[1].con3, DSMPD_MASK, in rkdclk_init()
47 rk_clrsetreg(&priv->cru->pll[1].con0, FBDIV_MASK, in rkdclk_init()
49 rk_clrsetreg(&priv->cru->pll[1].con1, in rkdclk_init()
54 rk_clrsetreg(&priv->cru->pll[1].con3, GLOBAL_POWER_DOWN_MASK, in rkdclk_init()
59 rk_clrsetreg(&priv->cru->clksel_con[4], CLK_DDR_PLL_SEL_MASK | in rkdclk_init()
62 rk_clrsetreg(&priv->cru->pll[1].con3, WORK_MODE_MASK, in rkdclk_init()
68 rk_clrsetreg(&priv->cru->softrst_con[2], DDRUPCTL_PSRSTN_REQ_MASK | in phy_pctrl_reset_cru()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3568/
H A Drk3568.c538 rk_clrsetreg(&pmugrf->pmu_soc_con0, UART0_IO_SEL_MASK, in board_debug_uart_init()
542 rk_clrsetreg(&pmugrf->pmu_gpio0c_iomux_l, in board_debug_uart_init()
553 rk_clrsetreg(&grf->iofunc_sel3, UART1_IO_SEL_MASK, in board_debug_uart_init()
557 rk_clrsetreg(&grf->gpio2b_iomux_l, in board_debug_uart_init()
559 rk_clrsetreg(&grf->gpio2b_iomux_h, in board_debug_uart_init()
563 rk_clrsetreg(&grf->iofunc_sel3, UART1_IO_SEL_MASK, in board_debug_uart_init()
567 rk_clrsetreg(&grf->gpio3d_iomux_h, in board_debug_uart_init()
579 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK, in board_debug_uart_init()
583 rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l, in board_debug_uart_init()
589 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK, in board_debug_uart_init()
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dgmac_rockchip.c222 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); in px30_gmac_fix_mac_speed()
305 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_fix_mac_speed()
337 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); in rk3288_gmac_fix_mac_speed()
380 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); in rk3308_gmac_fix_mac_speed()
427 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], in rk3328_gmac_fix_mac_speed()
465 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); in rk3368_gmac_fix_mac_speed()
493 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); in rk3399_gmac_fix_mac_speed()
528 rk_clrsetreg(&grf->gmac_con0, in rv1108_set_rmii_speed()
564 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_DIV_MASK, div); in rk3506_set_rmii_speed()
566 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_DIV_MASK, div); in rk3506_set_rmii_speed()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1126/
H A Drv1126.c382 rk_clrsetreg(&grf->gpio1c_iomux_l, in board_debug_uart_init()
393 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK, in board_debug_uart_init()
397 rk_clrsetreg(&pmugrf->gpio0b_iomux_h, in board_debug_uart_init()
403 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK, in board_debug_uart_init()
407 rk_clrsetreg(&grf->gpio1d_iomux_l, in board_debug_uart_init()
418 rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK, in board_debug_uart_init()
422 rk_clrsetreg(&grf->gpio1a_iomux_h, in board_debug_uart_init()
428 rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK, in board_debug_uart_init()
432 rk_clrsetreg(&grf->gpio3a_iomux_l, in board_debug_uart_init()
443 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK, in board_debug_uart_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3399/
H A Drk3399.c99 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); in arch_cpu_init()
131 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
134 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
139 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
142 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
147 rk_clrsetreg(&grf->soc_con7, in board_debug_uart_init()
152 rk_clrsetreg(&grf->soc_con7, in board_debug_uart_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c98 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
100 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
102 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
104 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
106 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, in mcu_init()
108 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, in mcu_init()
111 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, in mcu_init()
161 rk_clrsetreg(&grf->gpio2d_iomux, in board_debug_uart_init()
163 rk_clrsetreg(&grf->gpio2d_iomux, in board_debug_uart_init()
181 rk_clrsetreg(&pmugrf->gpio0d_iomux, in board_debug_uart_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3308/
H A Drk3308.c161 rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val); in rk_board_init()
233 rk_clrsetreg(&grf->soc_con0, IOVSEL4_MASK, VCCIO4_3V3 << IOVSEL4_SHIFT); in arch_cpu_init()
297 rk_clrsetreg(&grf->soc_con15, mask, value); in rk_board_init_f()
312 rk_clrsetreg(&cru->clksel_con[16], in board_debug_uart_init()
319 rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, in board_debug_uart_init()
321 rk_clrsetreg(&grf->gpio1ch_iomux, GPIO1C7_MASK | GPIO1C6_MASK, in board_debug_uart_init()
327 rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, in board_debug_uart_init()
330 rk_clrsetreg(&grf->gpio4d_iomux, in board_debug_uart_init()
340 rk_clrsetreg(&cru->clksel_con[22], in board_debug_uart_init()
345 rk_clrsetreg(&grf->gpio4b_iomux, in board_debug_uart_init()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c314 rk_clrsetreg(base + pll->mode_offset, in rk3036_pll_set_rate()
323 rk_clrsetreg(base + pll->con_offset, in rk3036_pll_set_rate()
328 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
333 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
357 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
464 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); in rk3588_pll_set_rate()
466 rk_clrsetreg(base + pll->mode_offset, in rk3588_pll_set_rate()
470 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0), in rk3588_pll_set_rate()
474 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0), in rk3588_pll_set_rate()
478 rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5), in rk3588_pll_set_rate()
[all …]
H A Dclk_rv1108.c85 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
98 rk_clrsetreg(&pll->con2, FRACDIV_MASK, in rkclk_set_pll()
111 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
181 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, in rv1108_sfc_set_clk()
207 rk_clrsetreg(&cru->clksel_con[22], in rv1108_saradc_set_clk()
232 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio1_set_clk()
258 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio0_set_clk()
[all …]
H A Dclk_rk322x.c115 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
119 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
124 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
205 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, in rk322x_mac_set_clk()
239 rk_clrsetreg(&cru->cru_clksel_con[11], in rk322x_mmc_set_clk()
242 rk_clrsetreg(&cru->cru_clksel_con[12], in rk322x_mmc_set_clk()
249 rk_clrsetreg(&cru->cru_clksel_con[11], in rk322x_mmc_set_clk()
256 rk_clrsetreg(&cru->cru_clksel_con[11], in rk322x_mmc_set_clk()
259 rk_clrsetreg(&cru->cru_clksel_con[12], in rk322x_mmc_set_clk()
[all …]
H A Dclk_rk3036.c85 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
110 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
130 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
135 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
153 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
158 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
178 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
188 rk_clrsetreg(&cru->cru_clksel_con[16], in rkclk_init()
194 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
[all …]
H A Dclk_rk3066.c125 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
128 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
131 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
171 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
181 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
220 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rkclk_configure_cpu()
230 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
235 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
240 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rkclk_configure_cpu()
318 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
[all …]
H A Dclk_rk3188.c123 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
126 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
129 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
169 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
179 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
228 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
233 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
238 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
320 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
[all …]
H A Dclk_rk3399.c384 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
388 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, in rkclk_set_pll()
391 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, in rkclk_set_pll()
393 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
405 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
548 rk_clrsetreg(&cru->clksel_con[con_base], in rk3399_configure_cpu()
555 rk_clrsetreg(&cru->clksel_con[con_base + 1], in rk3399_configure_cpu()
631 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), in rk3399_i2c_set_clk()
635 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), in rk3399_i2c_set_clk()
639 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), in rk3399_i2c_set_clk()
[all …]
H A Dclk_rk3576.c232 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
236 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
252 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
263 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
350 rk_clrsetreg(&cru->clksel_con[9], in rk3576_top_set_clk()
365 rk_clrsetreg(&cru->clksel_con[10], in rk3576_top_set_clk()
379 rk_clrsetreg(&cru->clksel_con[8], in rk3576_top_set_clk()
392 rk_clrsetreg(&cru->clksel_con[19], in rk3576_top_set_clk()
484 rk_clrsetreg(&cru->pmuclksel_con[6], CLK_I2C0_SEL_MASK, in rk3576_i2c_set_clk()
488 rk_clrsetreg(&cru->clksel_con[57], CLK_I2C1_SEL_MASK, in rk3576_i2c_set_clk()
[all …]
H A Dclk_rk3328.c141 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
145 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
150 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
154 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
208 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
215 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
222 rk_clrsetreg(&cru->clksel_con[35], in rk3328_i2c_set_clk()
229 rk_clrsetreg(&cru->clksel_con[35], in rk3328_i2c_set_clk()
271 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK, in rk3328_gmac2io_set_clk()
295 rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK, in rk3328_gmac2phy_src_set_clk()
[all …]
H A Dclk_rk3288.c250 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, in rkclk_set_pll()
252 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
256 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, div->nb - 1); in rkclk_set_pll()
258 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
332 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
463 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
495 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
507 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
519 rk_clrsetreg(&cru->cru_clksel_con[27], in rockchip_vop_set_clk()
[all …]
H A Dclk_rv1126.c200 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rv1126_rtc32k_set_pmuclk()
246 rk_clrsetreg(&pmucru->pmu_clksel_con[2], CLK_I2C0_DIV_MASK, in rv1126_i2c_set_pmuclk()
250 rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C2_DIV_MASK, in rv1126_i2c_set_pmuclk()
297 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
300 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
305 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
308 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
315 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
318 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
323 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
[all …]
H A Dclk_rk3568.c231 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rk3568_rtc32k_set_pmuclk()
273 rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C0_DIV_MASK, in rk3568_i2c_set_pmuclk()
315 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rk3568_pwm_set_pmuclk()
323 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rk3568_pwm_set_pmuclk()
361 rk_clrsetreg(&pmucru->pmu_clksel_con[2], in rk3568_pmu_set_pmuclk()
463 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rk3568_rtc32k_set_parent()
466 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rk3568_rtc32k_set_parent()
502 rk_clrsetreg(&priv->pmucru->pmu_clkgate_con[2], 0x3 << 13, 0 << 13); in rk3568_pmuclk_probe()
565 rk_clrsetreg(&cru->clksel_con[0], in rk3568_armclk_set_clk()
568 rk_clrsetreg(&cru->clksel_con[2], in rk3568_armclk_set_clk()
[all …]
H A Dclk_rk1808.c144 rk_clrsetreg(&cru->pmu_clksel_con[7], in rk1808_i2c_set_clk()
150 rk_clrsetreg(&cru->clksel_con[59], in rk1808_i2c_set_clk()
156 rk_clrsetreg(&cru->clksel_con[59], in rk1808_i2c_set_clk()
162 rk_clrsetreg(&cru->clksel_con[60], in rk1808_i2c_set_clk()
168 rk_clrsetreg(&cru->clksel_con[71], in rk1808_i2c_set_clk()
174 rk_clrsetreg(&cru->clksel_con[71], in rk1808_i2c_set_clk()
252 rk_clrsetreg(&cru->clksel_con[con_id], in rk1808_mmc_set_clk()
257 rk_clrsetreg(&cru->clksel_con[con_id], in rk1808_mmc_set_clk()
262 rk_clrsetreg(&cru->clksel_con[con_id + 1], EMMC_CLK_SEL_MASK, in rk1808_mmc_set_clk()
286 rk_clrsetreg(&cru->clksel_con[26], in rk1808_sfc_set_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3588/
H A Drk3588.c492 rk_clrsetreg(&pmu2_ioc->gpio0c_iomux_sel_h, in board_debug_uart_init()
502 rk_clrsetreg(&pmu1_ioc->gpio0b_iomux_sel_l, in board_debug_uart_init()
511 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_h, in board_debug_uart_init()
514 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_l, in board_debug_uart_init()
526 rk_clrsetreg(&bus_ioc->gpio2b_iomux_sel_h, in board_debug_uart_init()
535 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_h, in board_debug_uart_init()
546 rk_clrsetreg(&pmu2_ioc->gpio0d_iomux_sel_l, in board_debug_uart_init()
552 rk_clrsetreg(&bus_ioc->gpio0d_iomux_sel_l, in board_debug_uart_init()
567 rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h, in board_debug_uart_init()
573 rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h, in board_debug_uart_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk322x/
H A Drk322x.c47 rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK, in arch_cpu_init()
78 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
83 rk_clrsetreg(&grf->con_iomux, in board_debug_uart_init()
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk3399_mipi.c39 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
43 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
63 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
67 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); in rk_mipi_dphy_mode_set()
71 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); in rk_mipi_dphy_mode_set()
H A Drk3288_mipi.c41 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
46 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
67 rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
72 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
78 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()

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