Lines Matching refs:rk_clrsetreg
222 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); in px30_gmac_fix_mac_speed()
305 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_fix_mac_speed()
337 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); in rk3288_gmac_fix_mac_speed()
380 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); in rk3308_gmac_fix_mac_speed()
427 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], in rk3328_gmac_fix_mac_speed()
465 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); in rk3368_gmac_fix_mac_speed()
493 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); in rk3399_gmac_fix_mac_speed()
528 rk_clrsetreg(&grf->gmac_con0, in rv1108_set_rmii_speed()
564 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_DIV_MASK, div); in rk3506_set_rmii_speed()
566 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_DIV_MASK, div); in rk3506_set_rmii_speed()
624 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); in rk3528_set_rgmii_speed()
626 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); in rk3528_set_rgmii_speed()
669 rk_clrsetreg(&grf->soc_con[0], in rk3562_set_gmac_speed()
683 rk_clrsetreg(&grf->soc_con[0], in rk3562_set_gmac_speed()
705 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); in rk3562_set_gmac_speed()
707 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); in rk3562_set_gmac_speed()
757 rk_clrsetreg(&s_grf->gmac1_con, div_mask, div); in rk3576_set_rgmii_speed()
759 rk_clrsetreg(&s_grf->gmac0_con, div_mask, div); in rk3576_set_rgmii_speed()
817 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); in rk3588_set_rgmii_speed()
854 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); in rv1106_set_rmii_speed()
940 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), RV1126B_GMAC_CLK_RMII_DIV_MASK, div); in rv1126b_set_rgmii_speed()
958 rk_clrsetreg(&grf->mac_con1, in px30_gmac_set_to_rmii()
988 rk_clrsetreg(&grf->mac_con1, in rk1808_gmac_set_to_rgmii()
996 rk_clrsetreg(&grf->mac_con0, in rk1808_gmac_set_to_rgmii()
1031 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_set_to_rgmii()
1040 rk_clrsetreg(&grf->mac_con[0], in rk3228_gmac_set_to_rgmii()
1060 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_set_to_rmii()
1074 rk_clrsetreg(&grf->soc_con1, in rk3288_gmac_set_to_rgmii()
1078 rk_clrsetreg(&grf->soc_con3, in rk3288_gmac_set_to_rgmii()
1100 rk_clrsetreg(&grf->mac_con0, in rk3308_gmac_set_to_rmii()
1133 rk_clrsetreg(&grf->mac_con[1], in rk3328_gmac_set_to_rgmii()
1142 rk_clrsetreg(&grf->mac_con[0], in rk3328_gmac_set_to_rgmii()
1161 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], in rk3328_gmac_set_to_rmii()
1191 rk_clrsetreg(&grf->soc_con15, in rk3368_gmac_set_to_rgmii()
1195 rk_clrsetreg(&grf->soc_con16, in rk3368_gmac_set_to_rgmii()
1212 rk_clrsetreg(&grf->soc_con5, in rk3399_gmac_set_to_rgmii()
1216 rk_clrsetreg(&grf->soc_con6, in rk3399_gmac_set_to_rgmii()
1237 rk_clrsetreg(&grf->gmac_con0, in rv1108_gmac_set_to_rmii()
1270 rk_clrsetreg(&grf->con_iomux, in rk3228_gmac_integrated_phy_powerup()
1274 rk_clrsetreg(&grf->macphy_con[2], in rk3228_gmac_integrated_phy_powerup()
1278 rk_clrsetreg(&grf->macphy_con[3], in rk3228_gmac_integrated_phy_powerup()
1283 rk_clrsetreg(&grf->macphy_con[0], in rk3228_gmac_integrated_phy_powerup()
1296 rk_clrsetreg(&grf->macphy_con[0], in rk3228_gmac_integrated_phy_powerup()
1330 rk_clrsetreg(&grf->macphy_con[1], in rk3328_gmac_integrated_phy_powerup()
1334 rk_clrsetreg(&grf->macphy_con[2], in rk3328_gmac_integrated_phy_powerup()
1338 rk_clrsetreg(&grf->macphy_con[3], in rk3328_gmac_integrated_phy_powerup()
1343 rk_clrsetreg(&grf->macphy_con[0], in rk3328_gmac_integrated_phy_powerup()
1356 rk_clrsetreg(&grf->macphy_con[0], in rk3328_gmac_integrated_phy_powerup()
1378 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); in rk3506_set_to_rmii()
1380 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_RMII_MODE_MASK, clk_mode); in rk3506_set_to_rmii()
1439 rk_clrsetreg(&grf->macphy_con0, in rk3528_gmac_integrated_phy_powerup()
1449 rk_clrsetreg(&grf->macphy_con1, in rk3528_gmac_integrated_phy_powerup()
1478 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); in rk3528_set_to_rmii()
1481 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); in rk3528_set_to_rmii()
1526 rk_clrsetreg(&grf->gmac1_con0, in rk3528_set_to_rgmii()
1533 rk_clrsetreg(&grf->gmac1_con1, in rk3528_set_to_rgmii()
1555 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); in rk3562_set_to_rmii()
1594 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, in rk3562_set_to_rgmii()
1605 rk_clrsetreg(&ioc->mac0_io_con1, in rk3562_set_to_rgmii()
1610 rk_clrsetreg(&ioc->mac0_io_con0, in rk3562_set_to_rgmii()
1616 rk_clrsetreg(&ioc->mac1_io_con1, in rk3562_set_to_rgmii()
1621 rk_clrsetreg(&ioc->mac1_io_con0, in rk3562_set_to_rgmii()
1646 rk_clrsetreg(con1, in rk3568_set_to_rmii()
1688 rk_clrsetreg(con0, in rk3568_set_to_rgmii()
1694 rk_clrsetreg(con1, in rk3568_set_to_rgmii()
1719 rk_clrsetreg(&s_grf->gmac1_con, clk_mode_mask, clk_mode); in rk3576_set_to_rmii()
1721 rk_clrsetreg(&s_grf->gmac0_con, clk_mode_mask, clk_mode); in rk3576_set_to_rmii()
1760 rk_clrsetreg(&s_grf->gmac1_con, clk_mode_mask, clk_mode); in rk3576_set_to_rgmii()
1765 rk_clrsetreg(&s_grf->gmac0_con, clk_mode_mask, clk_mode); in rk3576_set_to_rgmii()
1806 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); in rk3588_set_to_rmii()
1807 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); in rk3588_set_to_rmii()
1880 rk_clrsetreg(offset_con, in rk3588_set_to_rgmii()
1886 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, in rk3588_set_to_rgmii()
1889 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); in rk3588_set_to_rgmii()
1890 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); in rk3588_set_to_rgmii()
1902 rk_clrsetreg(&grf->gmac_clk_con, in rv1103b_set_to_rmii()
1973 rk_clrsetreg(&grf->macphy_con0, in rv1106_gmac_integrated_phy_powerup()
1983 rk_clrsetreg(&grf->macphy_con1, in rv1106_gmac_integrated_phy_powerup()
2000 rk_clrsetreg(&grf->gmac_clk_con, in rv1106_set_to_rmii()
2017 rk_clrsetreg(&grf->mac_con0, in rv1126_set_to_rmii()
2064 rk_clrsetreg(&grf->mac_con0, in rv1126_set_to_rgmii()
2076 rk_clrsetreg(&grf->mac_con1, in rv1126_set_to_rgmii()
2082 rk_clrsetreg(&grf->mac_con2, in rv1126_set_to_rgmii()
2150 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), in rv1126b_set_to_rmii()
2154 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), in rv1126b_set_to_rmii()
2194 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), in rv1126b_set_to_rgmii()
2206 rk_clrsetreg(&ioc1->grf_gmacio_m0_con1 + (0x38000 / 4), in rv1126b_set_to_rgmii()
2211 rk_clrsetreg(&ioc0->grf_gmacio_m1_con1 + (0x30000 / 4), in rv1126b_set_to_rgmii()
2216 rk_clrsetreg(&ioc1->grf_gmacio_m0_con0 + (0x38000 / 4), in rv1126b_set_to_rgmii()
2222 rk_clrsetreg(&ioc0->grf_gmacio_m1_con0 + (0x30000 / 4), in rv1126b_set_to_rgmii()
2249 rk_clrsetreg(&grf->soc_con11, RK3506_GMAC_CLK_SELET_MASK, val); in rk3506_set_clock_selection()
2251 rk_clrsetreg(&grf->soc_con8, RK3506_GMAC_CLK_SELET_MASK, val); in rk3506_set_clock_selection()
2272 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); in rk3528_set_clock_selection()
2315 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); in rk3562_set_clock_selection()
2318 rk_clrsetreg(&ioc->mac1_io_con1, in rk3562_set_clock_selection()
2320 rk_clrsetreg(&ioc->mac0_io_con1, in rk3562_set_clock_selection()
2326 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); in rk3562_set_clock_selection()
2329 rk_clrsetreg(&ioc->mac1_io_con1, in rk3562_set_clock_selection()
2352 rk_clrsetreg(&s_grf->gmac1_con, mask, val); in rk3576_set_clock_selection()
2354 rk_clrsetreg(&s_grf->gmac0_con, mask, val); in rk3576_set_clock_selection()
2379 rk_clrsetreg(&php_grf->clk_con1, mask, val); in rk3588_set_clock_selection()
2397 rk_clrsetreg(&grf->gmac_grf_con0 + (0x50000 / 4), RV1126B_GMAC_CLK_SELET_MASK, val); in rv1126b_set_clock_selection()