Home
last modified time | relevance | path

Searched refs:x0 (Results 1 – 25 of 314) sorted by relevance

12345678910>>...13

/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/fdts/
H A Drdn2_nt_fw_config.dts18 platform-id = <0x0>;
19 config-id = <0x0>;
20 multi-chip-mode = <0x0>;
25 isolated-cpu-list = <0x0 0x0
26 0x0 0x0
27 0x0 0x0
28 0x0 0x0
29 0x0 0x0
30 0x0 0x0
31 0x0 0x0
[all …]
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dneoverse_v1.S33 ldr x0, =0x0
34 msr NEOVERSE_V1_CPUPSELR_EL3, x0
35 ldr x0, = 0xEE070F14
36 msr NEOVERSE_V1_CPUPOR_EL3, x0
37 ldr x0, = 0xFFFF0FFF
38 msr NEOVERSE_V1_CPUPMR_EL3, x0
39 ldr x0, =0x4005027FF
40 msr NEOVERSE_V1_CPUPCR_EL3, x0
43 ldr x0, =0x1
44 msr NEOVERSE_V1_CPUPSELR_EL3, x0
[all …]
H A Dcortex_a77.S33 mov x0, x7
35 cbz x0, 1f
37 ldr x0, =0x0
38 msr CORTEX_A77_CPUPSELR_EL3, x0
39 ldr x0, =0x00E8400000
40 msr CORTEX_A77_CPUPOR_EL3, x0
41 ldr x0, =0x00FFE00000
42 msr CORTEX_A77_CPUPMR_EL3, x0
43 ldr x0, =0x4004003FF
44 msr CORTEX_A77_CPUPCR_EL3, x0
[all …]
H A Dcortex_a78.S49 ldr x0, =0x10E3900002
50 msr S3_6_c15_c8_2, x0
51 ldr x0, =0x10FFF00083
52 msr S3_6_c15_c8_3, x0
53 ldr x0, =0x2001003FF
54 msr S3_6_c15_c8_1, x0
56 mov x0, #1
57 msr S3_6_c15_c8_0, x0
58 ldr x0, =0x10E3800082
59 msr S3_6_c15_c8_2, x0
[all …]
H A Dcortex_a710.S53 mov x0, #0
54 msr S3_6_C15_C8_0, x0
55 ldr x0, =0x10E3900002
56 msr S3_6_C15_C8_2, x0
57 ldr x0, =0x10FFF00083
58 msr S3_6_C15_C8_3, x0
59 ldr x0, =0x2001003FF
60 msr S3_6_C15_C8_1, x0
62 mov x0, #1
63 msr S3_6_C15_C8_0, x0
[all...]
H A Dcortex_a715.S42 ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
43 cmp x0, #MTE_IMPLEMENTED_ELX
49 mov x0, #2
50 msr CORTEX_A715_CPUPSELR_EL3, x0
52 ldr x0, =0xd69f0bff
53 msr CORTEX_A715_CPUPOR_EL3, x0
54 ldr x0, =0xfffffbff
55 msr CORTEX_A715_CPUPMR_EL3, x0
84 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
85 cbz x0,
[all...]
H A Dcortex_x2.S53 mov x0, #0
54 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
55 ldr x0, =0x10E3900002
56 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
57 ldr x0, =0x10FFF00083
58 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
59 ldr x0, =0x2001003FF
60 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
62 mov x0, #1
63 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL
[all...]
H A Dcortex_a76ae.S45 ldr x0,=0x3
46 msr CORTEX_A76AE_CPUPSELR_EL3,x0
47 ldr x0,=0x10E3900002
48 msr CORTEX_A76AE_CPUPOR_EL3,x0
49 ldr x0,=0x10FFF00083
50 msr CORTEX_A76AE_CPUPMR_EL3,x0
51 ldr x0,=0x2001003FF
52 msr CORTEX_A76AE_CPUPCR_EL3,x0
54 ldr x0,=0x4
55 msr CORTEX_A76AE_CPUPSELR_EL3,x0
[all …]
H A Dcortex_a78_ae.S35 ldr x0, =0x10E3900002
36 msr S3_6_c15_c8_2, x0
37 ldr x0, =0x10FFF00083
38 msr S3_6_c15_c8_3, x0
39 ldr x0, =0x2001003FF
40 msr S3_6_c15_c8_1, x0
42 mov x0, #1
43 msr S3_6_c15_c8_0, x0
44 ldr x0, =0x10E3800082
45 msr S3_6_c15_c8_2, x0
[all …]
/rk3399_ARM-atf/plat/imx/common/
H A Dimx8_helpers.S32 mrs x0, midr_el1
33 ubfx x0, x0, MIDR_PN_SHIFT, #12
56 mrs x0, mpidr_el1
57 and x0, x0, #(MPIDR_CPU_MASK)
58 cmp x0, #PLAT_PRIMARY_CPU
59 cset x0, eq
70 mrs x0, mpidr_el1
71 and x1, x0, #MPIDR_CPU_MASK
72 and x0, x0, #MPIDR_CLUSTER_MASK
73 add x0, x1, x0, LSR #6
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/common/aarch64/
H A Dtegra_helpers.S64 mrs x0, midr_el1
66 and x0, x0, x1
67 lsr x0, x0, #MIDR_PN_SHIFT
68 cmp x0, #MIDR_PN_CORTEX_A57
75 mrs x0, CORTEX_A57_L2ECTLR_EL1
77 bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
78 orr x0, x0, x1
79 msr CORTEX_A57_L2ECTLR_EL1, x0
82 mrs x0, CORTEX_A57_ECTLR_EL1
84 bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
[all …]
/rk3399_ARM-atf/plat/ti/common/
H A Dk3_helpers.S34 ldr x0, k3_boot_reason_data_store
35 cmp x0, #K3_BOOT_REASON_COLD_RESET
39 mov x0, #0
72 mrs x0, MPIDR_EL1
74 and x1, x0, #MPIDR_CLUSTER_MASK
76 and x0, x0, #MPIDR_CPU_MASK
80 add x0, x0, #K3_CLUSTER0_CORE_COUNT
84 add x0, x0, #K3_CLUSTER1_CORE_COUNT
88 add x0, x0, #K3_CLUSTER2_CORE_COUNT
107 mrs x0, CORTEX_A72_L2CTLR_EL1
[all …]
/rk3399_ARM-atf/plat/nuvoton/common/
H A Dnuvoton_helpers.S37 mrs x0, midr_el1
38 ubfx x0, x0, MIDR_PN_SHIFT, #12
72 mrs x0, mpidr_el1
73 and x0, x0, #(MPIDR_CPU_MASK)
74 cmp x0, #PLAT_PRIMARY_CPU
75 cset x0, eq
86 mrs x0, mpidr_el1
87 and x1, x0, #MPIDR_CPU_MASK
88 and x0, x0, #MPIDR_CLUSTER_MASK
89 add x0, x1, x0, LSR #6
[all …]
/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Ddsu_macros.S22 ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\
25 cmp x0, x1
26 csel x0, x2, x3, EQ
31 mrs x0, CLUSTERACTLR_EL1
32 orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING
33 msr CLUSTERACTLR_EL1, x0
38 mrs x0, CPUCFR_EL1
39 ubfx x0, x0, #SCU_SHIFT, #1
40 eor x0, x0, #1
42 cmp x0, xzr
[all …]
/rk3399_ARM-atf/plat/rpi/common/aarch64/
H A Dplat_helpers.S39 mrs x0, mpidr_el1
40 tst x0, #MPIDR_MT_MASK
41 lsr x1, x0, #MPIDR_AFFINITY_BITS
42 csel x0, x1, x0, ne
53 and x1, x0, #MPIDR_CPU_MASK
54 and x0, x0, #MPIDR_CLUSTER_MASK
55 add x0, x1, x0, LSR #6
67 mrs x0, mpidr_el1
68 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
69 cmp x0, #RPI_PRIMARY_CPU
[all …]
/rk3399_ARM-atf/include/arch/aarch64/
H A Del3_common_macros.S41 mrs x0, sctlr_el3
43 bic x0, x0, #SCTLR_BT_BIT
45 orr x0, x0, x1
46 msr sctlr_el3, x0
85 mov_imm x0, SCR_RESET_VAL
90 orr x0, x0, #SCR_EEL2_BIT
93 msr scr_el3, x0
99 mov_imm x0, MDCR_EL3_RESET_VAL
100 msr mdcr_el3, x0
107 mov_imm x0, CPTR_EL3_RESET_VAL
[all …]
/rk3399_ARM-atf/plat/marvell/armada/common/aarch64/
H A Dmarvell_helpers.S40 mrs x0, mpidr_el1
52 and x1, x0, #MPIDR_CPU_MASK
53 and x0, x0, #MPIDR_CLUSTER_MASK
54 add x0, x1, x0, LSR #7
71 mul x1, x0, x1
75 mov_imm x0, PLAT_MARVELL_UART_BASE
110 mov_imm x0, PLAT_MARVELL_UART_BASE
132 mrs x0, sctlr_el3
133 bic x0, x0, 0x1 /* M bit - MMU */
134 bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */
[all …]
/rk3399_ARM-atf/bl32/tsp/aarch64/
H A Dtsp_entrypoint.S32 ldp x6, x7, [x0, #SMC_ARG6]
33 ldp x4, x5, [x0, #SMC_ARG4]
34 ldp x2, x3, [x0, #SMC_ARG2]
35 ldp x0, x1, [x0, #SMC_ARG0]
59 mov x20, x0
75 ldr x0, =pie_fixup
76 and x0, x0, #~(PAGE_SIZE_MASK)
78 add x1, x1, x0
86 adr x0, tsp_exceptions
87 msr vbar_el1, x0
[all …]
/rk3399_ARM-atf/bl2/aarch64/
H A Dbl2_entrypoint.S22 mov x20, x0
31 adr x0, early_exceptions
32 msr vbar_el1, x0
49 mrs x0, sctlr_el1
50 orr x0, x0, x1
53 bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
55 bic x0, x0, #SCTLR_DSSBS_BIT
56 msr sctlr_el1, x0
68 adr x0, __RW_START__
70 sub x1, x1, x0
[all …]
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/arch/aarch64/
H A Dnrd_helper.S38 mov x4, x0
46 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
57 madd x0, x1, x4, x0
80 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
81 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
82 msr CORTEX_A75_CPUPWRCTLR_EL1, x0
87 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
88 bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
89 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
94 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
[all …]
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhisi_pwrc_sram.S19 mov x0, 0
20 msr oslar_el1, x0
22 mrs x0, CORTEX_A53_CPUACTLR_EL1
23 bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
25 orr x0, x0, #0x180000
26 orr x0, x0, #0xe000
27 msr CORTEX_A53_CPUACTLR_EL1, x0
38 mrs x0, mpidr_el1
39 and x1, x0, #MPIDR_CPU_MASK
40 and x0, x0, #MPIDR_CLUSTER_MASK
[all …]
/rk3399_ARM-atf/lib/libc/aarch64/
H A Dsetjmp.S20 stp x19, x20, [x0, #JMP_CTX_X19]
21 stp x21, x22, [x0, #JMP_CTX_X21]
22 stp x23, x24, [x0, #JMP_CTX_X23]
23 stp x25, x26, [x0, #JMP_CTX_X25]
24 stp x27, x28, [x0, #JMP_CTX_X27]
25 stp x29, x30, [x0, #JMP_CTX_X29]
26 stp x7, xzr, [x0, #JMP_CTX_SP]
28 mov x0, #0
37 ldp x7, xzr, [x0, #JMP_CTX_SP]
49 ldp x19, x20, [x0, #JMP_CTX_X19]
[all …]
/rk3399_ARM-atf/plat/brcm/board/stingray/aarch64/
H A Dplat_helpers.S44 mrs x0, CORTEX_A72_L2ACTLR_EL1
46 orr x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI
48 bic x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI
50 msr CORTEX_A72_L2ACTLR_EL1, x0
53 mrs x0, CORTEX_A72_L2CTLR_EL1
60 bic x0, x0, x1
65 orr x0, x0, x1
66 msr CORTEX_A72_L2CTLR_EL1, x0
100 mov x0, #0
116 add x0, x1, x0, LSL #3
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_trampoline.S23 adr x0, __tegra194_system_suspend_state
24 ldr x1, [x0]
36 str x1, [x0]
40 mov x0, #BL31_BASE
50 stp x3, x4, [x0], #16
57 strb w3, [x0], #1
69 adr x0, __tegra194_cpu_reset_handler_data
70 ldr x0, [x0]
71 br x0
112 adr x0, __tegra194_cpu_reset_handler_end
[all …]
/rk3399_ARM-atf/bl2u/aarch64/
H A Dbl2u_entrypoint.S28 adr x0, early_exceptions
29 msr vbar_el1, x0
46 mrs x0, sctlr_el1
47 orr x0, x0, x1
50 bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
52 bic x0, x0, #SCTLR_DSSBS_BIT
53 msr sctlr_el1, x0
65 adr x0, __RW_START__
67 sub x1, x1, x0
76 adrp x0, __BSS_START__
[all …]

12345678910>>...13