1127793daSHaojian Zhuang/* 2127793daSHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3127793daSHaojian Zhuang * 4127793daSHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5127793daSHaojian Zhuang */ 6127793daSHaojian Zhuang 7127793daSHaojian Zhuang#include <arch.h> 8127793daSHaojian Zhuang#include <asm_macros.S> 9127793daSHaojian Zhuang#include <cortex_a53.h> 10127793daSHaojian Zhuang#include <hi6220.h> 11127793daSHaojian Zhuang#include <hisi_sram_map.h> 12127793daSHaojian Zhuang 13127793daSHaojian Zhuang .global pm_asm_code 14127793daSHaojian Zhuang .global pm_asm_code_end 15127793daSHaojian Zhuang .global v7_asm 16127793daSHaojian Zhuang .global v7_asm_end 17127793daSHaojian Zhuang 1864726e6dSJulius Wernerfunc pm_asm_code _align=3 19127793daSHaojian Zhuang mov x0, 0 20127793daSHaojian Zhuang msr oslar_el1, x0 21127793daSHaojian Zhuang 22*f9a856baSEleanor Bonnici mrs x0, CORTEX_A53_CPUACTLR_EL1 23*f9a856baSEleanor Bonnici bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \ 24*f9a856baSEleanor Bonnici CORTEX_A53_CPUACTLR_EL1_L1RADIS) 25127793daSHaojian Zhuang orr x0, x0, #0x180000 26127793daSHaojian Zhuang orr x0, x0, #0xe000 27*f9a856baSEleanor Bonnici msr CORTEX_A53_CPUACTLR_EL1, x0 28127793daSHaojian Zhuang 29127793daSHaojian Zhuang mrs x3, actlr_el3 30127793daSHaojian Zhuang orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT 31127793daSHaojian Zhuang msr actlr_el3, x3 32127793daSHaojian Zhuang 33127793daSHaojian Zhuang mrs x3, actlr_el2 34127793daSHaojian Zhuang orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT 35127793daSHaojian Zhuang msr actlr_el2, x3 36127793daSHaojian Zhuang 37127793daSHaojian Zhuang ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD 38127793daSHaojian Zhuang mrs x0, mpidr_el1 39127793daSHaojian Zhuang and x1, x0, #MPIDR_CPU_MASK 40127793daSHaojian Zhuang and x0, x0, #MPIDR_CLUSTER_MASK 41127793daSHaojian Zhuang add x0, x1, x0, LSR #6 42127793daSHaojian Zhuangpen: ldr x4, [x3, x0, LSL #3] 43127793daSHaojian Zhuang cbz x4, pen 44127793daSHaojian Zhuang 45127793daSHaojian Zhuang mov x0, #0x0 46127793daSHaojian Zhuang mov x1, #0x0 47127793daSHaojian Zhuang mov x2, #0x0 48127793daSHaojian Zhuang mov x3, #0x0 49127793daSHaojian Zhuang br x4 50127793daSHaojian Zhuang 51127793daSHaojian Zhuang .ltorg 52127793daSHaojian Zhuang 53127793daSHaojian Zhuangpm_asm_code_end: 54127793daSHaojian Zhuangendfunc pm_asm_code 55127793daSHaojian Zhuang 56127793daSHaojian Zhuang /* 57127793daSHaojian Zhuang * By default, all cores in Hi6220 reset with aarch32 mode. 58127793daSHaojian Zhuang * Now hardcode ARMv7 instructions to execute warm reset for 59127793daSHaojian Zhuang * switching aarch64 mode. 60127793daSHaojian Zhuang */ 61127793daSHaojian Zhuang .align 3 62127793daSHaojian Zhuang .section .rodata.v7_asm, "aS" 63127793daSHaojian Zhuangv7_asm: 64127793daSHaojian Zhuang .word 0xE1A00000 // nop 65127793daSHaojian Zhuang .word 0xE3A02003 // mov r2, #3 66127793daSHaojian Zhuang .word 0xEE0C2F50 // mcr 15, 0, r2, cr12, cr0, {2} 67127793daSHaojian Zhuang .word 0xE320F003 // wfi 68127793daSHaojian Zhuang 69127793daSHaojian Zhuang .ltorg 70127793daSHaojian Zhuangv7_asm_end: 71