Lines Matching refs:x0
48 and x1, x0, #MPIDR_CPU_MASK
49 and x0, x0, #MPIDR_CLUSTER_MASK
50 add x0, x1, x0, LSR #6
59 mrs x0, mpidr_el1
79 mrs x0, mpidr_el1
84 mov x0, #0
110 mov x0, #0
122 lsl x0, x0, #CACHE_WRITEBACK_SHIFT
123 ldr x0, [x10, x0]
124 cbz x0, _panic
139 mrs x0, sctlr_el3
140 bic x0, x0, #SCTLR_EE_BIT
141 msr sctlr_el3, x0
144 mrs x0, cptr_el3
148 msr cptr_el3, x0
153 mov_imm x0, PARAMS_BASE
170 mov x20, x0
181 mov x0, #DCCISW
196 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
197 msr elr_el3, x0
214 ldr x0, =MBOX_BASE
217 str xzr, [x0], #CACHE_WRITEBACK_GRANULE
241 and x0, x0, x2
243 cmp x0, x1
245 mrs x0, ELR_EL3
265 mov x0, #0
275 mov x0, #1
341 ldr x0, =0xFFF00044
342 ldr w0, [x0]
359 mrs x0, midr_el1
360 ubfx x1, x0, MIDR_PN_SHIFT, #12
366 mrs x0, CORTEX_A57_L2CTLR_EL1
379 and x0, x0, x1
381 orr x0, x0, #0x2 << 6
385 orr x0, x0, #0x1 << 5
388 orr x0, x0, #0x3
390 msr CORTEX_A57_L2CTLR_EL1, x0