Lines Matching refs:x0
37 mrs x0, midr_el1
38 ubfx x0, x0, MIDR_PN_SHIFT, #12
72 mrs x0, mpidr_el1
73 and x0, x0, #(MPIDR_CPU_MASK)
74 cmp x0, #PLAT_PRIMARY_CPU
75 cset x0, eq
86 mrs x0, mpidr_el1
87 and x1, x0, #MPIDR_CPU_MASK
88 and x0, x0, #MPIDR_CLUSTER_MASK
89 add x0, x1, x0, LSR #6
99 and x1, x0, #MPIDR_CPU_MASK
100 and x0, x0, #MPIDR_CLUSTER_MASK
101 add x0, x1, x0, LSR #6
131 mov_imm x0, PLAT_NPCM_TM_HOLD_BASE
132 ldr x0, [x0]
133 cmp x0, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF
134 adr x0, plat_wait_for_warm_boot
135 csel x0, x0, xzr, eq
137 1: mov x0, #0
143 str x0, [x1, :lo12:mailbox_base]
153 lsl x0, x0, #3
155 add x0, x0, x2
156 mov x8, x0
165 str x1,[x0]
176 str x1,[x0]
180 ldr x1, [x0]
187 mov_imm x0, PLAT_NPCM_TM_ENTRYPOINT
188 ldr x1, [x0]
197 mov x0, #1
206 mov x0, #0