1b62673c6SBoyan Karatotev/* 2b62673c6SBoyan Karatotev * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. 3b62673c6SBoyan Karatotev * 4b62673c6SBoyan Karatotev * SPDX-License-Identifier: BSD-3-Clause 5b62673c6SBoyan Karatotev */ 6b62673c6SBoyan Karatotev 7b62673c6SBoyan Karatotev#ifndef DSU_MACROS_S 8b62673c6SBoyan Karatotev#define DSU_MACROS_S 9b62673c6SBoyan Karatotev 10b62673c6SBoyan Karatotev#include <asm_macros.S> 11b62673c6SBoyan Karatotev#include <dsu_def.h> 12b62673c6SBoyan Karatotev#include <lib/cpus/errata.h> 13b62673c6SBoyan Karatotev 14b62673c6SBoyan Karatotev.macro check_errata_dsu_798953_impl 15b62673c6SBoyan Karatotev mov x2, #ERRATA_APPLIES 16b62673c6SBoyan Karatotev mov x3, #ERRATA_NOT_APPLIES 17b62673c6SBoyan Karatotev 18b62673c6SBoyan Karatotev /* Check if DSU is equal to r0p0 */ 19b62673c6SBoyan Karatotev mrs x1, CLUSTERIDR_EL1 20b62673c6SBoyan Karatotev 21b62673c6SBoyan Karatotev /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ 22b62673c6SBoyan Karatotev ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ 23b62673c6SBoyan Karatotev #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) 24b62673c6SBoyan Karatotev mov x1, #(0x0 << CLUSTERIDR_REV_SHIFT) 25b62673c6SBoyan Karatotev cmp x0, x1 26b62673c6SBoyan Karatotev csel x0, x2, x3, EQ 27b62673c6SBoyan Karatotev.endm 28b62673c6SBoyan Karatotev 29b62673c6SBoyan Karatotev.macro errata_dsu_798953_wa_impl 30b62673c6SBoyan Karatotev /* If erratum applies, disable high-level clock gating */ 31b62673c6SBoyan Karatotev mrs x0, CLUSTERACTLR_EL1 32b62673c6SBoyan Karatotev orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING 33b62673c6SBoyan Karatotev msr CLUSTERACTLR_EL1, x0 34b62673c6SBoyan Karatotev.endm 35b62673c6SBoyan Karatotev 36b62673c6SBoyan Karatotev.macro branch_if_scu_not_present _target:req 37b62673c6SBoyan Karatotev /* Check if the SCU L3 Unit is present on the DSU */ 38b62673c6SBoyan Karatotev mrs x0, CPUCFR_EL1 39b62673c6SBoyan Karatotev ubfx x0, x0, #SCU_SHIFT, #1 40b62673c6SBoyan Karatotev eor x0, x0, #1 41b62673c6SBoyan Karatotev /* If SCU is not present, return without applying patch */ 42b62673c6SBoyan Karatotev cmp x0, xzr 43b62673c6SBoyan Karatotev mov x0, #ERRATA_NOT_APPLIES 44b62673c6SBoyan Karatotev b.eq \_target 45b62673c6SBoyan Karatotev.endm 46b62673c6SBoyan Karatotev 47b62673c6SBoyan Karatotev.macro check_errata_dsu_936184_impl 48b62673c6SBoyan Karatotev mov x0, #ERRATA_NOT_APPLIES 49b62673c6SBoyan Karatotev /* Erratum applies only if DSU has the ACP interface */ 50b62673c6SBoyan Karatotev mrs x1, CLUSTERCFR_EL1 51b62673c6SBoyan Karatotev ubfx x1, x1, #CLUSTERCFR_ACP_SHIFT, #1 52b62673c6SBoyan Karatotev cbz x1, 1f 53b62673c6SBoyan Karatotev 54b62673c6SBoyan Karatotev /* If ACP is present, check if DSU is older than r2p0 */ 55b62673c6SBoyan Karatotev mrs x1, CLUSTERIDR_EL1 56b62673c6SBoyan Karatotev 57b62673c6SBoyan Karatotev /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ 58b62673c6SBoyan Karatotev ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\ 59b62673c6SBoyan Karatotev #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) 60b62673c6SBoyan Karatotev cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT) 61b62673c6SBoyan Karatotev b.hs 1f 62b62673c6SBoyan Karatotev mov x0, #ERRATA_APPLIES 63b62673c6SBoyan Karatotev1: 64b62673c6SBoyan Karatotev.endm 65b62673c6SBoyan Karatotev 66b62673c6SBoyan Karatotev.macro errata_dsu_936184_wa_impl 67b62673c6SBoyan Karatotev /* If erratum applies, we set a mask to a DSU control register */ 68b62673c6SBoyan Karatotev mrs x0, CLUSTERACTLR_EL1 69b62673c6SBoyan Karatotev ldr x1, =DSU_ERRATA_936184_MASK 70b62673c6SBoyan Karatotev orr x0, x0, x1 71b62673c6SBoyan Karatotev msr CLUSTERACTLR_EL1, x0 72b62673c6SBoyan Karatotev.endm 73b62673c6SBoyan Karatotev 74b62673c6SBoyan Karatotev.macro check_errata_dsu_2313941_impl 75b62673c6SBoyan Karatotev mov x2, #ERRATA_APPLIES 76b62673c6SBoyan Karatotev mov x3, #ERRATA_NOT_APPLIES 77b62673c6SBoyan Karatotev 78b62673c6SBoyan Karatotev /* Check if DSU version is less than or equal to r3p1 */ 79b62673c6SBoyan Karatotev mrs x1, CLUSTERIDR_EL1 80b62673c6SBoyan Karatotev 81b62673c6SBoyan Karatotev mov x0, #ERRATA_NOT_APPLIES 82b62673c6SBoyan Karatotev /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ 83b62673c6SBoyan Karatotev ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ 84b62673c6SBoyan Karatotev #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) 85b62673c6SBoyan Karatotev mov x1, #(0x31 << CLUSTERIDR_REV_SHIFT) 86b62673c6SBoyan Karatotev cmp x0, x1 87b62673c6SBoyan Karatotev csel x0, x2, x3, LS 88b62673c6SBoyan Karatotev1: 89b62673c6SBoyan Karatotev.endm 90b62673c6SBoyan Karatotev 91b62673c6SBoyan Karatotev.macro errata_dsu_2313941_wa_impl 92b62673c6SBoyan Karatotev /* If erratum applies, disable high-level clock gating */ 93b62673c6SBoyan Karatotev mrs x0, CLUSTERACTLR_EL1 94b62673c6SBoyan Karatotev orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING 95b62673c6SBoyan Karatotev msr CLUSTERACTLR_EL1, x0 96b62673c6SBoyan Karatotev.endm 97*efc945f1SArvind Ram Prakash 98*efc945f1SArvind Ram Prakash/* 99*efc945f1SArvind Ram Prakash * Check if erratum is fixed via CLUSTERREVIDR_EL1 bit (\bitpos). 100*efc945f1SArvind Ram Prakash * If not fixed (bit is clear), set x0 = ERRATA_APPLIES (from x3). 101*efc945f1SArvind Ram Prakash * If fixed (bit is set), keep x0 = ERRATA_NOT_APPLIES. 102*efc945f1SArvind Ram Prakash */ 103*efc945f1SArvind Ram Prakash.macro check_revidr_bit bitpos:req 104*efc945f1SArvind Ram Prakash mrs x4, CLUSTERREVIDR_EL1 105*efc945f1SArvind Ram Prakash mov x1, #1 106*efc945f1SArvind Ram Prakash lsl x1, x1, #\bitpos 107*efc945f1SArvind Ram Prakash tst x1, x4 108*efc945f1SArvind Ram Prakash csel x0, x0, x3, NE 109*efc945f1SArvind Ram Prakash.endm 110*efc945f1SArvind Ram Prakash 111*efc945f1SArvind Ram Prakash.macro check_errata_dsu_2900952_applies 112*efc945f1SArvind Ram Prakash mov x0, #ERRATA_NOT_APPLIES 113*efc945f1SArvind Ram Prakash mov x3, #ERRATA_APPLIES 114*efc945f1SArvind Ram Prakash 115*efc945f1SArvind Ram Prakash /* Check if DSU revision is equal to r2p0 */ 116*efc945f1SArvind Ram Prakash mrs x1, CLUSTERIDR_EL1 117*efc945f1SArvind Ram Prakash 118*efc945f1SArvind Ram Prakash /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ 119*efc945f1SArvind Ram Prakash ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\ 120*efc945f1SArvind Ram Prakash #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) 121*efc945f1SArvind Ram Prakash cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT) 122*efc945f1SArvind Ram Prakash b.ne 1f 123*efc945f1SArvind Ram Prakash check_revidr_bit 1 124*efc945f1SArvind Ram Prakash1: 125*efc945f1SArvind Ram Prakash.endm 126*efc945f1SArvind Ram Prakash 127*efc945f1SArvind Ram Prakash.macro errata_dsu_2900952_wa_apply 128*efc945f1SArvind Ram Prakash 129*efc945f1SArvind Ram Prakash ldr x1, =((CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY | \ 130*efc945f1SArvind Ram Prakash CLUSTERACTLR_EL1_ASSERT_CBUSY)) 131*efc945f1SArvind Ram Prakash 132*efc945f1SArvind Ram Prakash mrs x0, CLUSTERACTLR_EL1 133*efc945f1SArvind Ram Prakash orr x0, x0, x1 134*efc945f1SArvind Ram Prakash msr CLUSTERACTLR_EL1, x0 135*efc945f1SArvind Ram Prakash.endm 136*efc945f1SArvind Ram Prakash 137b62673c6SBoyan Karatotev#endif /* DSU_MACROS_S */ 138