Lines Matching refs:x0
39 mrs x0, mpidr_el1
40 tst x0, #MPIDR_MT_MASK
41 lsr x1, x0, #MPIDR_AFFINITY_BITS
42 csel x0, x1, x0, ne
53 and x1, x0, #MPIDR_CPU_MASK
54 and x0, x0, #MPIDR_CLUSTER_MASK
55 add x0, x1, x0, LSR #6
67 mrs x0, mpidr_el1
68 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
69 cmp x0, #RPI_PRIMARY_CPU
89 lsl x0, x0, #3
91 add x0, x0, x2
98 str x1,[x0]
103 ldr x1, [x0]
108 mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
109 ldr x1, [x0]
148 mov_imm x0, PLAT_RPI3_TM_HOLD_BASE
149 ldr x0, [x0]
150 cmp x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF
151 adr x0, plat_wait_for_warm_boot
152 csel x0, x0, xzr, eq
154 1: mov x0, #0
176 mov_imm x0, PLAT_RPI_CRASH_UART_BASE
213 mov_imm x0, PLAT_RPI_CRASH_UART_BASE
231 mrs x0, midr_el1
232 and x0, x0, #0xf0 /* Isolate low byte of part number */
259 mrs x0, CORTEX_A72_L2CTLR_EL1
261 orr x0, x0, x1
262 msr CORTEX_A72_L2CTLR_EL1, x0