1bd08def3SAnson Huang/* 2fcd41e86SJacky Bai * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3bd08def3SAnson Huang * 4bd08def3SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5bd08def3SAnson Huang */ 6bd08def3SAnson Huang 7bd08def3SAnson Huang#include <asm_macros.S> 8bd08def3SAnson Huang#include <platform_def.h> 9bd08def3SAnson Huang#include <cortex_a35.h> 10bd08def3SAnson Huang 11bd08def3SAnson Huang .globl plat_is_my_cpu_primary 12bd08def3SAnson Huang .globl plat_my_core_pos 13bd08def3SAnson Huang .globl plat_calc_core_pos 14bd08def3SAnson Huang .globl plat_reset_handler 15bd08def3SAnson Huang .globl plat_get_my_entrypoint 16bd08def3SAnson Huang .globl plat_secondary_cold_boot_setup 17bd08def3SAnson Huang .globl plat_crash_console_init 18bd08def3SAnson Huang .globl plat_crash_console_putc 199c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 20bd08def3SAnson Huang .globl platform_mem_init 21bd08def3SAnson Huang .globl imx_mailbox_init 22bd08def3SAnson Huang 23bd08def3SAnson Huang /* -------------------------------------------------------------------- 24bd08def3SAnson Huang * Helper macro that reads the part number of the current CPU and jumps 25bd08def3SAnson Huang * to the given label if it matches the CPU MIDR provided. 26bd08def3SAnson Huang * 27bd08def3SAnson Huang * Clobbers x0. 28bd08def3SAnson Huang * -------------------------------------------------------------------- 29bd08def3SAnson Huang */ 30bd08def3SAnson Huang .macro jump_if_cpu_midr _cpu_midr, _label 31bd08def3SAnson Huang 32bd08def3SAnson Huang mrs x0, midr_el1 33bd08def3SAnson Huang ubfx x0, x0, MIDR_PN_SHIFT, #12 34bd08def3SAnson Huang cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 35bd08def3SAnson Huang b.eq \_label 36bd08def3SAnson Huang 37bd08def3SAnson Huang .endm 38bd08def3SAnson Huang 39bd08def3SAnson Huang /* ---------------------------------------------- 40bd08def3SAnson Huang * The mailbox_base is used to distinguish warm/cold 41bd08def3SAnson Huang * reset. The mailbox_base is in the data section, not 42bd08def3SAnson Huang * in .bss, this allows function to start using this 43bd08def3SAnson Huang * variable before the runtime memory is initialized. 44bd08def3SAnson Huang * ---------------------------------------------- 45bd08def3SAnson Huang */ 46bd08def3SAnson Huang .section .data.mailbox_base 47bd08def3SAnson Huang .align 3 48bd08def3SAnson Huang mailbox_base: .quad 0x0 49bd08def3SAnson Huang 50bd08def3SAnson Huang /* ---------------------------------------------- 51bd08def3SAnson Huang * unsigned int plat_is_my_cpu_primary(void); 52bd08def3SAnson Huang * This function checks if this is the primary CPU 53bd08def3SAnson Huang * ---------------------------------------------- 54bd08def3SAnson Huang */ 55bd08def3SAnson Huangfunc plat_is_my_cpu_primary 56bd08def3SAnson Huang mrs x0, mpidr_el1 57bd08def3SAnson Huang and x0, x0, #(MPIDR_CPU_MASK) 58bd08def3SAnson Huang cmp x0, #PLAT_PRIMARY_CPU 59bd08def3SAnson Huang cset x0, eq 60bd08def3SAnson Huang ret 61bd08def3SAnson Huangendfunc plat_is_my_cpu_primary 62bd08def3SAnson Huang 63bd08def3SAnson Huang /* ---------------------------------------------- 64bd08def3SAnson Huang * unsigned int plat_my_core_pos(void) 65bd08def3SAnson Huang * This Function uses the plat_calc_core_pos() 66bd08def3SAnson Huang * to get the index of the calling CPU. 67bd08def3SAnson Huang * ---------------------------------------------- 68bd08def3SAnson Huang */ 69bd08def3SAnson Huangfunc plat_my_core_pos 70bd08def3SAnson Huang mrs x0, mpidr_el1 71bd08def3SAnson Huang and x1, x0, #MPIDR_CPU_MASK 72bd08def3SAnson Huang and x0, x0, #MPIDR_CLUSTER_MASK 73bd08def3SAnson Huang add x0, x1, x0, LSR #6 74bd08def3SAnson Huang ret 75bd08def3SAnson Huangendfunc plat_my_core_pos 76bd08def3SAnson Huang 77bd08def3SAnson Huang /* 78bd08def3SAnson Huang * unsigned int plat_calc_core_pos(uint64_t mpidr) 79bd08def3SAnson Huang * helper function to calculate the core position. 80bd08def3SAnson Huang * With this function. 81bd08def3SAnson Huang */ 82bd08def3SAnson Huangfunc plat_calc_core_pos 83bd08def3SAnson Huang and x1, x0, #MPIDR_CPU_MASK 84bd08def3SAnson Huang and x0, x0, #MPIDR_CLUSTER_MASK 85bd08def3SAnson Huang add x0, x1, x0, LSR #6 86bd08def3SAnson Huang ret 87bd08def3SAnson Huangendfunc plat_calc_core_pos 88bd08def3SAnson Huang 89fcd41e86SJacky Bai /* ---------------------------------------------- 90fcd41e86SJacky Bai * function to handle platform specific reset. 91fcd41e86SJacky Bai * ---------------------------------------------- 92fcd41e86SJacky Bai */ 93fcd41e86SJacky Baifunc plat_reset_handler 94fcd41e86SJacky Bai#if defined(PLAT_imx8ulp) 95*bcca70b9SJacky Bai /* enable the 512KB cache by default */ 96*bcca70b9SJacky Bai mov x0, #IMX_SIM1_BASE 97*bcca70b9SJacky Bai /* 98*bcca70b9SJacky Bai * if the RVBADDR is ROM entry, that means we did 99*bcca70b9SJacky Bai * NOT switch the L2 cache to 512KB. default is 256K config, 100*bcca70b9SJacky Bai * so skip 101*bcca70b9SJacky Bai */ 102*bcca70b9SJacky Bai ldr w1, [x0, #0x5c] 103*bcca70b9SJacky Bai cmp w1, #0x1000 104*bcca70b9SJacky Bai b.eq 1f 105*bcca70b9SJacky Bai add x0, x0, #0x30 106*bcca70b9SJacky Bai ldr w1, [x0] 107*bcca70b9SJacky Bai /* if already 512KB config, skip */ 108*bcca70b9SJacky Bai tbnz w1, #4, 1f 109*bcca70b9SJacky Bai ldr w1, [x0] 110*bcca70b9SJacky Bai orr w1, w1, #0x10 111*bcca70b9SJacky Bai str w1, [x0] 112*bcca70b9SJacky Bai orr w1, w1, #0x10000 113*bcca70b9SJacky Bai str w1, [x0] 114*bcca70b9SJacky Bai b . 115*bcca70b9SJacky Bai1: mrs x0, CORTEX_A35_CPUECTLR_EL1 116fcd41e86SJacky Bai orr x0, x0, #(0x1 << 0) 117fcd41e86SJacky Bai orr x0, x0, #(0x1 << 3) 118fcd41e86SJacky Bai msr CORTEX_A35_CPUECTLR_EL1, x0 119fcd41e86SJacky Bai 120fcd41e86SJacky Bai mrs x0, CORTEX_A35_L2ECTLR_EL1 121fcd41e86SJacky Bai orr x0, x0, #(0x1 << 0) 122fcd41e86SJacky Bai msr CORTEX_A35_L2ECTLR_EL1, x0 123fcd41e86SJacky Bai isb 124fcd41e86SJacky Bai#endif 125fcd41e86SJacky Bai /* enable EL2 cpuectlr RW access */ 126fcd41e86SJacky Bai mov x0, #0x73 127fcd41e86SJacky Bai msr actlr_el3, x0 128fcd41e86SJacky Bai msr actlr_el2, x0 129fcd41e86SJacky Bai isb 130fcd41e86SJacky Bai 131fcd41e86SJacky Bai ret 132fcd41e86SJacky Baiendfunc plat_reset_handler 133fcd41e86SJacky Bai 134bd08def3SAnson Huang /* --------------------------------------------- 135bd08def3SAnson Huang * function to get the entrypoint. 136bd08def3SAnson Huang * --------------------------------------------- 137bd08def3SAnson Huang */ 138bd08def3SAnson Huangfunc plat_get_my_entrypoint 139bd08def3SAnson Huang adrp x1, mailbox_base 140bd08def3SAnson Huang ldr x0, [x1, :lo12:mailbox_base] 141bd08def3SAnson Huang ret 142bd08def3SAnson Huangendfunc plat_get_my_entrypoint 143bd08def3SAnson Huang 144bd08def3SAnson Huangfunc imx_mailbox_init 145bd08def3SAnson Huang adrp x1, mailbox_base 146bd08def3SAnson Huang str x0, [x1, :lo12:mailbox_base] 147bd08def3SAnson Huang ret 148bd08def3SAnson Huangendfunc imx_mailbox_init 149bd08def3SAnson Huang 150bd08def3SAnson Huangfunc plat_secondary_cold_boot_setup 151bd08def3SAnson Huang b . 152bd08def3SAnson Huangendfunc plat_secondary_cold_boot_setup 153bd08def3SAnson Huang 154bd08def3SAnson Huangfunc plat_crash_console_init 1559c675b37SAntonio Nino Diaz mov x0, #1 156bd08def3SAnson Huang ret 157bd08def3SAnson Huangendfunc plat_crash_console_init 158bd08def3SAnson Huang 159bd08def3SAnson Huangfunc plat_crash_console_putc 160bd08def3SAnson Huang ret 161bd08def3SAnson Huangendfunc plat_crash_console_putc 162bd08def3SAnson Huang 1639c675b37SAntonio Nino Diazfunc plat_crash_console_flush 1649c675b37SAntonio Nino Diaz mov x0, #0 1659c675b37SAntonio Nino Diaz ret 1669c675b37SAntonio Nino Diazendfunc plat_crash_console_flush 1679c675b37SAntonio Nino Diaz 168bd08def3SAnson Huangfunc platform_mem_init 169bd08def3SAnson Huang ret 170bd08def3SAnson Huangendfunc platform_mem_init 171