| #
cab31629 |
| 15-Oct-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(rcar3): clear TCR_EL1 at the BL2 entry point" into integration
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| #
fe87637a |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(rcar3): clear TCR_EL1 at the BL2 entry point
According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to a
fix(rcar3): clear TCR_EL1 at the BL2 entry point
According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to an architecturally UNKNOWN value.
On some SoCs, after reset, this TCR_EL1 may not be 0, which in itself
is perfectly valid behavior. However, existing software may depend on
TCR_EL1 being 0, and the UNKNOWN value may confuse such software.
Reset TCR_EL1 to well defined value 0 at BL2 entrypoint to achieve
maximum compatibility.
[1] https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message
Change-Id: If3a1d40291b9b9768a8fc55e750bd742f3cc4ddc
---
Note: This is related to MR 25532 , but with reworked commit message
and broken out from the large work-in-progress series.
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| #
4b8e5078 |
| 23-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Ib481fade,Id4070b46,I4ac997cd into integration
* changes:
feat(rcar3): update IPL and Secure Monitor Rev.4.0.0
feat(rcar3): add cache operations to boot process
feat(rcar3): chan
Merge changes Ib481fade,Id4070b46,I4ac997cd into integration
* changes:
feat(rcar3): update IPL and Secure Monitor Rev.4.0.0
feat(rcar3): add cache operations to boot process
feat(rcar3): change MMU configurations
show more ...
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| #
5e8c2d8e |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(rcar3): change MMU configurations
Always enable MMU and control access protection.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yosh
feat(rcar3): change MMU configurations
Always enable MMU and control access protection.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I4ac997cda2985746b2bf97ab9e4e5ace600f43ca
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| #
dc2b8e80 |
| 23-Feb-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "panic_cleanup" into integration
* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remo
Merge changes from topic "panic_cleanup" into integration
* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remove weak links to el3_panic
refactor(aarch64): refactor usage of elx_panic
refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage
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| #
bd62ce98 |
| 16-Jan-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(aarch64): rename do_panic and el3_panic
Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
wh
refactor(aarch64): rename do_panic and el3_panic
Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
which handles panic from lower ELs.
So now we can remove do_panic and just call el3_panic for all panics.
Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| #
a6db44ad |
| 05-Oct-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration
* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
fea
Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration
* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
feat(plat/rcar3): modify LifeC register setting for R-Car D3
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
feat(plat/rcar3): update DDR setting for R-Car D3
feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3
feat(plat/rcar3): add process of SSCG setting for R-Car D3
feat(plat/rcar3): add process to back up X6 and X7 register's value
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
feat(plat/rcar3): change the memory map for OP-TEE
feat(plat/rcar3): use PRR cut to determine DRAM size on M3
feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537
fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3
fix(plat/rcar3): fix eMMC boot support for R-Car D3
fix(plat/rcar3): fix version judgment for R-Car D3
fix(plat/rcar3): fix source file to make about GICv2
fix(drivers/rcar3): console: fix a return value of console_rcar_init
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| #
7d58aed3 |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): add process to back up X6 and X7 register's value
Because the x6 and x7 registers will be overwritten by the callee function,
added the processing the register's value push to/pop
feat(plat/rcar3): add process to back up X6 and X7 register's value
Because the x6 and x7 registers will be overwritten by the callee function,
added the processing the register's value push to/pop from stack memory.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8
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| #
65d227c3 |
| 14-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration
* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: re
Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration
* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: renesas: aarch64: Move to common
drivers: renesas: Move ddr/qos/qos header files
drivers: renesas: rpc: Move to common
drivers: renesas: avs: Move to common
drivers: renesas: auth: Move to common
drivers: renesas: dma: Move to common
drivers: renesas: watchdog: Move to common
drivers: renesas: rom: Move to common
drivers: renesas: delay: Move to common
drivers: renesas: console: Move to common
drivers: renesas: pwrc: Move to common
drivers: renesas: io: Move to common
drivers: renesas: eMMC: Move to common
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| #
fd9b3c5a |
| 16-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
plat: renesas: aarch64: Move to common
Move plat aarch64 code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@
plat: renesas: aarch64: Move to common
Move plat aarch64 code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I66265e5e68bfcf5c3534965fb3549a145c782b47
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