Lines Matching refs:x0
32 mrs x0, midr_el1
33 ubfx x0, x0, MIDR_PN_SHIFT, #12
56 mrs x0, mpidr_el1
57 and x0, x0, #(MPIDR_CPU_MASK)
58 cmp x0, #PLAT_PRIMARY_CPU
59 cset x0, eq
70 mrs x0, mpidr_el1
71 and x1, x0, #MPIDR_CPU_MASK
72 and x0, x0, #MPIDR_CLUSTER_MASK
73 add x0, x1, x0, LSR #6
83 and x1, x0, #MPIDR_CPU_MASK
84 and x0, x0, #MPIDR_CLUSTER_MASK
85 add x0, x1, x0, LSR #6
96 mov x0, #IMX_SIM1_BASE
102 ldr w1, [x0, #0x5c]
105 add x0, x0, #0x30
106 ldr w1, [x0]
109 ldr w1, [x0]
111 str w1, [x0]
113 str w1, [x0]
115 1: mrs x0, CORTEX_A35_CPUECTLR_EL1
116 orr x0, x0, #(0x1 << 0)
117 orr x0, x0, #(0x1 << 3)
118 msr CORTEX_A35_CPUECTLR_EL1, x0
120 mrs x0, CORTEX_A35_L2ECTLR_EL1
121 orr x0, x0, #(0x1 << 0)
122 msr CORTEX_A35_L2ECTLR_EL1, x0
126 mov x0, #0x73
127 msr actlr_el3, x0
128 msr actlr_el2, x0
140 ldr x0, [x1, :lo12:mailbox_base]
146 str x0, [x1, :lo12:mailbox_base]
155 mov x0, #1
164 mov x0, #0