Merge changes from topic "xl/a76ae-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus):

Merge changes from topic "xl/a76ae-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus): workaround for Cortex-A76AE erratum 1931435
fix(cpus): workaround for Cortex-A76AE erratum 1931427

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fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setti

fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setting CPUACTLR2_EL1[0] to 1. The
bit force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches. There might be a small performance
degradation to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: Id65846bebde1a0911ba11956202d0d255d3c8c82
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a

fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the i

Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the init_cpu_data_ptr function
perf(cpus): inline the reset function
perf(cpus): inline the cpu_get_rev_var call
perf(cpus): inline cpu_rev_var checks
refactor(cpus): register DSU errata with the errata framework's wrappers
refactor(cpus): convert checker functions to standard helpers
refactor(cpus): convert the Cortex-A65 to use the errata framework
fix(cpus): declare reset errata correctly

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perf(cpus): make reset errata do fewer branches

Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and cach

perf(cpus): make reset errata do fewer branches

Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and caches will be empty so a branch to a workaround function must be
fetched from memory and that round trip is very slow. Then it also runs
with the I-cache off, which means that the loop to iterate over the
workarounds must also be fetched from memory on each iteration.

We can remove both branches. First, we can simply apply every erratum
directly instead of defining a workaround function and jumping to it.
Currently, no errata that need to be applied at both reset and runtime,
with the same workaround function, exist. If the need arose in future,
this should be achievable with a reset + runtime wrapper combo.

Then, we can construct a function that applies each erratum linearly
instead of looping over the list. If this function is part of the reset
function, then the only "far" branches at reset will be for the checker
functions. Importantly, this mitigates the slowdown even when an erratum
is disabled.

The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup
from PSCI calls that end in powerdown. This is roughly back to the
baseline of v2.9, before the errata framework regressed on performance
(or a little better). It is important to note that there are other
slowdowns since then that remain unknown.

Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "clean-up-errata-compatibility" into integration

* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "gr/errata_refactor" into integration

* changes:
refactor(cpus): convert the Cortex-A55 to use cpu helpers
refactor(cpus): convert the Cortex-A55 to use the errata frame

Merge changes from topic "gr/errata_refactor" into integration

* changes:
refactor(cpus): convert the Cortex-A55 to use cpu helpers
refactor(cpus): convert the Cortex-A55 to use the errata framework
refactor(cpus): convert the Cortex-A76AE to use cpu helpers
refactor(cpus): convert the Cortex-A76AE to use the errata framework
refactor(cpus): convert the Cortex-A78 to use cpu helpers
refactor(cpus): convert the Cortex-A78 to use the errata framework
refactor(cpus): reorder Cortex-A78 errata by ascending order
refactor(cpus): convert the Cortex-A78C to use cpu helpers
refactor(cpus): convert the Cortex-A78C to use the errata framework
refactor(cpus): reorder Cortex-A78C errata by ascending order
refactor(cpus): convert the Cortex-X1 to use cpu helpers
refactor(cpus): convert the Cortex-X1 to use the errata framework
refactor(cpus): reorder Cortex-X1 errata by ascending order
refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpu
refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus

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refactor(cpus): convert the Cortex-A76AE to use cpu helpers

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I72627afd0e2f10fb754d5c0de137fc9714ed391f

refactor(cpus): convert the Cortex-A76AE to use the errata framework

Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Buildi

refactor(cpus): convert the Cortex-A76AE to use the errata framework

Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with errata and stepping through from ArmDS and running tftf.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I1936ab6aaef803f653e79f5c6b590a59b34a8ed1

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Merge "fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C" into integration

fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C

Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Sig

fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C

Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548

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Merge "Apply compile-time check for AArch64-only cores" into integration

Apply compile-time check for AArch64-only cores

Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is suppose

Apply compile-time check for AArch64-only cores

Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is supposed to run on AArch64-only cores, it must be compiled with
CTX_INCLUDE_AARCH32_REGS=0.

Currently, the default settings for compiling TF-A are with the AArch32
system registers included. So, if we compile TF-A the default way and
attempt to run it on an AArch64-only core, we only get a runtime panic.

Now a compile-time check has been added to ensure that this flag has the
appropriate value when AArch64-only cores are included in the build.

Change-Id: I298ec550037fafc9347baafb056926d149197d4c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration

Add compile-time errors for HW_ASSISTED_COHERENCY flag

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores imp

Add compile-time errors for HW_ASSISTED_COHERENCY flag

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge "Add support for Cortex-A76AE CPU" into integration

Add support for Cortex-A76AE CPU

Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>