108438e24SVarun Wadekar/* 2544c092bSAmbroise Vincent * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3b1481cffSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 7a69a1112SVarun Wadekar 808438e24SVarun Wadekar#include <arch.h> 908438e24SVarun Wadekar#include <asm_macros.S> 1008438e24SVarun Wadekar#include <assert_macros.S> 11ee1ebbd1SIsla Mitchell#include <cortex_a57.h> 12a69a1112SVarun Wadekar#include <cpu_macros.S> 13a69a1112SVarun Wadekar 1411bd24beSVarun Wadekar#include <platform_def.h> 1508438e24SVarun Wadekar#include <tegra_def.h> 16c195fec6SHarvey Hsieh#include <tegra_platform.h> 1708438e24SVarun Wadekar 180cd6138dSVarun Wadekar#define MIDR_PN_CORTEX_A57 0xD07 190cd6138dSVarun Wadekar 200cd6138dSVarun Wadekar/******************************************************************************* 210cd6138dSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 220cd6138dSVarun Wadekar ******************************************************************************/ 23b1481cffSVarun Wadekar#define ACTLR_ELx_L2ACTLR_BIT (U(1) << 6) 24b1481cffSVarun Wadekar#define ACTLR_ELx_L2ECTLR_BIT (U(1) << 5) 25b1481cffSVarun Wadekar#define ACTLR_ELx_L2CTLR_BIT (U(1) << 4) 26b1481cffSVarun Wadekar#define ACTLR_ELx_CPUECTLR_BIT (U(1) << 1) 27b1481cffSVarun Wadekar#define ACTLR_ELx_CPUACTLR_BIT (U(1) << 0) 28b1481cffSVarun Wadekar#define ACTLR_ELx_ENABLE_ALL_ACCESS (ACTLR_ELx_L2ACTLR_BIT | \ 29b1481cffSVarun Wadekar ACTLR_ELx_L2ECTLR_BIT | \ 30b1481cffSVarun Wadekar ACTLR_ELx_L2CTLR_BIT | \ 31b1481cffSVarun Wadekar ACTLR_ELx_CPUECTLR_BIT | \ 32b1481cffSVarun Wadekar ACTLR_ELx_CPUACTLR_BIT) 330cd6138dSVarun Wadekar 3408438e24SVarun Wadekar /* Global functions */ 3571cb26eaSVarun Wadekar .globl plat_is_my_cpu_primary 3671cb26eaSVarun Wadekar .globl plat_my_core_pos 3771cb26eaSVarun Wadekar .globl plat_get_my_entrypoint 3808438e24SVarun Wadekar .globl plat_secondary_cold_boot_setup 3908438e24SVarun Wadekar .globl platform_mem_init 4008438e24SVarun Wadekar .globl plat_crash_console_init 4108438e24SVarun Wadekar .globl plat_crash_console_putc 429c675b37SAntonio Nino Diaz .globl plat_crash_console_flush 430ac1bf72SVarun Wadekar .weak plat_core_pos_by_mpidr 4408438e24SVarun Wadekar .globl tegra_secure_entrypoint 4508438e24SVarun Wadekar .globl plat_reset_handler 4608438e24SVarun Wadekar 4708438e24SVarun Wadekar /* Global variables */ 4871cb26eaSVarun Wadekar .globl tegra_sec_entry_point 4908438e24SVarun Wadekar .globl ns_image_entrypoint 5008438e24SVarun Wadekar .globl tegra_bl31_phys_base 51e1084216SVarun Wadekar .globl tegra_console_base 5208438e24SVarun Wadekar 5308438e24SVarun Wadekar /* --------------------- 5408438e24SVarun Wadekar * Common CPU init code 5508438e24SVarun Wadekar * --------------------- 5608438e24SVarun Wadekar */ 5708438e24SVarun Wadekar.macro cpu_init_common 5808438e24SVarun Wadekar 590cd6138dSVarun Wadekar /* ------------------------------------------------ 60018b8480SVarun Wadekar * We enable procesor retention, L2/CPUECTLR NS 61018b8480SVarun Wadekar * access and ECC/Parity protection for A57 CPUs 620cd6138dSVarun Wadekar * ------------------------------------------------ 630cd6138dSVarun Wadekar */ 640cd6138dSVarun Wadekar mrs x0, midr_el1 650cd6138dSVarun Wadekar mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) 660cd6138dSVarun Wadekar and x0, x0, x1 670cd6138dSVarun Wadekar lsr x0, x0, #MIDR_PN_SHIFT 680cd6138dSVarun Wadekar cmp x0, #MIDR_PN_CORTEX_A57 690cd6138dSVarun Wadekar b.ne 1f 700cd6138dSVarun Wadekar 71b42192bcSVarun Wadekar /* --------------------------- 72b42192bcSVarun Wadekar * Enable processor retention 73b42192bcSVarun Wadekar * --------------------------- 74b42192bcSVarun Wadekar */ 75fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_L2ECTLR_EL1 76fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 77fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK 78b42192bcSVarun Wadekar orr x0, x0, x1 79fb7d32e5SVarun Wadekar msr CORTEX_A57_L2ECTLR_EL1, x0 80b42192bcSVarun Wadekar isb 81b42192bcSVarun Wadekar 82fb7d32e5SVarun Wadekar mrs x0, CORTEX_A57_ECTLR_EL1 83fb7d32e5SVarun Wadekar mov x1, #RETENTION_ENTRY_TICKS_512 84fb7d32e5SVarun Wadekar bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK 85b42192bcSVarun Wadekar orr x0, x0, x1 86fb7d32e5SVarun Wadekar msr CORTEX_A57_ECTLR_EL1, x0 87b42192bcSVarun Wadekar isb 88b42192bcSVarun Wadekar 8908438e24SVarun Wadekar /* ------------------------------------------------------- 9008438e24SVarun Wadekar * Enable L2 and CPU ECTLR RW access from non-secure world 9108438e24SVarun Wadekar * ------------------------------------------------------- 9208438e24SVarun Wadekar */ 9375516c3eSSteven Kao mrs x0, actlr_el3 94b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9575516c3eSSteven Kao orr x0, x0, x1 9608438e24SVarun Wadekar msr actlr_el3, x0 9775516c3eSSteven Kao mrs x0, actlr_el2 98b1481cffSVarun Wadekar mov x1, #ACTLR_ELx_ENABLE_ALL_ACCESS 9975516c3eSSteven Kao orr x0, x0, x1 10008438e24SVarun Wadekar msr actlr_el2, x0 10108438e24SVarun Wadekar isb 10208438e24SVarun Wadekar 10308438e24SVarun Wadekar /* -------------------------------- 10408438e24SVarun Wadekar * Enable the cycle count register 10508438e24SVarun Wadekar * -------------------------------- 10608438e24SVarun Wadekar */ 1070cd6138dSVarun Wadekar1: mrs x0, pmcr_el0 10808438e24SVarun Wadekar ubfx x0, x0, #11, #5 // read PMCR.N field 10908438e24SVarun Wadekar mov x1, #1 11008438e24SVarun Wadekar lsl x0, x1, x0 11108438e24SVarun Wadekar sub x0, x0, #1 // mask of event counters 11208438e24SVarun Wadekar orr x0, x0, #0x80000000 // disable overflow intrs 11308438e24SVarun Wadekar msr pmintenclr_el1, x0 11408438e24SVarun Wadekar msr pmuserenr_el0, x1 // enable user mode access 11508438e24SVarun Wadekar 11608438e24SVarun Wadekar /* ---------------------------------------------------------------- 11708438e24SVarun Wadekar * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count 11808438e24SVarun Wadekar * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ 11908438e24SVarun Wadekar * registers from EL0. 12008438e24SVarun Wadekar * ---------------------------------------------------------------- 12108438e24SVarun Wadekar */ 12208438e24SVarun Wadekar mrs x0, cntkctl_el1 12308438e24SVarun Wadekar orr x0, x0, #EL0VCTEN_BIT 12408438e24SVarun Wadekar msr cntkctl_el1, x0 12508438e24SVarun Wadekar.endm 12608438e24SVarun Wadekar 12708438e24SVarun Wadekar /* ----------------------------------------------------- 128*96d07af4SVarun Wadekar * bool plat_is_my_cpu_primary(void); 12908438e24SVarun Wadekar * 13008438e24SVarun Wadekar * This function checks if this is the Primary CPU 131*96d07af4SVarun Wadekar * 132*96d07af4SVarun Wadekar * Registers clobbered: x0, x1 13308438e24SVarun Wadekar * ----------------------------------------------------- 13408438e24SVarun Wadekar */ 13571cb26eaSVarun Wadekarfunc plat_is_my_cpu_primary 13671cb26eaSVarun Wadekar mrs x0, mpidr_el1 137*96d07af4SVarun Wadekar adr x1, tegra_primary_cpu_mpid 138*96d07af4SVarun Wadekar ldr x1, [x1] 139*96d07af4SVarun Wadekar cmp x0, x1 14008438e24SVarun Wadekar cset x0, eq 14108438e24SVarun Wadekar ret 14271cb26eaSVarun Wadekarendfunc plat_is_my_cpu_primary 14308438e24SVarun Wadekar 144b627d083SVarun Wadekar /* ---------------------------------------------------------- 14571cb26eaSVarun Wadekar * unsigned int plat_my_core_pos(void); 14608438e24SVarun Wadekar * 147b627d083SVarun Wadekar * result: CorePos = CoreId + (ClusterId * cpus per cluster) 1483bab03ebSKalyani Chidambaram * Registers clobbered: x0, x8 149b627d083SVarun Wadekar * ---------------------------------------------------------- 15008438e24SVarun Wadekar */ 15171cb26eaSVarun Wadekarfunc plat_my_core_pos 1523bab03ebSKalyani Chidambaram mov x8, x30 15371cb26eaSVarun Wadekar mrs x0, mpidr_el1 1543bab03ebSKalyani Chidambaram bl plat_core_pos_by_mpidr 1553bab03ebSKalyani Chidambaram ret x8 15671cb26eaSVarun Wadekarendfunc plat_my_core_pos 15771cb26eaSVarun Wadekar 15871cb26eaSVarun Wadekar /* ----------------------------------------------------- 15971cb26eaSVarun Wadekar * unsigned long plat_get_my_entrypoint (void); 16071cb26eaSVarun Wadekar * 16171cb26eaSVarun Wadekar * Main job of this routine is to distinguish between 16271cb26eaSVarun Wadekar * a cold and warm boot. If the tegra_sec_entry_point for 16371cb26eaSVarun Wadekar * this CPU is present, then it's a warm boot. 16471cb26eaSVarun Wadekar * 16571cb26eaSVarun Wadekar * ----------------------------------------------------- 16671cb26eaSVarun Wadekar */ 16771cb26eaSVarun Wadekarfunc plat_get_my_entrypoint 16871cb26eaSVarun Wadekar adr x1, tegra_sec_entry_point 16971cb26eaSVarun Wadekar ldr x0, [x1] 17071cb26eaSVarun Wadekar ret 17171cb26eaSVarun Wadekarendfunc plat_get_my_entrypoint 17208438e24SVarun Wadekar 17308438e24SVarun Wadekar /* ----------------------------------------------------- 17408438e24SVarun Wadekar * void plat_secondary_cold_boot_setup (void); 17508438e24SVarun Wadekar * 17608438e24SVarun Wadekar * This function performs any platform specific actions 17708438e24SVarun Wadekar * needed for a secondary cpu after a cold reset. Right 17808438e24SVarun Wadekar * now this is a stub function. 17908438e24SVarun Wadekar * ----------------------------------------------------- 18008438e24SVarun Wadekar */ 18108438e24SVarun Wadekarfunc plat_secondary_cold_boot_setup 18208438e24SVarun Wadekar mov x0, #0 18308438e24SVarun Wadekar ret 18408438e24SVarun Wadekarendfunc plat_secondary_cold_boot_setup 18508438e24SVarun Wadekar 18608438e24SVarun Wadekar /* -------------------------------------------------------- 18708438e24SVarun Wadekar * void platform_mem_init (void); 18808438e24SVarun Wadekar * 18908438e24SVarun Wadekar * Any memory init, relocation to be done before the 19008438e24SVarun Wadekar * platform boots. Called very early in the boot process. 19108438e24SVarun Wadekar * -------------------------------------------------------- 19208438e24SVarun Wadekar */ 19308438e24SVarun Wadekarfunc platform_mem_init 19408438e24SVarun Wadekar mov x0, #0 19508438e24SVarun Wadekar ret 19608438e24SVarun Wadekarendfunc platform_mem_init 19708438e24SVarun Wadekar 19808438e24SVarun Wadekar /* --------------------------------------------------- 19908438e24SVarun Wadekar * Function to handle a platform reset and store 20008438e24SVarun Wadekar * input parameters passed by BL2. 20108438e24SVarun Wadekar * --------------------------------------------------- 20208438e24SVarun Wadekar */ 20308438e24SVarun Wadekarfunc plat_reset_handler 20408438e24SVarun Wadekar 205939dcf25SVarun Wadekar /* ---------------------------------------------------- 206939dcf25SVarun Wadekar * Verify if we are running from BL31_BASE address 207939dcf25SVarun Wadekar * ---------------------------------------------------- 208939dcf25SVarun Wadekar */ 209939dcf25SVarun Wadekar adr x18, bl31_entrypoint 210939dcf25SVarun Wadekar mov x17, #BL31_BASE 211939dcf25SVarun Wadekar cmp x18, x17 212939dcf25SVarun Wadekar b.eq 1f 213939dcf25SVarun Wadekar 214939dcf25SVarun Wadekar /* ---------------------------------------------------- 215939dcf25SVarun Wadekar * Copy the entire BL31 code to BL31_BASE if we are not 216939dcf25SVarun Wadekar * running from it already 217939dcf25SVarun Wadekar * ---------------------------------------------------- 218939dcf25SVarun Wadekar */ 219939dcf25SVarun Wadekar mov x0, x17 220939dcf25SVarun Wadekar mov x1, x18 221a565d16cSanzhou adr x2, __RELA_END__ 222a565d16cSanzhou sub x2, x2, x18 223939dcf25SVarun Wadekar_loop16: 224939dcf25SVarun Wadekar cmp x2, #16 225768baf6eSDouglas Raillard b.lo _loop1 226939dcf25SVarun Wadekar ldp x3, x4, [x1], #16 227939dcf25SVarun Wadekar stp x3, x4, [x0], #16 228939dcf25SVarun Wadekar sub x2, x2, #16 229939dcf25SVarun Wadekar b _loop16 230939dcf25SVarun Wadekar /* copy byte per byte */ 231939dcf25SVarun Wadekar_loop1: 232939dcf25SVarun Wadekar cbz x2, _end 233939dcf25SVarun Wadekar ldrb w3, [x1], #1 234939dcf25SVarun Wadekar strb w3, [x0], #1 235939dcf25SVarun Wadekar subs x2, x2, #1 236939dcf25SVarun Wadekar b.ne _loop1 237939dcf25SVarun Wadekar 238939dcf25SVarun Wadekar /* ---------------------------------------------------- 239939dcf25SVarun Wadekar * Jump to BL31_BASE and start execution again 240939dcf25SVarun Wadekar * ---------------------------------------------------- 241939dcf25SVarun Wadekar */ 242939dcf25SVarun Wadekar_end: mov x0, x20 243939dcf25SVarun Wadekar mov x1, x21 244939dcf25SVarun Wadekar br x17 245939dcf25SVarun Wadekar1: 246939dcf25SVarun Wadekar 24708438e24SVarun Wadekar /* ----------------------------------- 24808438e24SVarun Wadekar * derive and save the phys_base addr 24908438e24SVarun Wadekar * ----------------------------------- 25008438e24SVarun Wadekar */ 25108438e24SVarun Wadekar adr x17, tegra_bl31_phys_base 25208438e24SVarun Wadekar ldr x18, [x17] 25308438e24SVarun Wadekar cbnz x18, 1f 25408438e24SVarun Wadekar adr x18, bl31_entrypoint 25508438e24SVarun Wadekar str x18, [x17] 25608438e24SVarun Wadekar 257*96d07af4SVarun Wadekar /* ----------------------------------- 258*96d07af4SVarun Wadekar * save the boot CPU MPID value 259*96d07af4SVarun Wadekar * ----------------------------------- 260*96d07af4SVarun Wadekar */ 261*96d07af4SVarun Wadekar mrs x0, mpidr_el1 262*96d07af4SVarun Wadekar adr x1, tegra_primary_cpu_mpid 263*96d07af4SVarun Wadekar str x0, [x1] 264*96d07af4SVarun Wadekar 26508438e24SVarun Wadekar1: cpu_init_common 26608438e24SVarun Wadekar 26708438e24SVarun Wadekar ret 26808438e24SVarun Wadekarendfunc plat_reset_handler 26908438e24SVarun Wadekar 2700ac1bf72SVarun Wadekar /* ------------------------------------------------------ 2710ac1bf72SVarun Wadekar * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 2720ac1bf72SVarun Wadekar * 2730ac1bf72SVarun Wadekar * This function implements a part of the critical 2740ac1bf72SVarun Wadekar * interface between the psci generic layer and the 2750ac1bf72SVarun Wadekar * platform that allows the former to query the platform 2760ac1bf72SVarun Wadekar * to convert an MPIDR to a unique linear index. An error 2770ac1bf72SVarun Wadekar * code (-1) is returned in case the MPIDR is invalid. 2780ac1bf72SVarun Wadekar * 2790ac1bf72SVarun Wadekar * Clobbers: x0-x3 2800ac1bf72SVarun Wadekar * ------------------------------------------------------ 2810ac1bf72SVarun Wadekar */ 2820ac1bf72SVarun Wadekarfunc plat_core_pos_by_mpidr 2830ac1bf72SVarun Wadekar lsr x1, x0, #MPIDR_AFF0_SHIFT 2840ac1bf72SVarun Wadekar and x1, x1, #MPIDR_AFFLVL_MASK /* core id */ 2850ac1bf72SVarun Wadekar lsr x2, x0, #MPIDR_AFF1_SHIFT 2860ac1bf72SVarun Wadekar and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */ 2870ac1bf72SVarun Wadekar 2880ac1bf72SVarun Wadekar /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */ 2890ac1bf72SVarun Wadekar mov x0, #-1 2900ac1bf72SVarun Wadekar cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1) 2910ac1bf72SVarun Wadekar b.gt 1f 2920ac1bf72SVarun Wadekar 2930ac1bf72SVarun Wadekar /* cluster_id >= PLATFORM_CLUSTER_COUNT */ 2940ac1bf72SVarun Wadekar cmp x2, #(PLATFORM_CLUSTER_COUNT - 1) 2950ac1bf72SVarun Wadekar b.gt 1f 2960ac1bf72SVarun Wadekar 2970ac1bf72SVarun Wadekar /* CorePos = CoreId + (ClusterId * cpus per cluster) */ 2980ac1bf72SVarun Wadekar mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER 2990ac1bf72SVarun Wadekar mul x3, x3, x2 3000ac1bf72SVarun Wadekar add x0, x1, x3 3010ac1bf72SVarun Wadekar 3020ac1bf72SVarun Wadekar1: 3030ac1bf72SVarun Wadekar ret 3040ac1bf72SVarun Wadekarendfunc plat_core_pos_by_mpidr 3050ac1bf72SVarun Wadekar 30608438e24SVarun Wadekar /* ---------------------------------------- 30708438e24SVarun Wadekar * Secure entrypoint function for CPU boot 30808438e24SVarun Wadekar * ---------------------------------------- 30908438e24SVarun Wadekar */ 31064726e6dSJulius Wernerfunc tegra_secure_entrypoint _align=6 31108438e24SVarun Wadekar 31208438e24SVarun Wadekar#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT 31308438e24SVarun Wadekar 314c195fec6SHarvey Hsieh /* -------------------------------------------------------- 315c195fec6SHarvey Hsieh * Skip the invalidate BTB workaround for Tegra210B01 SKUs. 316c195fec6SHarvey Hsieh * -------------------------------------------------------- 317c195fec6SHarvey Hsieh */ 318c195fec6SHarvey Hsieh mov x0, #TEGRA_MISC_BASE 319c195fec6SHarvey Hsieh add x0, x0, #HARDWARE_REVISION_OFFSET 320c195fec6SHarvey Hsieh ldr w1, [x0] 321c195fec6SHarvey Hsieh lsr w1, w1, #CHIP_ID_SHIFT 322c195fec6SHarvey Hsieh and w1, w1, #CHIP_ID_MASK 323c195fec6SHarvey Hsieh cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ 324c195fec6SHarvey Hsieh b.ne 2f 325c195fec6SHarvey Hsieh ldr w1, [x0] 326c195fec6SHarvey Hsieh lsr w1, w1, #MAJOR_VERSION_SHIFT 327c195fec6SHarvey Hsieh and w1, w1, #MAJOR_VERSION_MASK 328c195fec6SHarvey Hsieh cmp w1, #0x02 /* T210 B01? */ 329c195fec6SHarvey Hsieh b.eq 2f 330c195fec6SHarvey Hsieh 33108438e24SVarun Wadekar /* ------------------------------------------------------- 33208438e24SVarun Wadekar * Invalidate BTB along with I$ to remove any stale 33308438e24SVarun Wadekar * entries from the branch predictor array. 33408438e24SVarun Wadekar * ------------------------------------------------------- 33508438e24SVarun Wadekar */ 336d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 33708438e24SVarun Wadekar orr x0, x0, #1 338d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ 33908438e24SVarun Wadekar dsb sy 34008438e24SVarun Wadekar isb 34108438e24SVarun Wadekar ic iallu /* actual invalidate */ 34208438e24SVarun Wadekar dsb sy 34308438e24SVarun Wadekar isb 34408438e24SVarun Wadekar 345d0e1094eSEleanor Bonnici mrs x0, CORTEX_A57_CPUACTLR_EL1 34608438e24SVarun Wadekar bic x0, x0, #1 347d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ 34808438e24SVarun Wadekar dsb sy 34908438e24SVarun Wadekar isb 35008438e24SVarun Wadekar 35108438e24SVarun Wadekar .rept 7 35208438e24SVarun Wadekar nop /* wait */ 35308438e24SVarun Wadekar .endr 35408438e24SVarun Wadekar 35508438e24SVarun Wadekar /* ----------------------------------------------- 35608438e24SVarun Wadekar * Extract OSLK bit and check if it is '1'. This 35708438e24SVarun Wadekar * bit remains '0' for A53 on warm-resets. If '1', 35808438e24SVarun Wadekar * turn off regional clock gating and request warm 35908438e24SVarun Wadekar * reset. 36008438e24SVarun Wadekar * ----------------------------------------------- 36108438e24SVarun Wadekar */ 36208438e24SVarun Wadekar mrs x0, oslsr_el1 36308438e24SVarun Wadekar and x0, x0, #2 36408438e24SVarun Wadekar mrs x1, mpidr_el1 36508438e24SVarun Wadekar bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ 36608438e24SVarun Wadekar b.eq restore_oslock 36708438e24SVarun Wadekar mov x0, xzr 36808438e24SVarun Wadekar msr oslar_el1, x0 /* os lock stays 0 across warm reset */ 36908438e24SVarun Wadekar mov x3, #3 37008438e24SVarun Wadekar movz x4, #0x8000, lsl #48 371d0e1094eSEleanor Bonnici msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ 37208438e24SVarun Wadekar isb 37308438e24SVarun Wadekar msr rmr_el3, x3 /* request warm reset */ 37408438e24SVarun Wadekar isb 37508438e24SVarun Wadekar dsb sy 37608438e24SVarun Wadekar1: wfi 37708438e24SVarun Wadekar b 1b 37808438e24SVarun Wadekar 37908438e24SVarun Wadekar /* -------------------------------------------------- 38008438e24SVarun Wadekar * These nops are here so that speculative execution 38108438e24SVarun Wadekar * won't harm us before we are done with warm reset. 38208438e24SVarun Wadekar * -------------------------------------------------- 38308438e24SVarun Wadekar */ 38408438e24SVarun Wadekar .rept 65 38508438e24SVarun Wadekar nop 38608438e24SVarun Wadekar .endr 387c195fec6SHarvey Hsieh2: 38808438e24SVarun Wadekar /* -------------------------------------------------- 38908438e24SVarun Wadekar * Do not insert instructions here 39008438e24SVarun Wadekar * -------------------------------------------------- 39108438e24SVarun Wadekar */ 39208438e24SVarun Wadekar#endif 39308438e24SVarun Wadekar 39408438e24SVarun Wadekar /* -------------------------------------------------- 39508438e24SVarun Wadekar * Restore OS Lock bit 39608438e24SVarun Wadekar * -------------------------------------------------- 39708438e24SVarun Wadekar */ 39808438e24SVarun Wadekarrestore_oslock: 39908438e24SVarun Wadekar mov x0, #1 40008438e24SVarun Wadekar msr oslar_el1, x0 40108438e24SVarun Wadekar 40208438e24SVarun Wadekar /* -------------------------------------------------- 40308438e24SVarun Wadekar * Get secure world's entry point and jump to it 40408438e24SVarun Wadekar * -------------------------------------------------- 40508438e24SVarun Wadekar */ 40671cb26eaSVarun Wadekar bl plat_get_my_entrypoint 40708438e24SVarun Wadekar br x0 40808438e24SVarun Wadekarendfunc tegra_secure_entrypoint 40908438e24SVarun Wadekar 41008438e24SVarun Wadekar .data 41108438e24SVarun Wadekar .align 3 41208438e24SVarun Wadekar 41308438e24SVarun Wadekar /* -------------------------------------------------- 41471cb26eaSVarun Wadekar * CPU Secure entry point - resume from suspend 41508438e24SVarun Wadekar * -------------------------------------------------- 41608438e24SVarun Wadekar */ 41771cb26eaSVarun Wadekartegra_sec_entry_point: 41808438e24SVarun Wadekar .quad 0 41908438e24SVarun Wadekar 42008438e24SVarun Wadekar /* -------------------------------------------------- 42108438e24SVarun Wadekar * NS world's cold boot entry point 42208438e24SVarun Wadekar * -------------------------------------------------- 42308438e24SVarun Wadekar */ 42408438e24SVarun Wadekarns_image_entrypoint: 42508438e24SVarun Wadekar .quad 0 42608438e24SVarun Wadekar 42708438e24SVarun Wadekar /* -------------------------------------------------- 42808438e24SVarun Wadekar * BL31's physical base address 42908438e24SVarun Wadekar * -------------------------------------------------- 43008438e24SVarun Wadekar */ 43108438e24SVarun Wadekartegra_bl31_phys_base: 43208438e24SVarun Wadekar .quad 0 433e1084216SVarun Wadekar 434e1084216SVarun Wadekar /* -------------------------------------------------- 435e1084216SVarun Wadekar * UART controller base for console init 436e1084216SVarun Wadekar * -------------------------------------------------- 437e1084216SVarun Wadekar */ 438e1084216SVarun Wadekartegra_console_base: 439e1084216SVarun Wadekar .quad 0 440*96d07af4SVarun Wadekar 441*96d07af4SVarun Wadekar /* -------------------------------------------------- 442*96d07af4SVarun Wadekar * MPID value for the boot CPU 443*96d07af4SVarun Wadekar * -------------------------------------------------- 444*96d07af4SVarun Wadekar */ 445*96d07af4SVarun Wadekartegra_primary_cpu_mpid: 446*96d07af4SVarun Wadekar .quad 0 447