1/* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10 11 12 .globl bl2_entrypoint 13 14 15 16func bl2_entrypoint 17 /*--------------------------------------------- 18 * Save arguments x0 - x3 from BL1 for future 19 * use. 20 * --------------------------------------------- 21 */ 22 mov x20, x0 23 mov x21, x1 24 mov x22, x2 25 mov x23, x3 26 27 /* --------------------------------------------- 28 * Set the exception vector to something sane. 29 * --------------------------------------------- 30 */ 31 adr x0, early_exceptions 32 msr vbar_el1, x0 33 isb 34 35 /* --------------------------------------------- 36 * Enable the SError interrupt now that the 37 * exception vectors have been setup. 38 * --------------------------------------------- 39 */ 40 msr daifclr, #DAIF_ABT_BIT 41 42 /* --------------------------------------------- 43 * Enable the instruction cache, stack pointer 44 * and data access alignment checks and disable 45 * speculative loads. 46 * --------------------------------------------- 47 */ 48 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 49 mrs x0, sctlr_el1 50 orr x0, x0, x1 51#if ENABLE_BTI 52 /* Enable PAC branch type compatibility */ 53 bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT) 54#endif 55 bic x0, x0, #SCTLR_DSSBS_BIT 56 msr sctlr_el1, x0 57 isb 58 59 /* --------------------------------------------- 60 * Invalidate the RW memory used by the BL2 61 * image. This includes the data and NOBITS 62 * sections. This is done to safeguard against 63 * possible corruption of this memory by dirty 64 * cache lines in a system cache as a result of 65 * use by an earlier boot loader stage. 66 * --------------------------------------------- 67 */ 68 adr x0, __RW_START__ 69 adr x1, __RW_END__ 70 sub x1, x1, x0 71 bl inv_dcache_range 72 73 /* --------------------------------------------- 74 * Zero out NOBITS sections. There are 2 of them: 75 * - the .bss section; 76 * - the coherent memory section. 77 * --------------------------------------------- 78 */ 79 adrp x0, __BSS_START__ 80 add x0, x0, :lo12:__BSS_START__ 81 adrp x1, __BSS_END__ 82 add x1, x1, :lo12:__BSS_END__ 83 sub x1, x1, x0 84 bl zeromem 85 86#if USE_COHERENT_MEM 87 adrp x0, __COHERENT_RAM_START__ 88 add x0, x0, :lo12:__COHERENT_RAM_START__ 89 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 90 add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__ 91 sub x1, x1, x0 92 bl zeromem 93#endif 94 95 /* -------------------------------------------- 96 * Allocate a stack whose memory will be marked 97 * as Normal-IS-WBWA when the MMU is enabled. 98 * There is no risk of reading stale stack 99 * memory after enabling the MMU as only the 100 * primary cpu is running at the moment. 101 * -------------------------------------------- 102 */ 103 bl plat_set_my_stack 104 105 /* --------------------------------------------- 106 * Initialize the stack protector canary before 107 * any C code is called. 108 * --------------------------------------------- 109 */ 110#if STACK_PROTECTOR_ENABLED 111 bl update_stack_protector_canary 112#endif 113 114 /* --------------------------------------------- 115 * Perform BL2 setup 116 * --------------------------------------------- 117 */ 118 mov x0, x20 119 mov x1, x21 120 mov x2, x22 121 mov x3, x23 122 123 /* --------------------------------------------- 124 * Jump to main function. 125 * --------------------------------------------- 126 */ 127 bl bl2_main 128 129 /* --------------------------------------------- 130 * Should never reach this point. 131 * --------------------------------------------- 132 */ 133 no_ret plat_panic_handler 134 135endfunc bl2_entrypoint 136