Lines Matching refs:x0
64 mrs x0, midr_el1
66 and x0, x0, x1
67 lsr x0, x0, #MIDR_PN_SHIFT
68 cmp x0, #MIDR_PN_CORTEX_A57
75 mrs x0, CORTEX_A57_L2ECTLR_EL1
77 bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
78 orr x0, x0, x1
79 msr CORTEX_A57_L2ECTLR_EL1, x0
82 mrs x0, CORTEX_A57_ECTLR_EL1
84 bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
85 orr x0, x0, x1
86 msr CORTEX_A57_ECTLR_EL1, x0
93 mrs x0, actlr_el3
95 orr x0, x0, x1
96 msr actlr_el3, x0
97 mrs x0, actlr_el2
99 orr x0, x0, x1
100 msr actlr_el2, x0
107 1: mrs x0, pmcr_el0
108 ubfx x0, x0, #11, #5 // read PMCR.N field
110 lsl x0, x1, x0
111 sub x0, x0, #1 // mask of event counters
112 orr x0, x0, #0x80000000 // disable overflow intrs
113 msr pmintenclr_el1, x0
122 mrs x0, cntkctl_el1
123 orr x0, x0, #EL0VCTEN_BIT
124 msr cntkctl_el1, x0
136 mrs x0, mpidr_el1
139 cmp x0, x1
140 cset x0, eq
153 mrs x0, mpidr_el1
169 ldr x0, [x1]
182 mov x0, #0
194 mov x0, #0
219 mov x0, x17
227 stp x3, x4, [x0], #16
234 strb w3, [x0], #1
242 _end: mov x0, x20
261 mrs x0, mpidr_el1
263 str x0, [x1]
283 lsr x1, x0, #MPIDR_AFF0_SHIFT
285 lsr x2, x0, #MPIDR_AFF1_SHIFT
289 mov x0, #-1
300 add x0, x1, x3
318 mov x0, #TEGRA_MISC_BASE
319 add x0, x0, #HARDWARE_REVISION_OFFSET
320 ldr w1, [x0]
325 ldr w1, [x0]
336 mrs x0, CORTEX_A57_CPUACTLR_EL1
337 orr x0, x0, #1
338 msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
345 mrs x0, CORTEX_A57_CPUACTLR_EL1
346 bic x0, x0, #1
362 mrs x0, oslsr_el1
363 and x0, x0, #2
365 bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */
367 mov x0, xzr
368 msr oslar_el1, x0 /* os lock stays 0 across warm reset */
399 mov x0, #1
400 msr oslar_el1, x0
407 br x0