Lines Matching refs:x0
33 ldr x0, =0x0
34 msr NEOVERSE_V1_CPUPSELR_EL3, x0
35 ldr x0, = 0xEE070F14
36 msr NEOVERSE_V1_CPUPOR_EL3, x0
37 ldr x0, = 0xFFFF0FFF
38 msr NEOVERSE_V1_CPUPMR_EL3, x0
39 ldr x0, =0x4005027FF
40 msr NEOVERSE_V1_CPUPCR_EL3, x0
43 ldr x0, =0x1
44 msr NEOVERSE_V1_CPUPSELR_EL3, x0
45 ldr x0, =0x00e8400000
46 msr NEOVERSE_V1_CPUPOR_EL3, x0
47 ldr x0, =0x00fff00000
48 msr NEOVERSE_V1_CPUPMR_EL3, x0
49 ldr x0, = 0x4001027FF
50 msr NEOVERSE_V1_CPUPCR_EL3, x0
53 ldr x0, =0x2
54 msr NEOVERSE_V1_CPUPSELR_EL3, x0
55 ldr x0, =0x00e8c00040
56 msr NEOVERSE_V1_CPUPOR_EL3, x0
57 ldr x0, =0x00fff00040
58 msr NEOVERSE_V1_CPUPMR_EL3, x0
59 ldr x0, = 0x4001027FF
60 msr NEOVERSE_V1_CPUPCR_EL3, x0
63 ldr x0, =0x3
64 msr NEOVERSE_V1_CPUPSELR_EL3, x0
65 ldr x0, =0x00e8400000
66 msr NEOVERSE_V1_CPUPOR_EL3, x0
67 ldr x0, =0x00fff00000
68 msr NEOVERSE_V1_CPUPMR_EL3, x0
69 ldr x0, = 0x4004027FF
70 msr NEOVERSE_V1_CPUPCR_EL3, x0
73 ldr x0, =0x4
74 msr NEOVERSE_V1_CPUPSELR_EL3, x0
75 ldr x0, =0x00e8c00040
76 msr NEOVERSE_V1_CPUPOR_EL3, x0
77 ldr x0, =0x00fff00040
78 msr NEOVERSE_V1_CPUPMR_EL3, x0
79 ldr x0, = 0x4004027FF
80 msr NEOVERSE_V1_CPUPCR_EL3, x0
115 mov x0, #0
116 msr S3_6_C15_C8_0, x0
117 ldr x0, =0x10E3900002
118 msr S3_6_C15_C8_2, x0
119 ldr x0, =0x10FFF00083
120 msr S3_6_C15_C8_3, x0
121 ldr x0, =0x2001003FF
122 msr S3_6_C15_C8_1, x0
124 mov x0, #1
125 msr S3_6_C15_C8_0, x0
126 ldr x0, =0x10E3800082
127 msr S3_6_C15_C8_2, x0
128 ldr x0, =0x10FFF00083
129 msr S3_6_C15_C8_3, x0
130 ldr x0, =0x2001003FF
131 msr S3_6_C15_C8_1, x0
133 mov x0, #2
134 msr S3_6_C15_C8_0, x0
135 ldr x0, =0x10E3800200
136 msr S3_6_C15_C8_2, x0
137 ldr x0, =0x10FFF003E0
138 msr S3_6_C15_C8_3, x0
139 ldr x0, =0x2001003FF
140 msr S3_6_C15_C8_1, x0
147 mov x0, #0x3
148 msr S3_6_C15_C8_0, x0
149 ldr x0, =0xEE010F12
150 msr S3_6_C15_C8_2, x0
151 ldr x0, =0xFFFF0FFF
152 msr S3_6_C15_C8_3, x0
153 ldr x0, =0x80000000003FF
154 msr S3_6_C15_C8_1, x0
160 mov x0, #0x3
161 msr S3_6_C15_C8_0, x0
162 ldr x0, =0xEE720F14
163 msr S3_6_C15_C8_2, x0
164 ldr x0, =0xFFFF0FDF
165 msr S3_6_C15_C8_3, x0
166 ldr x0, =0x40000005003FF
167 msr S3_6_C15_C8_1, x0
173 ldr x0, =0x5
174 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
175 ldr x0, =0x10F600E000
176 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
177 ldr x0, =0x10FF80E000
178 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
179 ldr x0, =0x80000000003FF
180 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */